Re: [U-Boot] [PATCH v3 05/11] spi: cadence_qspi: Clean up the #define names

[Jagan Teki]

On Tue, Nov 29, 2016 at 6:28 PM, Phil Edworthy
 wrote:
> A lot of the #defines are for single bits in a register, where the
> name has _MASK on the end. Since this can be used for both a mask
> and the value, remove _MASK from them.
>
> Whilst doing so, also remove the unnecessary brackets around the
> constants.
>
> Signed-off-by: Phil Edworthy 
> Acked-by: Marek Vasut 

Reviewed-by: Jagan Teki 

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
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[U-Boot] [PATCH v3 05/11] spi: cadence_qspi: Clean up the #define names

[Phil Edworthy]

A lot of the #defines are for single bits in a register, where the
name has _MASK on the end. Since this can be used for both a mask
and the value, remove _MASK from them.

Whilst doing so, also remove the unnecessary brackets around the
constants.

Signed-off-by: Phil Edworthy 
Acked-by: Marek Vasut 
---
 v3:
  - No change.
 v2:
  - No change.
---
 drivers/spi/cadence_qspi_apb.c | 86 +-
 1 file changed, 43 insertions(+), 43 deletions(-)

diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index b41f36b..634a857 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -32,37 +32,37 @@
 #include 
 #include "cadence_qspi.h"
 
-#define CQSPI_REG_POLL_US  (1) /* 1us */
-#define CQSPI_REG_RETRY(1)
-#define CQSPI_POLL_IDLE_RETRY  (3)
+#define CQSPI_REG_POLL_US  1 /* 1us */
+#define CQSPI_REG_RETRY1
+#define CQSPI_POLL_IDLE_RETRY  3
 
-#define CQSPI_FIFO_WIDTH   (4)
+#define CQSPI_FIFO_WIDTH   4
 
-#define CQSPI_REG_SRAM_THRESHOLD_WORDS (50)
+#define CQSPI_REG_SRAM_THRESHOLD_WORDS 50
 
 /* Transfer mode */
-#define CQSPI_INST_TYPE_SINGLE (0)
-#define CQSPI_INST_TYPE_DUAL   (1)
-#define CQSPI_INST_TYPE_QUAD   (2)
+#define CQSPI_INST_TYPE_SINGLE 0
+#define CQSPI_INST_TYPE_DUAL   1
+#define CQSPI_INST_TYPE_QUAD   2
 
-#define CQSPI_STIG_DATA_LEN_MAX(8)
-
-#define CQSPI_DUMMY_CLKS_PER_BYTE  (8)
-#define CQSPI_DUMMY_BYTES_MAX  (4)
+#define CQSPI_STIG_DATA_LEN_MAX8
 
+#define CQSPI_DUMMY_CLKS_PER_BYTE  8
+#define CQSPI_DUMMY_BYTES_MAX  4
 
 #define CQSPI_REG_SRAM_FILL_THRESHOLD  \
((CQSPI_REG_SRAM_SIZE_WORD / 2) * CQSPI_FIFO_WIDTH)
+
 /
  * Controller's configuration and status register (offset from QSPI_BASE)
  /
 #defineCQSPI_REG_CONFIG0x00
-#defineCQSPI_REG_CONFIG_ENABLE_MASKBIT(0)
+#defineCQSPI_REG_CONFIG_ENABLE BIT(0)
 #defineCQSPI_REG_CONFIG_CLK_POLBIT(1)
 #defineCQSPI_REG_CONFIG_CLK_PHABIT(2)
-#defineCQSPI_REG_CONFIG_DIRECT_MASKBIT(7)
-#defineCQSPI_REG_CONFIG_DECODE_MASKBIT(9)
-#defineCQSPI_REG_CONFIG_XIP_IMM_MASK   BIT(18)
+#defineCQSPI_REG_CONFIG_DIRECT BIT(7)
+#defineCQSPI_REG_CONFIG_DECODE BIT(9)
+#defineCQSPI_REG_CONFIG_XIP_IMMBIT(18)
 #defineCQSPI_REG_CONFIG_CHIPSELECT_LSB 10
 #defineCQSPI_REG_CONFIG_BAUD_LSB   19
 #defineCQSPI_REG_CONFIG_IDLE_LSB   31
@@ -123,18 +123,18 @@
 #defineCQSPI_REG_IRQMASK   0x44
 
 #defineCQSPI_REG_INDIRECTRD0x60
-#defineCQSPI_REG_INDIRECTRD_START_MASK BIT(0)
-#defineCQSPI_REG_INDIRECTRD_CANCEL_MASKBIT(1)
-#defineCQSPI_REG_INDIRECTRD_INPROGRESS_MASKBIT(2)
-#defineCQSPI_REG_INDIRECTRD_DONE_MASK  BIT(5)
+#defineCQSPI_REG_INDIRECTRD_START  BIT(0)
+#defineCQSPI_REG_INDIRECTRD_CANCEL BIT(1)
+#defineCQSPI_REG_INDIRECTRD_INPROGRESS BIT(2)
+#defineCQSPI_REG_INDIRECTRD_DONE   BIT(5)
 
 #defineCQSPI_REG_INDIRECTRDWATERMARK   0x64
 #defineCQSPI_REG_INDIRECTRDSTARTADDR   0x68
 #defineCQSPI_REG_INDIRECTRDBYTES   0x6C
 
 #defineCQSPI_REG_CMDCTRL   0x90
-#defineCQSPI_REG_CMDCTRL_EXECUTE_MASK  BIT(0)
-#defineCQSPI_REG_CMDCTRL_INPROGRESS_MASK   BIT(1)
+#defineCQSPI_REG_CMDCTRL_EXECUTE   BIT(0)
+#defineCQSPI_REG_CMDCTRL_INPROGRESSBIT(1)
 #defineCQSPI_REG_CMDCTRL_DUMMY_LSB 7
 #defineCQSPI_REG_CMDCTRL_WR_BYTES_LSB  12
 #defineCQSPI_REG_CMDCTRL_WR_EN_LSB 15
@@ -150,10 +150,10 @@
 #defineCQSPI_REG_CMDCTRL_OPCODE_MASK   0xFF
 
 #defineCQSPI_REG_INDIRECTWR0x70
-#defineCQSPI_REG_INDIRECTWR_START_MASK BIT(0)
-#defineCQSPI_REG_INDIRECTWR_CANCEL_MASKBIT(1)
-#defineCQSPI_REG_INDIRECTWR_INPROGRESS_MASKBIT(2)
-#defineCQSPI_REG_INDIRECTWR_DONE_MASK  BIT(5)
+#defineCQSPI_REG_INDIRECTWR_START  BIT(0)
+#define