Re: [U-Boot] [PATCH v3 39/45] net: mvpp2: Add GoP and NetC support for port 0 (SFI)

[Joe Hershberger]

On Mon, Mar 27, 2017 at 7:00 AM, Stefan Roese  wrote:
> This patch adds the GoP (Group of Ports) and NetC (Net Complex) setup to
> the Marvell mvpp2 ethernet driver for the missing port 0. This code is
> mostly copied from the Marvell U-Boot version and was written by Stefan
> Chulski. Please note that only SFI support have been added, as this
> is the only interface that this code has been tested with. XAUI and
> RXAUI support might follow at a later stage.
>
> Signed-off-by: Stefan Roese 
> Cc: Stefan Chulski 
> Cc: Kostya Porotchkin 
> Cc: Nadav Haklai 
> Cc: Joe Hershberger 

Acked-by: Joe Hershberger 
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v3 39/45] net: mvpp2: Add GoP and NetC support for port 0 (SFI)

[Stefan Roese]

This patch adds the GoP (Group of Ports) and NetC (Net Complex) setup to
the Marvell mvpp2 ethernet driver for the missing port 0. This code is
mostly copied from the Marvell U-Boot version and was written by Stefan
Chulski. Please note that only SFI support have been added, as this
is the only interface that this code has been tested with. XAUI and
RXAUI support might follow at a later stage.

Signed-off-by: Stefan Roese 
Cc: Stefan Chulski 
Cc: Kostya Porotchkin 
Cc: Nadav Haklai 
Cc: Joe Hershberger 
---
Changes in v3:
- Removed usage of mv_reset enum and used "int" type instead
- Changed "bool" enable / reset parameters to "int" type

Changes in v2:
- New patch

 drivers/net/mvpp2.c | 161 
 1 file changed, 161 insertions(+)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index e9637ca13d..10904b9dc5 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -3232,6 +3232,130 @@ static int gop_gpcs_reset(struct mvpp2_port *port, int 
reset)
return 0;
 }
 
+/* Set the internal mux's to the required PCS in the PI */
+static int gop_xpcs_mode(struct mvpp2_port *port, int num_of_lanes)
+{
+   u32 val;
+   int lane;
+
+   switch (num_of_lanes) {
+   case 1:
+   lane = 0;
+   break;
+   case 2:
+   lane = 1;
+   break;
+   case 4:
+   lane = 2;
+   break;
+   default:
+   return -1;
+   }
+
+   /* configure XG MAC mode */
+   val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
+   val &= ~MVPP22_XPCS_PCSMODE_OFFS;
+   val &= ~MVPP22_XPCS_LANEACTIVE_MASK;
+   val |= (2 * lane) << MVPP22_XPCS_LANEACTIVE_OFFS;
+   writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
+
+   return 0;
+}
+
+static int gop_mpcs_mode(struct mvpp2_port *port)
+{
+   u32 val;
+
+   /* configure PCS40G COMMON CONTROL */
+   val = readl(port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
+   val &= ~FORWARD_ERROR_CORRECTION_MASK;
+   writel(val, port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
+
+   /* configure PCS CLOCK RESET */
+   val = readl(port->priv->mpcs_base + PCS_CLOCK_RESET);
+   val &= ~CLK_DIVISION_RATIO_MASK;
+   val |= 1 << CLK_DIVISION_RATIO_OFFS;
+   writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
+
+   val &= ~CLK_DIV_PHASE_SET_MASK;
+   val |= MAC_CLK_RESET_MASK;
+   val |= RX_SD_CLK_RESET_MASK;
+   val |= TX_SD_CLK_RESET_MASK;
+   writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
+
+   return 0;
+}
+
+/* Set the internal mux's to the required MAC in the GOP */
+static int gop_xlg_mac_mode_cfg(struct mvpp2_port *port, int num_of_act_lanes)
+{
+   u32 val;
+
+   /* configure 10G MAC mode */
+   val = readl(port->base + MVPP22_XLG_CTRL0_REG);
+   val |= MVPP22_XLG_RX_FC_EN;
+   writel(val, port->base + MVPP22_XLG_CTRL0_REG);
+
+   val = readl(port->base + MVPP22_XLG_CTRL3_REG);
+   val &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
+   val |= MVPP22_XLG_CTRL3_MACMODESELECT_10GMAC;
+   writel(val, port->base + MVPP22_XLG_CTRL3_REG);
+
+   /* read - modify - write */
+   val = readl(port->base + MVPP22_XLG_CTRL4_REG);
+   val &= ~MVPP22_XLG_MODE_DMA_1G;
+   val |= MVPP22_XLG_FORWARD_PFC_EN;
+   val |= MVPP22_XLG_FORWARD_802_3X_FC_EN;
+   val &= ~MVPP22_XLG_EN_IDLE_CHECK_FOR_LINK;
+   writel(val, port->base + MVPP22_XLG_CTRL4_REG);
+
+   /* Jumbo frame support: 0x1400 * 2 = 0x2800 bytes */
+   val = readl(port->base + MVPP22_XLG_CTRL1_REG);
+   val &= ~MVPP22_XLG_MAX_RX_SIZE_MASK;
+   val |= 0x1400 << MVPP22_XLG_MAX_RX_SIZE_OFFS;
+   writel(val, port->base + MVPP22_XLG_CTRL1_REG);
+
+   /* unmask link change interrupt */
+   val = readl(port->base + MVPP22_XLG_INTERRUPT_MASK_REG);
+   val |= MVPP22_XLG_INTERRUPT_LINK_CHANGE;
+   val |= 1; /* unmask summary bit */
+   writel(val, port->base + MVPP22_XLG_INTERRUPT_MASK_REG);
+
+   return 0;
+}
+
+/* Set PCS to reset or exit from reset */
+static int gop_xpcs_reset(struct mvpp2_port *port, int reset)
+{
+   u32 val;
+
+   /* read - modify - write */
+   val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
+   if (reset)
+   val &= ~MVPP22_XPCS_PCSRESET;
+   else
+   val |= MVPP22_XPCS_PCSRESET;
+   writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
+
+   return 0;
+}
+
+/* Set the MAC to reset or exit from reset */
+static int gop_xlg_mac_reset(struct mvpp2_port *port, int reset)
+{
+   u32 val;
+
+   /* read - modify - write */
+   val = readl(port->base + MVPP22_XLG_CTRL0_REG);
+   if (reset)
+   val &= ~MVPP22_XLG_MAC_RESETN;
+   else
+   val