Re: [U-Boot] [PATCH v3 6/8] riscv: cache: Flush L2 cache before jump to linux

[Bin Meng]

On Wed, Aug 21, 2019 at 4:16 PM Andes  wrote:
>
> From: Rick Chen 
>
> Flush and disable L2 cache in dcache_disable()
> which will be called in cleanup_before_linux()
> before jump to linux.
>
> The sequence will be preferred as below:
> L1 flush -> L1 disable -> L2 flush -> L2 disable
>
> Signed-off-by: Rick Chen 
> Cc: KC Lin 
> ---
>  arch/riscv/cpu/ax25/cache.c | 17 +
>  1 file changed, 17 insertions(+)
>

Reviewed-by: Bin Meng 
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[U-Boot] [PATCH v3 6/8] riscv: cache: Flush L2 cache before jump to linux

[Andes]

From: Rick Chen 

Flush and disable L2 cache in dcache_disable()
which will be called in cleanup_before_linux()
before jump to linux.

The sequence will be preferred as below:
L1 flush -> L1 disable -> L2 flush -> L2 disable

Signed-off-by: Rick Chen 
Cc: KC Lin 
---
 arch/riscv/cpu/ax25/cache.c | 17 +
 1 file changed, 17 insertions(+)

diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c
index cd95058..8f5455e 100644
--- a/arch/riscv/cpu/ax25/cache.c
+++ b/arch/riscv/cpu/ax25/cache.c
@@ -5,6 +5,9 @@
  */
 
 #include 
+#include 
+#include 
+#include 
 
 void flush_dcache_all(void)
 {
@@ -59,11 +62,18 @@ void dcache_enable(void)
 {
 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 #ifdef CONFIG_RISCV_NDS_CACHE
+   struct udevice *dev = NULL;
+
asm volatile (
"csrr t1, mcache_ctl\n\t"
"ori t0, t1, 0x2\n\t"
"csrw mcache_ctl, t0\n\t"
);
+
+   uclass_find_first_device(UCLASS_CACHE, &dev);
+
+   if (dev)
+   cache_enable(dev);
 #endif
 #endif
 }
@@ -72,12 +82,19 @@ void dcache_disable(void)
 {
 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 #ifdef CONFIG_RISCV_NDS_CACHE
+   struct udevice *dev = NULL;
+
asm volatile (
"fence\n\t"
"csrr t1, mcache_ctl\n\t"
"andi t0, t1, ~0x2\n\t"
"csrw mcache_ctl, t0\n\t"
);
+
+   uclass_find_first_device(UCLASS_CACHE, &dev);
+
+   if (dev)
+   cache_disable(dev);
 #endif
 #endif
 }
-- 
2.7.4

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