Re: [U-Boot] [PATCH v4] arm: socfpga: Add SoCFPGA SR1500 board

[Pavel Machek]

On Wed 2015-11-18 11:06:09, Stefan Roese wrote:
> The SR1500 board is a CycloneV based board, similar to the EBV
> SoCrates, equipped with the following devices:
> 
> - SPI NOR
> - eMMC
> - Ethernet
> 
> Signed-off-by: Stefan Roese 
> Reviewed-by: Marek Vasut 

Acked-by: Pavel Machek 

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[U-Boot] [PATCH v4] arm: socfpga: Add SoCFPGA SR1500 board

[Stefan Roese]

The SR1500 board is a CycloneV based board, similar to the EBV
SoCrates, equipped with the following devices:

- SPI NOR
- eMMC
- Ethernet

Signed-off-by: Stefan Roese 
Reviewed-by: Marek Vasut 
Cc: Pavel Machek 
Cc: Dinh Nguyen 
---
v4:
- Really remove board specific commands

v3:
- Removed README.socfpga changes
- Removed board specific commands
- Change CONFIG_LOADADDR to 0x0100 as suggested by Dinh

v2:
- Addressed various review comments from Marek:
- Added chapter about SPL integration for SoC FPGA in doc/README.socfpga
- Delay after PHY reset deassertion added
- Reshuffle of the code for the PHY test code (fixes and cleanup)
- Cleanup of the board config header

 arch/arm/dts/Makefile|   4 +-
 arch/arm/dts/socfpga_cyclone5_sr1500.dts | 101 +
 arch/arm/mach-socfpga/Kconfig|   6 +
 board/sr1500/MAINTAINERS |   6 +
 board/sr1500/Makefile|   7 +
 board/sr1500/qts/iocsr_config.h  | 660 +++
 board/sr1500/qts/pinmux_config.h | 219 ++
 board/sr1500/qts/pll_config.h|  85 
 board/sr1500/qts/sdram_config.h  | 341 
 board/sr1500/socfpga.c   |  44 +++
 configs/socfpga_sr1500_defconfig |  17 +
 include/configs/socfpga_sr1500.h | 113 ++
 12 files changed, 1602 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/socfpga_cyclone5_sr1500.dts
 create mode 100644 board/sr1500/MAINTAINERS
 create mode 100644 board/sr1500/Makefile
 create mode 100644 board/sr1500/qts/iocsr_config.h
 create mode 100644 board/sr1500/qts/pinmux_config.h
 create mode 100644 board/sr1500/qts/pll_config.h
 create mode 100644 board/sr1500/qts/sdram_config.h
 create mode 100644 board/sr1500/socfpga.c
 create mode 100644 configs/socfpga_sr1500_defconfig
 create mode 100644 include/configs/socfpga_sr1500.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9542fff..82d68ce 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -80,7 +80,9 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_cyclone5_socdk.dtb  \
socfpga_cyclone5_de0_nano_soc.dtb   \
socfpga_cyclone5_sockit.dtb \
-   socfpga_cyclone5_socrates.dtb
+   socfpga_cyclone5_socrates.dtb   \
+   socfpga_cyclone5_sr1500.dtb
+
 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb
 dtb-$(CONFIG_TARGET_BEAGLE_X15) += am57xx-beagle-x15.dtb
 dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
diff --git a/arch/arm/dts/socfpga_cyclone5_sr1500.dts 
b/arch/arm/dts/socfpga_cyclone5_sr1500.dts
new file mode 100644
index 000..3729ca0
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_sr1500.dts
@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) 2015 Stefan Roese 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include "socfpga_cyclone5.dtsi"
+
+/ {
+   model = "SoCFPGA Cyclone V SR1500";
+   compatible = "anonymous,socfpga-sr1500", "altr,socfpga-cyclone5", 
"altr,socfpga";
+
+   chosen {
+   bootargs = "console=ttyS0,115200";
+   };
+
+   aliases {
+   /*
+* This allows the ethaddr uboot environmnet variable
+* contents to be added to the gmac1 device tree blob.
+*/
+   ethernet0 = 
+   };
+
+   memory@0 {
+   name = "memory";
+   device_type = "memory";
+   reg = <0x0 0x4000>; /* 1GB */
+   };
+
+   soc {
+   u-boot,dm-pre-reloc;
+   };
+};
+
+ {
+   status = "okay";
+   phy-mode = "rgmii";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+   speed-mode = <0>;
+};
+
+ {
+   status = "okay";
+   speed-mode = <0>;
+};
+
+ {
+   status = "okay";
+   bus-width = <8>;
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+   u-boot,dm-pre-reloc;
+
+   flash0: n25q00@0 {
+   u-boot,dm-pre-reloc;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "n25q00", "spi-flash";
+   reg = <0>;  /* chip select */
+   spi-max-frequency = <5000>;
+   m25p,fast-read;
+   page-size = <256>;
+   block-size = <16>; /* 2^16, 64KB */
+   read-delay = <4>;  /* delay value in read data capture register 
*/
+   tshsl-ns = <50>;
+   tsd2d-ns = <50>;
+   tchsh-ns = <4>;
+   tslch-ns = <4>;
+   };
+};
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index