Add HPET driver as an alternative timer for x86 (default is TSC).
HPET counter has constant frequency and does not need calibration.
This change also makes TSC timer driver optional on x86.
New HPET driver can also be selected as the early timer on x86.
HPET can be selected as the tick timer in the Device Tree "chosen" node:
/include/ "hpet.dtsi"
...
chosen {
tick-timer = "/hpet";
};
Signed-off-by: Ivan Gorinov
---
arch/Kconfig | 2 +-
arch/x86/Kconfig | 21 ++
arch/x86/dts/hpet.dtsi | 7 ++
drivers/timer/Kconfig | 9 +++
drivers/timer/Makefile | 1 +
drivers/timer/hpet_timer.c | 181 +
drivers/timer/tsc_timer.c | 8 ++
7 files changed, 228 insertions(+), 1 deletion(-)
create mode 100644 arch/x86/dts/hpet.dtsi
create mode 100644 drivers/timer/hpet_timer.c
diff --git a/arch/Kconfig b/arch/Kconfig
index e599e7a..37dabae 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -104,7 +104,7 @@ config X86
select DM_PCI
select PCI
select TIMER
- select X86_TSC_TIMER
+ imply X86_TSC_TIMER
imply BLK
imply DM_ETH
imply DM_GPIO
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 5c23b2c..2fe5b6a 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -119,6 +119,27 @@ source "arch/x86/cpu/tangier/Kconfig"
# architecture-specific options below
+choice
+ prompt "Select which timer to use early on x86"
+ depends on X86
+ default X86_EARLY_TIMER_TSC
+
+config X86_EARLY_TIMER_TSC
+ bool "TSC"
+ depends on X86_TSC_TIMER
+ help
+ This selects x86 Time Stamp Counter (TSC) as the early timer.
+ See CONFIG_TIMER_EARLY for the early timer description.
+
+config X86_EARLY_TIMER_HPET
+ bool "HPET"
+ depends on HPET_TIMER
+ help
+ This selects High Precision Event Timers as the early timer.
+ Early HPET base address is specified by CONFIG_HPET_ADDRESS.
+
+endchoice
+
config AHCI
default y
diff --git a/arch/x86/dts/hpet.dtsi b/arch/x86/dts/hpet.dtsi
new file mode 100644
index 000..a74f739
--- /dev/null
+++ b/arch/x86/dts/hpet.dtsi
@@ -0,0 +1,7 @@
+/ {
+ hpet: hpet@fed0 {
+ compatible = "hpet-x86";
+ u-boot,dm-pre-reloc;
+ reg = <0xfed0 0x1000>;
+ };
+};
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 2c96896..26743b7 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -65,6 +65,15 @@ config X86_TSC_TIMER
help
Select this to enable Time-Stamp Counter (TSC) timer for x86.
+config HPET_TIMER
+ bool "High Precision Event Timers (HPET) support"
+ depends on TIMER
+ default y if X86
+ help
+ Select this to enable High Precision Event Timers (HPET) on x86.
+ HPET main counter increments at constant rate and does not need
+ calibration.
+
config OMAP_TIMER
bool "Omap timer support"
depends on TIMER
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index a6e7832..557fecc 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -8,6 +8,7 @@ obj-y += timer-uclass.o
obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o
obj-$(CONFIG_SANDBOX_TIMER)+= sandbox_timer.o
obj-$(CONFIG_X86_TSC_TIMER)+= tsc_timer.o
+obj-$(CONFIG_HPET_TIMER) += hpet_timer.o
obj-$(CONFIG_OMAP_TIMER) += omap-timer.o
obj-$(CONFIG_AST_TIMER)+= ast_timer.o
obj-$(CONFIG_STI_TIMER)+= sti-timer.o
diff --git a/drivers/timer/hpet_timer.c b/drivers/timer/hpet_timer.c
new file mode 100644
index 000..86b05fa
--- /dev/null
+++ b/drivers/timer/hpet_timer.c
@@ -0,0 +1,181 @@
+/*
+ * Copyright (c) 2017 Intel Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define HPET_PERIOD_REG 0x004
+#define HPET_CONFIG_REG 0x010
+#define HPET_MAIN_COUNT 0x0f0
+
+#define ENABLE_CNF 1
+
+#define HPET_MAX_PERIOD 1
+
+struct hpet_timer_priv {
+ void *regs;
+};
+
+/*
+ * Returns HPET clock frequency in HZ
+ * (rounding to the nearest integer),
+ * or 0 if HPET is not available.
+ */
+static inline u32 get_clock_frequency(void *regs)
+{
+ u64 d = 1000ull;
+ u32 period;
+
+ period = readl(regs + HPET_PERIOD_REG);
+ if (period == 0)
+ return 0;
+ if (period > HPET_MAX_PERIOD)
+ return 0;
+
+ d += period / 2;
+
+ return d / period;
+}
+
+/* Reset and start the main counter. */
+static void start_main_counter(void *regs)
+{
+ volatile u64 *main_counter = regs + HPET_MAIN_COUNT;
+ u32 config;
+
+ config = readl(regs + HPET_CONFIG_REG);
+ config &= ~ENABLE_CNF;
+ writel(config, regs + HPET_CONFIG_REG);
+ *main_counter = 0;
+ config
