Re: [U-Boot] [PATCH v4 1/4] mx6: ddr: Allow changing REFSEL and REFR fields
Hi Fabio, On 08/29/2016 04:37 PM, Fabio Estevam wrote: > From: Fabio Estevam> > Currently MX6 SPL DDR initialization hardcodes the REF_SEL and > REFR fields of the MDREF register as 1 and 7, respectively for > DDR3 and 0 and 3 for LPDDR2. > > Looking at the MDREF initialization done via DCD we see that > boards do need to initialize these fields differently: > > $ git grep 0x021b0020 board/ > board/bachmann/ot1200/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x5800 > board/ccv/xpress/imximage.cfg:DATA 4 0x021b0020 0x0800 /* MMDC0_MDREF */ > board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x7800 > board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x5800 > board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x5800 > board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x5800 > board/freescale/mx6qsabreauto/imximage.cfg:DATA 4 0x021b0020 0x5800 > board/freescale/mx6qsabreauto/mx6dl.cfg:DATA 4 0x021b0020 0x5800 > board/freescale/mx6qsabreauto/mx6qp.cfg:DATA 4 0x021b0020 0x5800 > board/freescale/mx6sabresd/mx6dlsabresd.cfg:DATA 4 0x021b0020 0x5800 > board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x5800 > board/freescale/mx6slevk/imximage.cfg:DATA 4 0x021b0020 0x1800 > board/freescale/mx6sxsabreauto/imximage.cfg:DATA 4 0x021b0020 0x0800 > board/freescale/mx6sxsabresd/imximage.cfg:DATA 4 0x021b0020 0x0800 > board/warp/imximage.cfg:DATA 4 0x021b0020 0x1800 > > So introduce a mechanism for users to be able to configure > REFSEL and REFR fields as needed. > > Keep all the mx6 SPL users in their current REF_SEL and REFR values, > so no functional changes for the existing users. > > Signed-off-by: Fabio Estevam > --- > Changes since v3: > - Fix the logic for setting refsel/refr registers (Eric) > > arch/arm/cpu/armv7/mx6/ddr.c | 6 ++ > arch/arm/include/asm/arch-mx6/mx6-ddr.h | 2 ++ > board/bachmann/ot1200/ot1200_spl.c| 2 ++ > board/barco/platinum/spl_picon.c | 2 ++ > board/barco/platinum/spl_titanium.c | 2 ++ > board/ccv/xpress/spl.c| 2 ++ > board/compulab/cm_fx6/spl.c | 4 > board/congatec/cgtqmx6eval/cgtqmx6eval.c | 2 ++ > board/el/el6x/el6x.c | 2 ++ > board/freescale/mx6sabresd/mx6sabresd.c | 2 ++ > board/freescale/mx6slevk/mx6slevk.c | 2 ++ > board/freescale/mx6sxsabresd/mx6sxsabresd.c | 2 ++ > board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 4 > board/gateworks/gw_ventana/gw_ventana_spl.c | 2 ++ > board/kosagi/novena/novena_spl.c | 2 ++ > board/phytec/pcm058/pcm058.c | 2 ++ > board/solidrun/mx6cuboxi/mx6cuboxi.c | 2 ++ > board/udoo/udoo_spl.c | 2 ++ > board/wandboard/spl.c | 6 ++ > 19 files changed, 46 insertions(+), 4 deletions(-) > > diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c > index f151eec..7beb7ea 100644 > --- a/arch/arm/cpu/armv7/mx6/ddr.c > +++ b/arch/arm/cpu/armv7/mx6/ddr.c > @@ -1166,8 +1166,7 @@ void mx6_lpddr2_cfg(const struct mx6_ddr_sysinfo > *sysinfo, > mmdc0->mpzqhwctrl = val; > > /* Step 12: Configure and activate periodic refresh */ > - mmdc0->mdref = (0 << 14) | /* REF_SEL: Periodic refresh cycle: 64kHz */ > -(3 << 11); /* REFR: Refresh Rate - 4 refreshes */ > + mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11); > > /* Step 13: Deassert config request - init complete */ > mmdc0->mdscr = 0x; > @@ -1472,8 +1471,7 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo, > MMDC1(mpzqhwctrl, val); > > /* Step 12: Configure and activate periodic refresh */ > - mmdc0->mdref = (1 << 14) | /* REF_SEL: Periodic refresh cycle: 32kHz */ > -(7 << 11); /* REFR: Refresh Rate - 8 refreshes */ > + mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11); > > /* Step 13: Deassert config request - init complete */ > mmdc0->mdscr = 0x; > diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h > b/arch/arm/include/asm/arch-mx6/mx6-ddr.h > index 12c30d2..9922409 100644 > --- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h > +++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h > @@ -408,6 +408,8 @@ struct mx6_ddr_sysinfo { > u8 sde_to_rst; /* Time from SDE enable until DDR reset# is high */ > u8 pd_fast_exit;/* enable precharge powerdown fast-exit */ > u8 ddr_type;/* DDR type: DDR3(0) or LPDDR2(1) */ > + u8 refsel; /* REF_SEL field of register MDREF */ > + u8 refr;/* REFR field of register MDREF */ > }; > > /* > diff --git a/board/bachmann/ot1200/ot1200_spl.c >
[U-Boot] [PATCH v4 1/4] mx6: ddr: Allow changing REFSEL and REFR fields
From: Fabio EstevamCurrently MX6 SPL DDR initialization hardcodes the REF_SEL and REFR fields of the MDREF register as 1 and 7, respectively for DDR3 and 0 and 3 for LPDDR2. Looking at the MDREF initialization done via DCD we see that boards do need to initialize these fields differently: $ git grep 0x021b0020 board/ board/bachmann/ot1200/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x5800 board/ccv/xpress/imximage.cfg:DATA 4 0x021b0020 0x0800 /* MMDC0_MDREF */ board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x7800 board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x5800 board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x5800 board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x5800 board/freescale/mx6qsabreauto/imximage.cfg:DATA 4 0x021b0020 0x5800 board/freescale/mx6qsabreauto/mx6dl.cfg:DATA 4 0x021b0020 0x5800 board/freescale/mx6qsabreauto/mx6qp.cfg:DATA 4 0x021b0020 0x5800 board/freescale/mx6sabresd/mx6dlsabresd.cfg:DATA 4 0x021b0020 0x5800 board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x5800 board/freescale/mx6slevk/imximage.cfg:DATA 4 0x021b0020 0x1800 board/freescale/mx6sxsabreauto/imximage.cfg:DATA 4 0x021b0020 0x0800 board/freescale/mx6sxsabresd/imximage.cfg:DATA 4 0x021b0020 0x0800 board/warp/imximage.cfg:DATA 4 0x021b0020 0x1800 So introduce a mechanism for users to be able to configure REFSEL and REFR fields as needed. Keep all the mx6 SPL users in their current REF_SEL and REFR values, so no functional changes for the existing users. Signed-off-by: Fabio Estevam --- Changes since v3: - Fix the logic for setting refsel/refr registers (Eric) arch/arm/cpu/armv7/mx6/ddr.c | 6 ++ arch/arm/include/asm/arch-mx6/mx6-ddr.h | 2 ++ board/bachmann/ot1200/ot1200_spl.c| 2 ++ board/barco/platinum/spl_picon.c | 2 ++ board/barco/platinum/spl_titanium.c | 2 ++ board/ccv/xpress/spl.c| 2 ++ board/compulab/cm_fx6/spl.c | 4 board/congatec/cgtqmx6eval/cgtqmx6eval.c | 2 ++ board/el/el6x/el6x.c | 2 ++ board/freescale/mx6sabresd/mx6sabresd.c | 2 ++ board/freescale/mx6slevk/mx6slevk.c | 2 ++ board/freescale/mx6sxsabresd/mx6sxsabresd.c | 2 ++ board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 4 board/gateworks/gw_ventana/gw_ventana_spl.c | 2 ++ board/kosagi/novena/novena_spl.c | 2 ++ board/phytec/pcm058/pcm058.c | 2 ++ board/solidrun/mx6cuboxi/mx6cuboxi.c | 2 ++ board/udoo/udoo_spl.c | 2 ++ board/wandboard/spl.c | 6 ++ 19 files changed, 46 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index f151eec..7beb7ea 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -1166,8 +1166,7 @@ void mx6_lpddr2_cfg(const struct mx6_ddr_sysinfo *sysinfo, mmdc0->mpzqhwctrl = val; /* Step 12: Configure and activate periodic refresh */ - mmdc0->mdref = (0 << 14) | /* REF_SEL: Periodic refresh cycle: 64kHz */ - (3 << 11); /* REFR: Refresh Rate - 4 refreshes */ + mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11); /* Step 13: Deassert config request - init complete */ mmdc0->mdscr = 0x; @@ -1472,8 +1471,7 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo, MMDC1(mpzqhwctrl, val); /* Step 12: Configure and activate periodic refresh */ - mmdc0->mdref = (1 << 14) | /* REF_SEL: Periodic refresh cycle: 32kHz */ - (7 << 11); /* REFR: Refresh Rate - 8 refreshes */ + mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11); /* Step 13: Deassert config request - init complete */ mmdc0->mdscr = 0x; diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h index 12c30d2..9922409 100644 --- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h +++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h @@ -408,6 +408,8 @@ struct mx6_ddr_sysinfo { u8 sde_to_rst; /* Time from SDE enable until DDR reset# is high */ u8 pd_fast_exit;/* enable precharge powerdown fast-exit */ u8 ddr_type;/* DDR type: DDR3(0) or LPDDR2(1) */ + u8 refsel; /* REF_SEL field of register MDREF */ + u8 refr;/* REFR field of register MDREF */ }; /* diff --git a/board/bachmann/ot1200/ot1200_spl.c b/board/bachmann/ot1200/ot1200_spl.c index f651a40..9d28da4 100644 --- a/board/bachmann/ot1200/ot1200_spl.c +++ b/board/bachmann/ot1200/ot1200_spl.c @@ -85,6 +85,8 @@ static struct mx6_ddr_sysinfo ot1200_ddr_sysinfo = { .bi_on = 1,