Re: [U-Boot] [PATCH v4 2/2] imx: Add PHYTEC phyBOARD-i.MX6UL-Segin

2019-01-18 Thread Martyn Welch 
Hi All,

Is there anything preventing this series being merged? I don't think
I've seen any further issues raised.

Sorry if it's already been merged somewhere and I've missed it...

Martyn

On Tue, 2018-12-11 at 11:34 +, Martyn Welch wrote:
> Port for the PHYTEC phyBOARD-i.MX6UL-Segin single board computer.
> Based on
> the PHYTEC phyCORE-i.MX6UL SOM (PCL063).
> 
> CPU:   Freescale i.MX6UL rev1.2 528 MHz (running at 396 MHz)
> CPU:   Industrial temperature grade (-40C to 105C) at 44C
> Reset cause: POR
> Board: PHYTEC phyCORE-i.MX6UL
> I2C:   ready
> DRAM:  256 MiB
> NAND:  512 MiB
> MMC:   FSL_SDHC: 0
> In:serial
> Out:   serial
> Err:   serial
> Net:   FEC0
> 
> Working:
>  - Eth0
>  - i2C
>  - MMC/SD
>  - NAND
>  - UART (1 & 5)
>  - USB (host & otg)
> 
> Signed-off-by: Martyn Welch 
> 
> ---
> 
> Changes in v4:
> - Added PXE boot option
> - Switched i2c to DM support
> 
> Changes in v3:
> - Correct spelling of Phytec
> - Remove unneeded license information
> - Correct image name in documentation
> - Correct whitespacing
> - Enable SPL to boot from MMC
> - Simplify defconfig, remove non-SPL build
> 
> Changes in v2:
> - Switch to driver model
> 
>  arch/arm/dts/Makefile |   3 +-
>  arch/arm/dts/imx6ul-pcl063.dtsi   | 173 +
>  arch/arm/dts/imx6ul-phycore-segin.dts |  76 ++
>  arch/arm/mach-imx/mx6/Kconfig |  13 ++
>  board/phytec/pcl063/Kconfig   |  12 ++
>  board/phytec/pcl063/MAINTAINERS   |   8 +
>  board/phytec/pcl063/Makefile  |   7 +
>  board/phytec/pcl063/README|  26 
>  board/phytec/pcl063/pcl063.c  | 206
> ++
>  board/phytec/pcl063/spl.c | 160 
>  configs/phycore_pcl063_defconfig  |  62 
>  include/configs/pcl063.h  |  94 
>  12 files changed, 839 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/dts/imx6ul-pcl063.dtsi
>  create mode 100644 arch/arm/dts/imx6ul-phycore-segin.dts
>  create mode 100644 board/phytec/pcl063/Kconfig
>  create mode 100644 board/phytec/pcl063/MAINTAINERS
>  create mode 100644 board/phytec/pcl063/Makefile
>  create mode 100644 board/phytec/pcl063/README
>  create mode 100644 board/phytec/pcl063/pcl063.c
>  create mode 100644 board/phytec/pcl063/spl.c
>  create mode 100644 configs/phycore_pcl063_defconfig
>  create mode 100644 include/configs/pcl063.h
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 949ee472fc..68411623e5 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -453,7 +453,8 @@ dtb-$(CONFIG_MX6UL) += \
>   imx6ul-isiot-nand.dtb \
>   imx6ul-opos6uldev.dtb \
>   imx6ul-14x14-evk.dtb \
> - imx6ul-9x9-evk.dtb
> + imx6ul-9x9-evk.dtb \
> + imx6ul-phycore-segin.dtb
>  
>  dtb-$(CONFIG_MX6ULL) += imx6ull-14x14-evk.dtb
>  
> diff --git a/arch/arm/dts/imx6ul-pcl063.dtsi b/arch/arm/dts/imx6ul-
> pcl063.dtsi
> new file mode 100644
> index 00..24a6a47983
> --- /dev/null
> +++ b/arch/arm/dts/imx6ul-pcl063.dtsi
> @@ -0,0 +1,173 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2018 Collabora Ltd.
> + *
> + * Based on dts[i] from Phytec barebox port:
> + * Copyright (C) 2016 PHYTEC Messtechnik GmbH
> + * Author: Christian Hemp 
> + */
> +
> +/dts-v1/;
> +
> +#include "imx6ul.dtsi"
> +
> +/ {
> + model = "Phytec phyCORE-i.MX6 Ultra Lite SOM";
> + compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul";
> +
> + memory {
> + reg = <0x8000 0x2000>;
> + };
> +
> + chosen {
> + stdout-path = 
> + };
> +};
> +
> + {
> + pinctrl-names = "default";
> + pinctrl-0 = <_enet1>;
> + phy-mode = "rmii";
> + phy-handle = <>;
> + status = "okay";
> +
> + mdio: mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethphy0: ethernet-phy@1 {
> + reg = <1>;
> + micrel,led-mode = <1>;
> + };
> + };
> +};
> +
> + {
> + pinctrl-names = "default";
> + pinctrl-0 = <_gpmi_nand>;
> + nand-on-flash-bbt;
> + fsl,no-blockmark-swap;
> + status = "okay";
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + partition@0 {
> + label = "uboot";
> + reg = <0x0 0x40>;
> + };
> +
> + partition@40 {
> + label = "uboot-env";
> + reg = <0x40 0x10>;
> + };
> +
> + partition@50 {
> + label = "root";
> + reg = <0x50 0x0>;
> + };
> +};
> +
> + {
> + clock-frequency = <10>;
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <_i2c1>;
> + pinctrl-1 = <_i2c1_gpio>;
> + scl-gpios = < 28 GPIO_ACTIVE_HIGH>;
> + sda-gpios = < 29 GPIO_ACTIVE_HIGH>;
> + status = "okay";
> +
> + eeprom@52 {
> + compatible = "cat,24c32";
> + reg = <0x52>;
> +

[U-Boot] [PATCH v4 2/2] imx: Add PHYTEC phyBOARD-i.MX6UL-Segin

2018-12-11 Thread Martyn Welch 
Port for the PHYTEC phyBOARD-i.MX6UL-Segin single board computer. Based on
the PHYTEC phyCORE-i.MX6UL SOM (PCL063).

CPU:   Freescale i.MX6UL rev1.2 528 MHz (running at 396 MHz)
CPU:   Industrial temperature grade (-40C to 105C) at 44C
Reset cause: POR
Board: PHYTEC phyCORE-i.MX6UL
I2C:   ready
DRAM:  256 MiB
NAND:  512 MiB
MMC:   FSL_SDHC: 0
In:serial
Out:   serial
Err:   serial
Net:   FEC0

Working:
 - Eth0
 - i2C
 - MMC/SD
 - NAND
 - UART (1 & 5)
 - USB (host & otg)

Signed-off-by: Martyn Welch 

---

Changes in v4:
- Added PXE boot option
- Switched i2c to DM support

Changes in v3:
- Correct spelling of Phytec
- Remove unneeded license information
- Correct image name in documentation
- Correct whitespacing
- Enable SPL to boot from MMC
- Simplify defconfig, remove non-SPL build

Changes in v2:
- Switch to driver model

 arch/arm/dts/Makefile |   3 +-
 arch/arm/dts/imx6ul-pcl063.dtsi   | 173 +
 arch/arm/dts/imx6ul-phycore-segin.dts |  76 ++
 arch/arm/mach-imx/mx6/Kconfig |  13 ++
 board/phytec/pcl063/Kconfig   |  12 ++
 board/phytec/pcl063/MAINTAINERS   |   8 +
 board/phytec/pcl063/Makefile  |   7 +
 board/phytec/pcl063/README|  26 
 board/phytec/pcl063/pcl063.c  | 206 ++
 board/phytec/pcl063/spl.c | 160 
 configs/phycore_pcl063_defconfig  |  62 
 include/configs/pcl063.h  |  94 
 12 files changed, 839 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/imx6ul-pcl063.dtsi
 create mode 100644 arch/arm/dts/imx6ul-phycore-segin.dts
 create mode 100644 board/phytec/pcl063/Kconfig
 create mode 100644 board/phytec/pcl063/MAINTAINERS
 create mode 100644 board/phytec/pcl063/Makefile
 create mode 100644 board/phytec/pcl063/README
 create mode 100644 board/phytec/pcl063/pcl063.c
 create mode 100644 board/phytec/pcl063/spl.c
 create mode 100644 configs/phycore_pcl063_defconfig
 create mode 100644 include/configs/pcl063.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 949ee472fc..68411623e5 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -453,7 +453,8 @@ dtb-$(CONFIG_MX6UL) += \
imx6ul-isiot-nand.dtb \
imx6ul-opos6uldev.dtb \
imx6ul-14x14-evk.dtb \
-   imx6ul-9x9-evk.dtb
+   imx6ul-9x9-evk.dtb \
+   imx6ul-phycore-segin.dtb
 
 dtb-$(CONFIG_MX6ULL) += imx6ull-14x14-evk.dtb
 
diff --git a/arch/arm/dts/imx6ul-pcl063.dtsi b/arch/arm/dts/imx6ul-pcl063.dtsi
new file mode 100644
index 00..24a6a47983
--- /dev/null
+++ b/arch/arm/dts/imx6ul-pcl063.dtsi
@@ -0,0 +1,173 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Collabora Ltd.
+ *
+ * Based on dts[i] from Phytec barebox port:
+ * Copyright (C) 2016 PHYTEC Messtechnik GmbH
+ * Author: Christian Hemp 
+ */
+
+/dts-v1/;
+
+#include "imx6ul.dtsi"
+
+/ {
+   model = "Phytec phyCORE-i.MX6 Ultra Lite SOM";
+   compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul";
+
+   memory {
+   reg = <0x8000 0x2000>;
+   };
+
+   chosen {
+   stdout-path = 
+   };
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_enet1>;
+   phy-mode = "rmii";
+   phy-handle = <>;
+   status = "okay";
+
+   mdio: mdio {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   ethphy0: ethernet-phy@1 {
+   reg = <1>;
+   micrel,led-mode = <1>;
+   };
+   };
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_gpmi_nand>;
+   nand-on-flash-bbt;
+   fsl,no-blockmark-swap;
+   status = "okay";
+
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   partition@0 {
+   label = "uboot";
+   reg = <0x0 0x40>;
+   };
+
+   partition@40 {
+   label = "uboot-env";
+   reg = <0x40 0x10>;
+   };
+
+   partition@50 {
+   label = "root";
+   reg = <0x50 0x0>;
+   };
+};
+
+ {
+   clock-frequency = <10>;
+   pinctrl-names = "default", "gpio";
+   pinctrl-0 = <_i2c1>;
+   pinctrl-1 = <_i2c1_gpio>;
+   scl-gpios = < 28 GPIO_ACTIVE_HIGH>;
+   sda-gpios = < 29 GPIO_ACTIVE_HIGH>;
+   status = "okay";
+
+   eeprom@52 {
+   compatible = "cat,24c32";
+   reg = <0x52>;
+   };
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_uart1>;
+   status = "okay";
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_usdhc1>;
+   cd-gpios = < 19 GPIO_ACTIVE_LOW>;
+   bus-width = <0x4>;
+   pinctrl-0 = <_usdhc1>;
+   no-1-8-v;
+   status = "okay";
+};
+
+ {
+   pinctrl-names = "default";
+
+   pinctrl_enet1: enet1grp {
+   fsl,pins = <
+