Re: [U-Boot] [PATCH v4 2/4] mx6ul_14x14_evk: Pass refsel and refr fields to avoid hang

[Stefano Babic]

On 30/08/2016 01:37, Fabio Estevam wrote:
> From: Fabio Estevam 
> 
> When running a NXP 4.1 kernel with U-Boot mainline on a mx6ul-evk,
> we observe a hang when going into the lowest operational point of cpufreq.
> 
> This hang issue does not happen on the NXP U-Boot version.
> 
> After comparing the SPL DDR initialization against the DCD table
> from NXP U-Boot, the key difference that causes the hang is the
> MDREF register setting:
> 
> DATA 4 0x021B0020 0x0800
> 
> ,which means:
> 
> REF_SEL = 0 --> Periodic refresh cycle: 64kHz
> REFR = 1 ---> Refresh Rate - 2 refreshes
> 
> So adjust the MDREF initialization for mx6ul_evk accordingly
> to fix the kernel hang issue at low bus frequency.
> 
> Reported-by: Eric Nelson 
> Signed-off-by: Fabio Estevam 
> ---

Applied (all series as fix !) to u-boot-imx, thanks !

Best regards,
Stefano Babic



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Re: [U-Boot] [PATCH v4 2/4] mx6ul_14x14_evk: Pass refsel and refr fields to avoid hang

[Eric Nelson]

Hi Fabio,

On 08/29/2016 04:37 PM, Fabio Estevam wrote:
> From: Fabio Estevam 
> 
> When running a NXP 4.1 kernel with U-Boot mainline on a mx6ul-evk,
> we observe a hang when going into the lowest operational point of cpufreq.
> 
> This hang issue does not happen on the NXP U-Boot version.
> 
> After comparing the SPL DDR initialization against the DCD table
> from NXP U-Boot, the key difference that causes the hang is the
> MDREF register setting:
> 
> DATA 4 0x021B0020 0x0800
> 
> ,which means:
> 
> REF_SEL = 0 --> Periodic refresh cycle: 64kHz
> REFR = 1 ---> Refresh Rate - 2 refreshes
> 
> So adjust the MDREF initialization for mx6ul_evk accordingly
> to fix the kernel hang issue at low bus frequency.
> 
> Reported-by: Eric Nelson 
> Signed-off-by: Fabio Estevam 
> ---
> Changes since v3:
> - Just adapt due to previous patch
> 
>  board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c 
> b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
> index 5e39108..2ca0921 100644
> --- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
> +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
> @@ -806,8 +806,8 @@ struct mx6_ddr_sysinfo ddr_sysinfo = {
>   .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
>   .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
>   .ddr_type = DDR_TYPE_DDR3,
> - .refsel = 1,/* Refresh cycles at 32KHz */
> - .refr = 7,  /* 8 refresh commands per refresh cycle */
> + .refsel = 0,/* Refresh cycles at 64KHz */
> + .refr = 1,  /* 2 refresh commands per refresh cycle */
>  };
>  
>  static struct mx6_ddr3_cfg mem_ddr = {
> 

Reviewed-by: Eric Nelson 

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[U-Boot] [PATCH v4 2/4] mx6ul_14x14_evk: Pass refsel and refr fields to avoid hang

[Fabio Estevam]

From: Fabio Estevam 

When running a NXP 4.1 kernel with U-Boot mainline on a mx6ul-evk,
we observe a hang when going into the lowest operational point of cpufreq.

This hang issue does not happen on the NXP U-Boot version.

After comparing the SPL DDR initialization against the DCD table
from NXP U-Boot, the key difference that causes the hang is the
MDREF register setting:

DATA 4 0x021B0020 0x0800

,which means:

REF_SEL = 0 --> Periodic refresh cycle: 64kHz
REFR = 1 ---> Refresh Rate - 2 refreshes

So adjust the MDREF initialization for mx6ul_evk accordingly
to fix the kernel hang issue at low bus frequency.

Reported-by: Eric Nelson 
Signed-off-by: Fabio Estevam 
---
Changes since v3:
- Just adapt due to previous patch

 board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c 
b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
index 5e39108..2ca0921 100644
--- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
+++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
@@ -806,8 +806,8 @@ struct mx6_ddr_sysinfo ddr_sysinfo = {
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
.ddr_type = DDR_TYPE_DDR3,
-   .refsel = 1,/* Refresh cycles at 32KHz */
-   .refr = 7,  /* 8 refresh commands per refresh cycle */
+   .refsel = 0,/* Refresh cycles at 64KHz */
+   .refr = 1,  /* 2 refresh commands per refresh cycle */
 };
 
 static struct mx6_ddr3_cfg mem_ddr = {
-- 
1.9.1

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