Re: [U-Boot] [PATCH v4 4/5] net: mvpp2: use new MVMDIO driver
On Thu, Aug 15, 2019 at 5:09 PM wrote: > > From: Nevo Hed > > This commit ports mvpp2 to use the recently introduced Marvell MDIO > (MVMDIO) driver. It removes direct interaction with the SMI & XSMI > busses. This commit is based in part on earlier work by > Ken Ma in Marvell's own downstream repo: > https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c81dc39. > > The above refrenced work was based on an MVMDIO implementation that > never made it into U-Boot. With this patch the mvpp2 driver switches > to use the new MVMDIO driver that is based on a more universal > mdio-uclass implementation. > > Signed-off-by: Nevo Hed Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 4/5] net: mvpp2: use new MVMDIO driver
On Fri, Aug 16, 2019 at 1:09 AM wrote:
>
> From: Nevo Hed
>
> This commit ports mvpp2 to use the recently introduced Marvell MDIO
> (MVMDIO) driver. It removes direct interaction with the SMI & XSMI
> busses. This commit is based in part on earlier work by
> Ken Ma in Marvell's own downstream repo:
> https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c81dc39.
>
> The above refrenced work was based on an MVMDIO implementation that
> never made it into U-Boot. With this patch the mvpp2 driver switches
> to use the new MVMDIO driver that is based on a more universal
> mdio-uclass implementation.
>
> Signed-off-by: Nevo Hed
> ---
> drivers/net/mvpp2.c | 195
> 1 file changed, 18 insertions(+), 177 deletions(-)
>
> diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
> index 4ba6f9be3e..cfd119da37 100644
> --- a/drivers/net/mvpp2.c
> +++ b/drivers/net/mvpp2.c
> @@ -32,6 +32,7 @@
> #include
> #include
> #include
> +#include
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -62,8 +63,6 @@ do {
> \
> #define MTU1500
> #define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
>
> -#define MVPP2_SMI_TIMEOUT 1
> -
> /* RX Fifo Registers */
> #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
> #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
> @@ -490,23 +489,8 @@ do {
> \
> #define MVPP2_QUEUE_NEXT_DESC(q, index) \
> (((index) < (q)->last_desc) ? ((index) + 1) : 0)
>
> -/* SMI: 0xc0054 -> offset 0x54 to lms_base */
> -#define MVPP21_SMI 0x0054
> /* PP2.2: SMI: 0x12a200 -> offset 0x1200 to iface_base */
> #define MVPP22_SMI 0x1200
> -#define MVPP2_PHY_REG_MASK 0x1f
> -/* SMI register fields */
> -#define MVPP2_SMI_DATA_OFFS0 /* Data */
> -#define MVPP2_SMI_DATA_MASK(0x <<
> MVPP2_SMI_DATA_OFFS)
> -#define MVPP2_SMI_DEV_ADDR_OFFS16 /* PHY device address
> */
> -#define MVPP2_SMI_REG_ADDR_OFFS21 /* PHY device reg
> addr*/
> -#define MVPP2_SMI_OPCODE_OFFS 26 /* Write/Read opcode
> */
> -#define MVPP2_SMI_OPCODE_READ (1 << MVPP2_SMI_OPCODE_OFFS)
> -#define MVPP2_SMI_READ_VALID (1 << 27) /* Read Valid
> */
> -#define MVPP2_SMI_BUSY (1 << 28) /* Busy */
> -
> -#define MVPP2_PHY_ADDR_MASK0x1f
> -#define MVPP2_PHY_REG_MASK 0x1f
>
> /* Additional PPv2.2 offsets */
> #define MVPP22_MPCS0x007000
> @@ -952,7 +936,6 @@ struct mvpp2_port {
>
> /* Per-port registers' base address */
> void __iomem *base;
> - void __iomem *mdio_base;
>
> struct mvpp2_rx_queue **rxqs;
> struct mvpp2_tx_queue **txqs;
> @@ -973,9 +956,8 @@ struct mvpp2_port {
>
> struct phy_device *phy_dev;
> phy_interface_t phy_interface;
> - int phy_node;
> int phyaddr;
> - struct mii_dev *bus;
> + struct udevice *mdio_dev;
> #ifdef CONFIG_DM_GPIO
> struct gpio_desc phy_reset_gpio;
> struct gpio_desc phy_tx_disable_gpio;
> @@ -4499,8 +4481,8 @@ static void mvpp2_phy_connect(struct udevice *dev,
> struct mvpp2_port *port)
> struct phy_device *phy_dev;
>
> if (!port->init || port->link == 0) {
> - phy_dev = phy_connect(port->bus, port->phyaddr, dev,
> - port->phy_interface);
> + phy_dev = dm_mdio_phy_connect(port->mdio_dev, port->phyaddr,
> + dev, port->phy_interface);
>
> /*
> * If the phy doesn't match with any existing u-boot drivers
> the
> @@ -4585,7 +4567,7 @@ static int mvpp2_open(struct udevice *dev, struct
> mvpp2_port *port)
> return err;
> }
>
> - if (port->phy_node) {
> + if (port->phyaddr < PHY_MAX_ADDR) {
> mvpp2_phy_connect(dev, port);
> mvpp2_link_event(port);
> } else {
> @@ -4724,35 +4706,25 @@ static int phy_info_parse(struct udevice *dev, struct
> mvpp2_port *port)
> u32 id;
> u32 phyaddr = 0;
> int phy_mode = -1;
> -
> - /* Default mdio_base from the same eth base */
> - if (port->priv->hw_version == MVPP21)
> - port->mdio_base = port->priv->lms_base + MVPP21_SMI;
> - else
> - port->mdio_base = port->priv->iface_base + MVPP22_SMI;
> + int ret;
>
> phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
>
> if (phy_node > 0) {
> - ofnode phy_ofnode;
[U-Boot] [PATCH v4 4/5] net: mvpp2: use new MVMDIO driver
From: Nevo Hed
This commit ports mvpp2 to use the recently introduced Marvell MDIO
(MVMDIO) driver. It removes direct interaction with the SMI & XSMI
busses. This commit is based in part on earlier work by
Ken Ma in Marvell's own downstream repo:
https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c81dc39.
The above refrenced work was based on an MVMDIO implementation that
never made it into U-Boot. With this patch the mvpp2 driver switches
to use the new MVMDIO driver that is based on a more universal
mdio-uclass implementation.
Signed-off-by: Nevo Hed
---
drivers/net/mvpp2.c | 195
1 file changed, 18 insertions(+), 177 deletions(-)
diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 4ba6f9be3e..cfd119da37 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -32,6 +32,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -62,8 +63,6 @@ do {
\
#define MTU1500
#define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
-#define MVPP2_SMI_TIMEOUT 1
-
/* RX Fifo Registers */
#define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
#define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
@@ -490,23 +489,8 @@ do {
\
#define MVPP2_QUEUE_NEXT_DESC(q, index) \
(((index) < (q)->last_desc) ? ((index) + 1) : 0)
-/* SMI: 0xc0054 -> offset 0x54 to lms_base */
-#define MVPP21_SMI 0x0054
/* PP2.2: SMI: 0x12a200 -> offset 0x1200 to iface_base */
#define MVPP22_SMI 0x1200
-#define MVPP2_PHY_REG_MASK 0x1f
-/* SMI register fields */
-#define MVPP2_SMI_DATA_OFFS0 /* Data */
-#define MVPP2_SMI_DATA_MASK(0x <<
MVPP2_SMI_DATA_OFFS)
-#define MVPP2_SMI_DEV_ADDR_OFFS16 /* PHY device address */
-#define MVPP2_SMI_REG_ADDR_OFFS21 /* PHY device reg addr*/
-#define MVPP2_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
-#define MVPP2_SMI_OPCODE_READ (1 << MVPP2_SMI_OPCODE_OFFS)
-#define MVPP2_SMI_READ_VALID (1 << 27) /* Read Valid */
-#define MVPP2_SMI_BUSY (1 << 28) /* Busy */
-
-#define MVPP2_PHY_ADDR_MASK0x1f
-#define MVPP2_PHY_REG_MASK 0x1f
/* Additional PPv2.2 offsets */
#define MVPP22_MPCS0x007000
@@ -952,7 +936,6 @@ struct mvpp2_port {
/* Per-port registers' base address */
void __iomem *base;
- void __iomem *mdio_base;
struct mvpp2_rx_queue **rxqs;
struct mvpp2_tx_queue **txqs;
@@ -973,9 +956,8 @@ struct mvpp2_port {
struct phy_device *phy_dev;
phy_interface_t phy_interface;
- int phy_node;
int phyaddr;
- struct mii_dev *bus;
+ struct udevice *mdio_dev;
#ifdef CONFIG_DM_GPIO
struct gpio_desc phy_reset_gpio;
struct gpio_desc phy_tx_disable_gpio;
@@ -4499,8 +4481,8 @@ static void mvpp2_phy_connect(struct udevice *dev, struct
mvpp2_port *port)
struct phy_device *phy_dev;
if (!port->init || port->link == 0) {
- phy_dev = phy_connect(port->bus, port->phyaddr, dev,
- port->phy_interface);
+ phy_dev = dm_mdio_phy_connect(port->mdio_dev, port->phyaddr,
+ dev, port->phy_interface);
/*
* If the phy doesn't match with any existing u-boot drivers the
@@ -4585,7 +4567,7 @@ static int mvpp2_open(struct udevice *dev, struct
mvpp2_port *port)
return err;
}
- if (port->phy_node) {
+ if (port->phyaddr < PHY_MAX_ADDR) {
mvpp2_phy_connect(dev, port);
mvpp2_link_event(port);
} else {
@@ -4724,35 +4706,25 @@ static int phy_info_parse(struct udevice *dev, struct
mvpp2_port *port)
u32 id;
u32 phyaddr = 0;
int phy_mode = -1;
-
- /* Default mdio_base from the same eth base */
- if (port->priv->hw_version == MVPP21)
- port->mdio_base = port->priv->lms_base + MVPP21_SMI;
- else
- port->mdio_base = port->priv->iface_base + MVPP22_SMI;
+ int ret;
phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
if (phy_node > 0) {
- ofnode phy_ofnode;
- fdt_addr_t phy_base;
-
+ int parent;
phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0);
if (phyaddr < 0) {
dev_err(&pdev->dev, "could not find phy address\n");
