Re: [U-Boot] [PATCH v5 05/33] ARM: i.MX6Q: sabresd: Add initial devicetree support

[Fabio Estevam]

On Thu, May 4, 2017 at 12:11 PM, Jagan Teki  wrote:
> From: Jagan Teki 
>
> Add initial devicetree support for i.MX6 Quad Sabresd board.
>
> The configs item are copied from configs/mx6sabresd_spl_defconfig
> and added
> - CONFIG_OF_CONTROL=y
> - CONFIG_DM_GPIO=y
> - CONFIG_DM_MMC=y
> - CONFIG_BLK is not set
> - CONFIG_DM_MMC_OPS is not set
> - CONFIG_PINCTRL=y
> - CONFIG_PINCTRL_IMX6=y
>
> Cc: Stefano Babic 
> Cc: Fabio Estevam 
> Cc: Michael Trimarchi 
> Signed-off-by: Jagan Teki 
> ---
>  board/freescale/mx6sabresd/MAINTAINERS  |   1 +
>  board/freescale/mx6sabresd/mx6sabresd.c | 132 
> ++--
>  configs/imx6qdl_sabresd_spl_defconfig   |  62 +++
>  include/configs/mx6sabresd.h|   4 +
>  4 files changed, 159 insertions(+), 40 deletions(-)
>  create mode 100644 configs/imx6qdl_sabresd_spl_defconfig
>
> diff --git a/board/freescale/mx6sabresd/MAINTAINERS 
> b/board/freescale/mx6sabresd/MAINTAINERS
> index add2314..ccb939d 100644
> --- a/board/freescale/mx6sabresd/MAINTAINERS
> +++ b/board/freescale/mx6sabresd/MAINTAINERS
> @@ -6,3 +6,4 @@ F:  include/configs/mx6sabresd.h
>  F: configs/mx6dlsabresd_defconfig
>  F: configs/mx6qsabresd_defconfig
>  F: configs/mx6sabresd_spl_defconfig
> +F: configs/imx6qdl_sabresd_spl_defconfig

mx6qdl_sabresd_spl_defconfig is not a good name:

- We do not support mx6dl currently
- We support mx6qp

Just use the existing mx6sabresd_spl_defconfig.
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[U-Boot] [PATCH v5 05/33] ARM: i.MX6Q: sabresd: Add initial devicetree support

[Jagan Teki]

From: Jagan Teki 

Add initial devicetree support for i.MX6 Quad Sabresd board.

The configs item are copied from configs/mx6sabresd_spl_defconfig
and added
- CONFIG_OF_CONTROL=y
- CONFIG_DM_GPIO=y
- CONFIG_DM_MMC=y
- CONFIG_BLK is not set
- CONFIG_DM_MMC_OPS is not set
- CONFIG_PINCTRL=y
- CONFIG_PINCTRL_IMX6=y

Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
 board/freescale/mx6sabresd/MAINTAINERS  |   1 +
 board/freescale/mx6sabresd/mx6sabresd.c | 132 ++--
 configs/imx6qdl_sabresd_spl_defconfig   |  62 +++
 include/configs/mx6sabresd.h|   4 +
 4 files changed, 159 insertions(+), 40 deletions(-)
 create mode 100644 configs/imx6qdl_sabresd_spl_defconfig

diff --git a/board/freescale/mx6sabresd/MAINTAINERS 
b/board/freescale/mx6sabresd/MAINTAINERS
index add2314..ccb939d 100644
--- a/board/freescale/mx6sabresd/MAINTAINERS
+++ b/board/freescale/mx6sabresd/MAINTAINERS
@@ -6,3 +6,4 @@ F:  include/configs/mx6sabresd.h
 F: configs/mx6dlsabresd_defconfig
 F: configs/mx6qsabresd_defconfig
 F: configs/mx6sabresd_spl_defconfig
+F: configs/imx6qdl_sabresd_spl_defconfig
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c 
b/board/freescale/mx6sabresd/mx6sabresd.c
index 80a7789..93d0dc4 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -241,7 +241,7 @@ static void setup_iomux_uart(void)
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 }
 
-#ifdef CONFIG_FSL_ESDHC
+#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_OF_CONTROL)
 struct fsl_esdhc_cfg usdhc_cfg[3] = {
{USDHC2_BASE_ADDR},
{USDHC3_BASE_ADDR},
@@ -276,9 +276,9 @@ int board_mmc_getcd(struct mmc *mmc)
return ret;
 }
 
+#ifndef CONFIG_FSL_ESDHC
 int board_mmc_init(bd_t *bis)
 {
-#ifndef CONFIG_SPL_BUILD
int ret;
int i;
 
@@ -321,46 +321,9 @@ int board_mmc_init(bd_t *bis)
}
 
return 0;
-#else
-   struct src *psrc = (struct src *)SRC_BASE_ADDR;
-   unsigned reg = readl(>sbmr1) >> 11;
-   /*
-* Upon reading BOOT_CFG register the following map is done:
-* Bit 11 and 12 of BOOT_CFG register can determine the current
-* mmc port
-* 0x1  SD1
-* 0x2  SD2
-* 0x3  SD4
-*/
-
-   switch (reg & 0x3) {
-   case 0x1:
-   imx_iomux_v3_setup_multiple_pads(
-   usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
-   usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
-   usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-   gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
-   break;
-   case 0x2:
-   imx_iomux_v3_setup_multiple_pads(
-   usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
-   usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
-   usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-   gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
-   break;
-   case 0x3:
-   imx_iomux_v3_setup_multiple_pads(
-   usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
-   usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
-   usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
-   gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
-   break;
-   }
-
-   return fsl_esdhc_initialize(bis, _cfg[0]);
-#endif
 }
 #endif
+#endif
 
 static int ar8031_phy_fixup(struct phy_device *phydev)
 {
@@ -717,6 +680,85 @@ int checkboard(void)
 #include 
 #include 
 
+#ifdef CONFIG_FSL_ESDHC
+
+#if defined(CONFIG_OF_CONTROL) && !defined(CONFIG_DM_MMC)
+struct fsl_esdhc_cfg usdhc_cfg[3] = {
+   {USDHC2_BASE_ADDR},
+   {USDHC3_BASE_ADDR},
+   {USDHC4_BASE_ADDR},
+};
+
+#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
+#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
+
+int board_mmc_get_env_dev(int devno)
+{
+   return devno - 1;
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+   struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+   int ret = 0;
+
+   switch (cfg->esdhc_base) {
+   case USDHC2_BASE_ADDR:
+   ret = !gpio_get_value(USDHC2_CD_GPIO);
+   break;
+   case USDHC3_BASE_ADDR:
+   ret = !gpio_get_value(USDHC3_CD_GPIO);
+   break;
+   case USDHC4_BASE_ADDR:
+   ret = 1; /* eMMC/uSDHC4 is always present */
+   break;
+   }
+
+   return ret;
+}
+#endif
+
+int board_mmc_init(bd_t *bis)
+{
+   struct src *psrc = (struct src *)SRC_BASE_ADDR;
+   unsigned reg = readl(>sbmr1) >> 11;
+   /*
+* Upon reading BOOT_CFG register the following map is done:
+* Bit 11 and 12 of BOOT_CFG register