The QorIQ LS1088A processor is built on the Layerscape
architecture combining eight ARM A53 processor cores
with advanced, high-performance datapath acceleration
and networks, peripheral interfaces required for
networking, wireless infrastructure, and general-purpose
embedded applications.
LS1088A is compliant with the Layerscape Chassis Generation 3.
Features summary:
- Eight 32-bit / 64-bit ARM v8 Cortex-A53 CPUs
- Cores are in 2 cluster of 4-cores each
- Cache coherent interconnect (CCI-400)
- One 64-bit DDR4 SDRAM memory controller with ECC
- Data path acceleration architecture 2.0 (DPAA2)
- Ethernet interfaces: SGMIIs, RGMIIs, QSGMIIs, XFIs
- QSPI, IFC, 3 PCIe, 1 SATA, 2 USB, 1 SDXC, 2 DUARTs etc
Signed-off-by: Alison Wang
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Ashish Kumar
Signed-off-by: Raghav Dogra
Signed-off-by: Shaohui Xie
---
v5:
No change
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 35 +-
arch/arm/cpu/armv8/fsl-layerscape/Makefile | 4 +
arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 43 ++-
.../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c| 19
arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c | 126 +
arch/arm/cpu/armv8/fsl-layerscape/soc.c| 1 +
arch/arm/dts/fsl-ls1088a.dtsi | 78 +
arch/arm/include/asm/arch-fsl-layerscape/config.h | 62 +-
arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 4 +
.../include/asm/arch-fsl-layerscape/fsl_serdes.h | 3 +-
.../include/asm/arch-fsl-layerscape/immap_lsch3.h | 11 ++
arch/arm/include/asm/arch-fsl-layerscape/soc.h | 4 +
.../asm/arch-fsl-layerscape/stream_id_lsch3.h | 14 +++
drivers/ddr/fsl/util.c | 2 +-
drivers/net/ldpaa_eth/Makefile | 1 +
drivers/net/ldpaa_eth/ls1088a.c| 87 ++
16 files changed, 482 insertions(+), 12 deletions(-)
create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
create mode 100644 arch/arm/dts/fsl-ls1088a.dtsi
create mode 100644 drivers/net/ldpaa_eth/ls1088a.c
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index eb8ccd1..aa2d0d1 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -50,6 +50,29 @@ config ARCH_LS1046A
select BOARD_EARLY_INIT_F
imply SCSI
+config ARCH_LS1088A
+ bool
+ select ARMV8_SET_SMPEN
+ select FSL_LSCH3
+ select SYS_FSL_DDR
+ select SYS_FSL_DDR_LE
+ select SYS_FSL_DDR_VER_50
+ select SYS_FSL_ERRATUM_A009803
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_ERRATUM_A010165
+ select SYS_FSL_ERRATUM_A008511
+ select SYS_FSL_ERRATUM_A008850
+ select SYS_FSL_HAS_CCI400
+ select SYS_FSL_HAS_DDR4
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_5
+ select SYS_FSL_SEC_LE
+ select SYS_FSL_SRDS_1
+ select SYS_FSL_SRDS_2
+ select FSL_TZASC_1
+ select ARCH_EARLY_INIT_R
+ select BOARD_EARLY_INIT_F
+
config ARCH_LS2080A
bool
select ARMV8_SET_SMPEN
@@ -100,7 +123,7 @@ config FSL_LSCH3
config FSL_MC_ENET
bool "Management Complex network"
- depends on ARCH_LS2080A
+ depends on ARCH_LS2080A || ARCH_LS1088A
default y
select RESV_RAM
help
@@ -116,6 +139,7 @@ config FSL_PCIE_COMPAT
default "fsl,ls1043a-pcie" if ARCH_LS1043A
default "fsl,ls1046a-pcie" if ARCH_LS1046A
default "fsl,ls2080a-pcie" if ARCH_LS2080A
+ default "fsl,ls1088a-pcie" if ARCH_LS1088A
help
This compatible is used to find pci controller node in Kernel DT
to complete fixup.
@@ -230,6 +254,7 @@ config MAX_CPUS
default 4 if ARCH_LS1043A
default 4 if ARCH_LS1046A
default 16 if ARCH_LS2080A
+ default 8 if ARCH_LS1088A
default 1
help
Set this number to the maximum number of possible CPUs in the SoC.
@@ -261,10 +286,10 @@ config SYS_CCI400_OFFSET
config SYS_FSL_IFC_BANK_COUNT
int "Maximum banks of Integrated flash controller"
- depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
+ depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
default 4 if ARCH_LS1043A
default 4 if ARCH_LS1046A
- default 8 if ARCH_LS2080A
+ default 8 if ARCH_LS2080A || ARCH_LS1088A
config SYS_FSL_HAS_CCI400
bool
@@ -313,6 +338,7 @@ config SYS_FSL_PCLK_DIV
int "Platform clock divider"
default 1 if ARCH_LS1043A
default 1 if ARCH_LS1046A
+ default 1 if ARCH_LS1088A
default 2
help
This is the divider that is used to derive Platform clock from
@@ -406,7 +432,8 @@ config SYS_FSL_ERRATUM_A009929
config SYS_MC_RSV_MEM_ALIGN
hex "Management Complex reserved me
