Re: [U-Boot] [PATCH v5 2/5] gpio: atmel_pio4: Rework to support DM & DT
Hi Wenyou, On 19 June 2016 at 20:02, Wenyou Yangwrote: > Rework the driver to support driver model and device tree, and > support to regard the pio4 pinctrl device as a child of > atmel_pio4 device. > > Signed-off-by: Wenyou Yang > --- > > Changes in v5: > - Update the clk API based on [PATCH] clk: convert API to match >reset/mailbox fstyle (http://patchwork.ozlabs.org/patch/625342/). > - Use clrbits_le32() to replace readl()/writel(). > - Fixed the return value, -ENODEV->-EINVAL. > - Remove check on dev_get_parent() return. > > Changes in v4: > - Remove the redundant log print. > > Changes in v3: > - Add bind callback to support the pinctl device regarding as >a child of atmel_pio4 device. > - Add clock support. > > Changes in v2: None > > drivers/gpio/Kconfig | 2 +- > drivers/gpio/atmel_pio4.c | 138 > ++ > 2 files changed, 117 insertions(+), 23 deletions(-) Reviewed-by: Simon Glass Minor comment below. > > diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig > index 73b862d..3332dab 100644 > --- a/drivers/gpio/Kconfig > +++ b/drivers/gpio/Kconfig > @@ -30,7 +30,7 @@ config DWAPB_GPIO > > config ATMEL_PIO4 > bool "ATMEL PIO4 driver" > - depends on DM > + depends on DM_GPIO > default n > help > Say yes here to support the Atmel PIO4 driver. > diff --git a/drivers/gpio/atmel_pio4.c b/drivers/gpio/atmel_pio4.c > index 84e8cc5..d1a59ba 100644 > --- a/drivers/gpio/atmel_pio4.c > +++ b/drivers/gpio/atmel_pio4.c > @@ -7,11 +7,17 @@ > * SPDX-License-Identifier:GPL-2.0+ > */ > #include > +#include > #include > +#include > +#include > #include > +#include > #include > #include > > +DECLARE_GLOBAL_DATA_PTR; > + > static struct atmel_pio4_port *atmel_pio4_port_base(u32 port) > { > struct atmel_pio4_port *base = NULL; > @@ -165,15 +171,37 @@ int atmel_pio4_get_pio_input(u32 port, u32 pin) > } > > #ifdef CONFIG_DM_GPIO > + > +struct atmel_pioctrl_data { > + u32 nbanks; > +}; > + > +struct atmel_pio4_platdata { > + struct atmel_pio4_port *reg_base; > +}; > + > +static struct atmel_pio4_port *atmel_pio4_bank_base(struct udevice *dev, > + u32 bank) > +{ > + struct atmel_pio4_platdata *plat = dev_get_platdata(dev); > + struct atmel_pio4_port *port_base = > + (struct atmel_pio4_port *)((u32)plat->reg_base + > + ATMEL_PIO_BANK_OFFSET * bank); > + > + return port_base; > +} > + > static int atmel_pio4_direction_input(struct udevice *dev, unsigned offset) > { > - struct at91_port_platdata *plat = dev_get_platdata(dev); > - struct atmel_pio4_port *port_base = (atmel_pio4_port > *)plat->base_addr; > - u32 mask = 0x01 << offset; > - u32 reg = ATMEL_PIO_CFGR_FUNC_GPIO; > + u32 bank = ATMEL_PIO_BANK(offset); > + u32 line = ATMEL_PIO_LINE(offset); > + struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank); > + u32 mask = BIT(line); > > writel(mask, _base->mskr); > - writel(reg, _base->cfgr); > + > + clrbits_le32(_base->cfgr, > +ATMEL_PIO_CFGR_FUNC_MASK | ATMEL_PIO_DIR_MASK); > > return 0; > } > @@ -181,13 +209,15 @@ static int atmel_pio4_direction_input(struct udevice > *dev, unsigned offset) > static int atmel_pio4_direction_output(struct udevice *dev, >unsigned offset, int value) > { > - struct at91_port_platdata *plat = dev_get_platdata(dev); > - struct atmel_pio4_port *port_base = (atmel_pio4_port > *)plat->base_addr; > - u32 mask = 0x01 << offset; > - u32 reg = ATMEL_PIO_CFGR_FUNC_GPIO | ATMEL_PIO_DIR_MASK; > + u32 bank = ATMEL_PIO_BANK(offset); > + u32 line = ATMEL_PIO_LINE(offset); > + struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank); > + u32 mask = BIT(line); > > writel(mask, _base->mskr); > - writel(reg, _base->cfgr); > + > + clrsetbits_le32(_base->cfgr, > + ATMEL_PIO_CFGR_FUNC_MASK, ATMEL_PIO_DIR_MASK); > > if (value) > writel(mask, _base->sodr); > @@ -199,9 +229,10 @@ static int atmel_pio4_direction_output(struct udevice > *dev, > > static int atmel_pio4_get_value(struct udevice *dev, unsigned offset) > { > - struct at91_port_platdata *plat = dev_get_platdata(dev); > - struct atmel_pio4_port *port_base = (atmel_pio4_port > *)plat->base_addr; > - u32 mask = 0x01 << offset; > + u32 bank = ATMEL_PIO_BANK(offset); > + u32 line = ATMEL_PIO_LINE(offset); > + struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank); > + u32 mask = BIT(line); > > return (readl(_base->pdsr) & mask) ? 1 : 0; > } > @@ -209,9 +240,10 @@ static int
[U-Boot] [PATCH v5 2/5] gpio: atmel_pio4: Rework to support DM & DT
Rework the driver to support driver model and device tree, and support to regard the pio4 pinctrl device as a child of atmel_pio4 device. Signed-off-by: Wenyou Yang--- Changes in v5: - Update the clk API based on [PATCH] clk: convert API to match reset/mailbox fstyle (http://patchwork.ozlabs.org/patch/625342/). - Use clrbits_le32() to replace readl()/writel(). - Fixed the return value, -ENODEV->-EINVAL. - Remove check on dev_get_parent() return. Changes in v4: - Remove the redundant log print. Changes in v3: - Add bind callback to support the pinctl device regarding as a child of atmel_pio4 device. - Add clock support. Changes in v2: None drivers/gpio/Kconfig | 2 +- drivers/gpio/atmel_pio4.c | 138 ++ 2 files changed, 117 insertions(+), 23 deletions(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 73b862d..3332dab 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -30,7 +30,7 @@ config DWAPB_GPIO config ATMEL_PIO4 bool "ATMEL PIO4 driver" - depends on DM + depends on DM_GPIO default n help Say yes here to support the Atmel PIO4 driver. diff --git a/drivers/gpio/atmel_pio4.c b/drivers/gpio/atmel_pio4.c index 84e8cc5..d1a59ba 100644 --- a/drivers/gpio/atmel_pio4.c +++ b/drivers/gpio/atmel_pio4.c @@ -7,11 +7,17 @@ * SPDX-License-Identifier:GPL-2.0+ */ #include +#include #include +#include +#include #include +#include #include #include +DECLARE_GLOBAL_DATA_PTR; + static struct atmel_pio4_port *atmel_pio4_port_base(u32 port) { struct atmel_pio4_port *base = NULL; @@ -165,15 +171,37 @@ int atmel_pio4_get_pio_input(u32 port, u32 pin) } #ifdef CONFIG_DM_GPIO + +struct atmel_pioctrl_data { + u32 nbanks; +}; + +struct atmel_pio4_platdata { + struct atmel_pio4_port *reg_base; +}; + +static struct atmel_pio4_port *atmel_pio4_bank_base(struct udevice *dev, + u32 bank) +{ + struct atmel_pio4_platdata *plat = dev_get_platdata(dev); + struct atmel_pio4_port *port_base = + (struct atmel_pio4_port *)((u32)plat->reg_base + + ATMEL_PIO_BANK_OFFSET * bank); + + return port_base; +} + static int atmel_pio4_direction_input(struct udevice *dev, unsigned offset) { - struct at91_port_platdata *plat = dev_get_platdata(dev); - struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr; - u32 mask = 0x01 << offset; - u32 reg = ATMEL_PIO_CFGR_FUNC_GPIO; + u32 bank = ATMEL_PIO_BANK(offset); + u32 line = ATMEL_PIO_LINE(offset); + struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank); + u32 mask = BIT(line); writel(mask, _base->mskr); - writel(reg, _base->cfgr); + + clrbits_le32(_base->cfgr, +ATMEL_PIO_CFGR_FUNC_MASK | ATMEL_PIO_DIR_MASK); return 0; } @@ -181,13 +209,15 @@ static int atmel_pio4_direction_input(struct udevice *dev, unsigned offset) static int atmel_pio4_direction_output(struct udevice *dev, unsigned offset, int value) { - struct at91_port_platdata *plat = dev_get_platdata(dev); - struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr; - u32 mask = 0x01 << offset; - u32 reg = ATMEL_PIO_CFGR_FUNC_GPIO | ATMEL_PIO_DIR_MASK; + u32 bank = ATMEL_PIO_BANK(offset); + u32 line = ATMEL_PIO_LINE(offset); + struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank); + u32 mask = BIT(line); writel(mask, _base->mskr); - writel(reg, _base->cfgr); + + clrsetbits_le32(_base->cfgr, + ATMEL_PIO_CFGR_FUNC_MASK, ATMEL_PIO_DIR_MASK); if (value) writel(mask, _base->sodr); @@ -199,9 +229,10 @@ static int atmel_pio4_direction_output(struct udevice *dev, static int atmel_pio4_get_value(struct udevice *dev, unsigned offset) { - struct at91_port_platdata *plat = dev_get_platdata(dev); - struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr; - u32 mask = 0x01 << offset; + u32 bank = ATMEL_PIO_BANK(offset); + u32 line = ATMEL_PIO_LINE(offset); + struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank); + u32 mask = BIT(line); return (readl(_base->pdsr) & mask) ? 1 : 0; } @@ -209,9 +240,10 @@ static int atmel_pio4_get_value(struct udevice *dev, unsigned offset) static int atmel_pio4_set_value(struct udevice *dev, unsigned offset, int value) { - struct at91_port_platdata *plat = dev_get_platdata(dev); - struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr; - u32 mask = 0x01 << offset; + u32 bank = ATMEL_PIO_BANK(offset); + u32 line =