Re: [U-Boot] [PATCH v6 1/5] spi: cadence_qspi: move trigger base configuration in init

[Jagan Teki]

On 11 September 2015 at 23:58, Vikas Manocha  wrote:
> No need to configure indirect trigger address for every read/write.
>
> Signed-off-by: Vikas Manocha 
> ---
>
> Changes in v6: None
> Changes in v5: fixed type cast compilation warnings.
> Changes in v4: removed extra type casts.
> Changes in v3: added commit message & removed extra bracket.
> Changes in v2: Rebased to master
>
>  drivers/spi/cadence_qspi_apb.c |9 ++---
>  1 file changed, 2 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
> index d053407..d377ad1 100644
> --- a/drivers/spi/cadence_qspi_apb.c
> +++ b/drivers/spi/cadence_qspi_apb.c
> @@ -534,6 +534,8 @@ void cadence_qspi_apb_controller_init(struct 
> cadence_spi_platdata *plat)
>
> /* Indirect mode configurations */
> writel((plat->sram_size/2), plat->regbase + CQSPI_REG_SRAMPARTITION);
> +   writel((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK,
> +  plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
>
> /* Disable all interrupts */
> writel(0, plat->regbase + CQSPI_REG_IRQMASK);
> @@ -693,10 +695,6 @@ int cadence_qspi_apb_indirect_read_setup(struct 
> cadence_spi_platdata *plat,
> /* for normal read (only ramtron as of now) */
> addr_bytes = cmdlen - 1;
>
> -   /* Setup the indirect trigger address */
> -   writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
> -  plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
> -
> /* Configure the opcode */
> rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB;
>
> @@ -790,9 +788,6 @@ int cadence_qspi_apb_indirect_write_setup(struct 
> cadence_spi_platdata *plat,
>cmdlen, (unsigned int)cmdbuf);
> return -EINVAL;
> }
> -   /* Setup the indirect trigger address */
> -   writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
> -  plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
>
> /* Configure the opcode */
> reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB;
> --
> 1.7.9.5
>
> ___
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Reviewed-by: Jagan Teki 

thanks!
-- 
Jagan | openedev.
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[U-Boot] [PATCH v6 1/5] spi: cadence_qspi: move trigger base configuration in init

[Vikas Manocha]

No need to configure indirect trigger address for every read/write.

Signed-off-by: Vikas Manocha 
---

Changes in v6: None
Changes in v5: fixed type cast compilation warnings.
Changes in v4: removed extra type casts.
Changes in v3: added commit message & removed extra bracket.
Changes in v2: Rebased to master

 drivers/spi/cadence_qspi_apb.c |9 ++---
 1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index d053407..d377ad1 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -534,6 +534,8 @@ void cadence_qspi_apb_controller_init(struct 
cadence_spi_platdata *plat)
 
/* Indirect mode configurations */
writel((plat->sram_size/2), plat->regbase + CQSPI_REG_SRAMPARTITION);
+   writel((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK,
+  plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
 
/* Disable all interrupts */
writel(0, plat->regbase + CQSPI_REG_IRQMASK);
@@ -693,10 +695,6 @@ int cadence_qspi_apb_indirect_read_setup(struct 
cadence_spi_platdata *plat,
/* for normal read (only ramtron as of now) */
addr_bytes = cmdlen - 1;
 
-   /* Setup the indirect trigger address */
-   writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
-  plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
-
/* Configure the opcode */
rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB;
 
@@ -790,9 +788,6 @@ int cadence_qspi_apb_indirect_write_setup(struct 
cadence_spi_platdata *plat,
   cmdlen, (unsigned int)cmdbuf);
return -EINVAL;
}
-   /* Setup the indirect trigger address */
-   writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
-  plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
 
/* Configure the opcode */
reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB;
-- 
1.7.9.5

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