Re: [U-Boot] [PATCH v8 4/7] arm: socfpga: Enable FPGA driver on SPL
On 06/19/2017 05:32 AM, Chee, Tien Fong wrote: > On Sel, 2017-06-13 at 11:05 +0200, Marek Vasut wrote: >> On 06/13/2017 05:26 AM, Chee, Tien Fong wrote: >>> >>> On Isn, 2017-06-12 at 16:38 +0800, Chee, Tien Fong wrote: On Jum, 2017-06-09 at 08:52 -0500, Dinh Nguyen wrote: > > > > On 06/09/2017 03:25 AM, Marek Vasut wrote: >> >> >> >> >> I didn't really look since we still have a discussion open on >> V8 >> . >> There >> is no point in sending new versions while discussion is still >> open. >> Also, I'd like some review from Ley/Dinh > I've reviewed v6 and gave my Reviewed-by. Now I see there's a > v10. > Should I be reviewing v10 or wait for a new version? > > Dinh If Marek agree with my planning, code cleaning for gen5 in different patchset. v10 is updated based on Mareks' comments on v9, then v10 should be the final version. Thanks. >>> Hi Marek, >>> >>> I think Dinh is still waiting answer from you. >> Thanks for reminding me daily. I'm actually on vacation, so sorry for >> the delayed reply. I have no idea what question I have to Marek, but it probably doesn't matter anymore. >> >>> >>> Could you please to >>> advice? >> Actually I lost track of what's going on here, we're still having >> discussion on V8 and I already have V10 in my mailbox. I have two >> suggestions: >> 1) Slow down, bombarding people with new versions of patches every >> day >>does not help at all. Give people some space to review the >> patchset, >>discuss and let the discussion settle, then submit a new set. That >>can take a week or more, so let's establish a rule that you will >> not >>submit more than one version of the patchset each week unless >>explicitly asked. OK ? +1 in agreement. Just because you're in a hurry to get a patchset reviewed and accepted, doesn't mean the rest of us are in a hurry to review for you. If you had done things right and planned to upstream first, often, and frequently, you'd not be trying to push 10 versions of patchset in 2 weeks down our throat. >> 2) I'd like AB/RB from Dinh on this set, yes. >> > Hi Dinh, > > Could you help to review? Sorry, I also just got back from vacation. Will try to get to it this week. Dinh ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v8 4/7] arm: socfpga: Enable FPGA driver on SPL
On Sel, 2017-06-13 at 11:05 +0200, Marek Vasut wrote: > On 06/13/2017 05:26 AM, Chee, Tien Fong wrote: > > > > On Isn, 2017-06-12 at 16:38 +0800, Chee, Tien Fong wrote: > > > > > > On Jum, 2017-06-09 at 08:52 -0500, Dinh Nguyen wrote: > > > > > > > > > > > > > > > > On 06/09/2017 03:25 AM, Marek Vasut wrote: > > > > > > > > > > > > > > > > > > > > > > > > > I didn't really look since we still have a discussion open on > > > > > V8 > > > > > . > > > > > There > > > > > is no point in sending new versions while discussion is still > > > > > open. > > > > > Also, I'd like some review from Ley/Dinh > > > > I've reviewed v6 and gave my Reviewed-by. Now I see there's a > > > > v10. > > > > Should I be reviewing v10 or wait for a new version? > > > > > > > > Dinh > > > If Marek agree with my planning, code cleaning for gen5 in > > > different > > > patchset. v10 is updated based on Mareks' comments on v9, then > > > v10 > > > should be the final version. > > > > > > Thanks. > > Hi Marek, > > > > I think Dinh is still waiting answer from you. > Thanks for reminding me daily. I'm actually on vacation, so sorry for > the delayed reply. > > > > > Could you please to > > advice? > Actually I lost track of what's going on here, we're still having > discussion on V8 and I already have V10 in my mailbox. I have two > suggestions: > 1) Slow down, bombarding people with new versions of patches every > day > does not help at all. Give people some space to review the > patchset, > discuss and let the discussion settle, then submit a new set. That > can take a week or more, so let's establish a rule that you will > not > submit more than one version of the patchset each week unless > explicitly asked. OK ? > 2) I'd like AB/RB from Dinh on this set, yes. > Hi Dinh, Could you help to review? Thanks. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v8 4/7] arm: socfpga: Enable FPGA driver on SPL
On Sel, 2017-06-13 at 11:05 +0200, Marek Vasut wrote: > > On 06/13/2017 05:26 AM, Chee, Tien Fong wrote: > > > > > > On Isn, 2017-06-12 at 16:38 +0800, Chee, Tien Fong wrote: > > > > > > > > > On Jum, 2017-06-09 at 08:52 -0500, Dinh Nguyen wrote: > > > > > > > > > > > > > > > > > > > > On 06/09/2017 03:25 AM, Marek Vasut wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I didn't really look since we still have a discussion open on > > > > > V8 > > > > > . > > > > > There > > > > > is no point in sending new versions while discussion is still > > > > > open. > > > > > Also, I'd like some review from Ley/Dinh > > > > I've reviewed v6 and gave my Reviewed-by. Now I see there's a > > > > v10. > > > > Should I be reviewing v10 or wait for a new version? > > > > > > > > Dinh > > > If Marek agree with my planning, code cleaning for gen5 in > > > different > > > patchset. v10 is updated based on Mareks' comments on v9, then > > > v10 > > > should be the final version. > > > > > > Thanks. > > Hi Marek, > > > > I think Dinh is still waiting answer from you. > Thanks for reminding me daily. I'm actually on vacation, so sorry for > the delayed reply. > Sorry for that, i don't know you are on vacation, i thought we are confused, hence i was trying to make it clear :) . > > > > > > > Could you please to > > advice? > Actually I lost track of what's going on here, we're still having > discussion on V8 and I already have V10 in my mailbox. I have two > suggestions: > 1) Slow down, bombarding people with new versions of patches every > day > does not help at all. Give people some space to review the > patchset, > discuss and let the discussion settle, then submit a new set. That > can take a week or more, so let's establish a rule that you will > not > submit more than one version of the patchset each week unless > explicitly asked. OK ? Okay, sure. > > 2) I'd like AB/RB from Dinh on this set, yes. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v8 4/7] arm: socfpga: Enable FPGA driver on SPL
On 06/13/2017 05:26 AM, Chee, Tien Fong wrote: > On Isn, 2017-06-12 at 16:38 +0800, Chee, Tien Fong wrote: >> On Jum, 2017-06-09 at 08:52 -0500, Dinh Nguyen wrote: >>> >>> >>> On 06/09/2017 03:25 AM, Marek Vasut wrote: I didn't really look since we still have a discussion open on V8 . There is no point in sending new versions while discussion is still open. Also, I'd like some review from Ley/Dinh >>> I've reviewed v6 and gave my Reviewed-by. Now I see there's a v10. >>> Should I be reviewing v10 or wait for a new version? >>> >>> Dinh >> If Marek agree with my planning, code cleaning for gen5 in different >> patchset. v10 is updated based on Mareks' comments on v9, then v10 >> should be the final version. >> >> Thanks. > > Hi Marek, > > I think Dinh is still waiting answer from you. Thanks for reminding me daily. I'm actually on vacation, so sorry for the delayed reply. > Could you please to > advice? Actually I lost track of what's going on here, we're still having discussion on V8 and I already have V10 in my mailbox. I have two suggestions: 1) Slow down, bombarding people with new versions of patches every day does not help at all. Give people some space to review the patchset, discuss and let the discussion settle, then submit a new set. That can take a week or more, so let's establish a rule that you will not submit more than one version of the patchset each week unless explicitly asked. OK ? 2) I'd like AB/RB from Dinh on this set, yes. -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v8 4/7] arm: socfpga: Enable FPGA driver on SPL
On Isn, 2017-06-12 at 16:38 +0800, Chee, Tien Fong wrote: > On Jum, 2017-06-09 at 08:52 -0500, Dinh Nguyen wrote: > > > > > > On 06/09/2017 03:25 AM, Marek Vasut wrote: > > > > > > > > > > > > I didn't really look since we still have a discussion open on V8 > > > . > > > There > > > is no point in sending new versions while discussion is still > > > open. > > > Also, I'd like some review from Ley/Dinh > > I've reviewed v6 and gave my Reviewed-by. Now I see there's a v10. > > Should I be reviewing v10 or wait for a new version? > > > > Dinh > If Marek agree with my planning, code cleaning for gen5 in different > patchset. v10 is updated based on Mareks' comments on v9, then v10 > should be the final version. > > Thanks. Hi Marek, I think Dinh is still waiting answer from you. Could you please to advice? Thanks. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v8 4/7] arm: socfpga: Enable FPGA driver on SPL
On Jum, 2017-06-09 at 08:52 -0500, Dinh Nguyen wrote: > > On 06/09/2017 03:25 AM, Marek Vasut wrote: > > > > > > I didn't really look since we still have a discussion open on V8 . > > There > > is no point in sending new versions while discussion is still open. > > Also, I'd like some review from Ley/Dinh > I've reviewed v6 and gave my Reviewed-by. Now I see there's a v10. > Should I be reviewing v10 or wait for a new version? > > Dinh If Marek agree with my planning, code cleaning for gen5 in different patchset. v10 is updated based on Mareks' comments on v9, then v10 should be the final version. Thanks. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v8 4/7] arm: socfpga: Enable FPGA driver on SPL
On 06/09/2017 03:25 AM, Marek Vasut wrote: > > I didn't really look since we still have a discussion open on V8 . There > is no point in sending new versions while discussion is still open. > Also, I'd like some review from Ley/Dinh I've reviewed v6 and gave my Reviewed-by. Now I see there's a v10. Should I be reviewing v10 or wait for a new version? Dinh ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v8 4/7] arm: socfpga: Enable FPGA driver on SPL
On 06/09/2017 05:39 AM, Chee, Tien Fong wrote: > On Kha, 2017-06-08 at 14:14 +0200, Marek Vasut wrote: >> On 06/08/2017 05:40 AM, Chee, Tien Fong wrote: >> [...] >>> > >> >> Any safety guideline? >> I checked the spl.map, we still have 10K left after >> calculation >> including bss size. >> > I compiled all Intel fpga related defconfigs, and we have 9K > free > based > on total 64K memory size. SO building PFGA driver would > contribute > around 1~2K only to SPL size. Do you have concern with that? Yes > > > If you have concern, i would remove patch 6, keep fpga_manager > intact. Can't you rework things such that they don't add useless code into the SPL instead ? >>> I checked the codes yesterday, mostly are bridge, and HPS-FPGA >>> interface configuration in SPL. So, i think we can try to remove >>> them >>> as they are not required in SPL, but i need more time to test it >>> out >>> and ensure this change doesn't break anything. >> That's fine, we're past RC1 anyway. >> >>> >>> To avoid impact the progress of submitting the rest of patchset as >>> they >>> are still pending until this patchset is accepted , so i suggest we >>> can >>> do it in later. So, i will keep fpga_manager in there. >>> >>> sounds good to you? >> You have about two months till the next MW opens , so if you want to >> flesh this out, please do. >> > Sure, this changes will be in separate patchset, as this is for codes > cleaning up and refactoring on gen5. Great, cleanup can go in first. > So, how about the Add Arria 10 FPGA driver v10 patchset overall? > Anything else i miss? I didn't really look since we still have a discussion open on V8 . There is no point in sending new versions while discussion is still open. Also, I'd like some review from Ley/Dinh -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v8 4/7] arm: socfpga: Enable FPGA driver on SPL
On Kha, 2017-06-08 at 14:14 +0200, Marek Vasut wrote: > On 06/08/2017 05:40 AM, Chee, Tien Fong wrote: > [...] > > > > > > > > > > > > > > > > > > > Any safety guideline? > > > > > I checked the spl.map, we still have 10K left after > > > > > calculation > > > > > including bss size. > > > > > > > > > I compiled all Intel fpga related defconfigs, and we have 9K > > > > free > > > > based > > > > on total 64K memory size. SO building PFGA driver would > > > > contribute > > > > around 1~2K only to SPL size. Do you have concern with that? > > > Yes > > > > > > > > > > > > > > > If you have concern, i would remove patch 6, keep fpga_manager > > > > intact. > > > Can't you rework things such that they don't add useless code > > > into > > > the > > > SPL instead ? > > > > > I checked the codes yesterday, mostly are bridge, and HPS-FPGA > > interface configuration in SPL. So, i think we can try to remove > > them > > as they are not required in SPL, but i need more time to test it > > out > > and ensure this change doesn't break anything. > That's fine, we're past RC1 anyway. > > > > > To avoid impact the progress of submitting the rest of patchset as > > they > > are still pending until this patchset is accepted , so i suggest we > > can > > do it in later. So, i will keep fpga_manager in there. > > > > sounds good to you? > You have about two months till the next MW opens , so if you want to > flesh this out, please do. > Sure, this changes will be in separate patchset, as this is for codes cleaning up and refactoring on gen5. So, how about the Add Arria 10 FPGA driver v10 patchset overall? Anything else i miss? Thanks. > > > > > > > > > > > > > > > > > > > > > > > > > > > > Thanks. > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v8 4/7] arm: socfpga: Enable FPGA driver on SPL
On 06/08/2017 05:40 AM, Chee, Tien Fong wrote: [...] Any safety guideline? I checked the spl.map, we still have 10K left after calculation including bss size. >>> I compiled all Intel fpga related defconfigs, and we have 9K free >>> based >>> on total 64K memory size. SO building PFGA driver would contribute >>> around 1~2K only to SPL size. Do you have concern with that? >> Yes >> >>> >>> If you have concern, i would remove patch 6, keep fpga_manager >>> intact. >> Can't you rework things such that they don't add useless code into >> the >> SPL instead ? >> > I checked the codes yesterday, mostly are bridge, and HPS-FPGA > interface configuration in SPL. So, i think we can try to remove them > as they are not required in SPL, but i need more time to test it out > and ensure this change doesn't break anything. That's fine, we're past RC1 anyway. > To avoid impact the progress of submitting the rest of patchset as they > are still pending until this patchset is accepted , so i suggest we can > do it in later. So, i will keep fpga_manager in there. > > sounds good to you? You have about two months till the next MW opens , so if you want to flesh this out, please do. >>> Thanks. -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v8 4/7] arm: socfpga: Enable FPGA driver on SPL
On Rab, 2017-06-07 at 14:31 +0200, Marek Vasut wrote: > On 06/07/2017 01:26 PM, Chee, Tien Fong wrote: > > > > On Rab, 2017-06-07 at 16:04 +0800, Chee, Tien Fong wrote: > > > > > > On Rab, 2017-06-07 at 08:36 +0200, Marek Vasut wrote: > > > > > > > > > > > > On 06/07/2017 05:06 AM, Chee, Tien Fong wrote: > > > > > > > > > > > > > > > > > > > > On Sel, 2017-06-06 at 11:50 +0200, Marek Vasut wrote: > > > > > > > > > > > > > > > > > > > > > > > > On 06/06/2017 11:46 AM, Chee, Tien Fong wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Sel, 2017-06-06 at 11:41 +0200, Marek Vasut wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On 06/06/2017 11:36 AM, Chee, Tien Fong wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Sel, 2017-06-06 at 10:35 +0200, Marek Vasut wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On 06/06/2017 10:19 AM, Chee, Tien Fong wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Sel, 2017-06-06 at 10:03 +0200, Marek Vasut > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On 06/06/2017 08:35 AM, tien.fong.c...@intel.co > > > > > > > > > > > > m > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > From: Tien Fong Chee > > > > > > > > > > > > m> > > > > > > > > > > > > > > > > > > > > > > > > > > This patch is for enabling FPGA driver > > > > > > > > > > > > > support on > > > > > > > > > > > > > SPL > > > > > > > > > > > > Why would we want that on Gen5 ? I believe this > > > > > > > > > > > > is > > > > > > > > > > > > only > > > > > > > > > > > > needed on > > > > > > > > > > > > Gen10. > > > > > > > > > > > > > > > > > > > > > > > I already moved the fpga_manager driver into > > > > > > > > > > > drivers/fpga/ > > > > > > > > > > > on > > > > > > > > > > > patch > > > > > > > > > > > 6, > > > > > > > > > > > and fpga_manager drivers are required on SPL. > > > > > > > > > > > Actually > > > > > > > > > > > fpga_manager > > > > > > > > > > > driver should be part of the drivers/fpga. > > > > > > > > > > I think I miss some fundamental piece of > > > > > > > > > > information . > > > > > > > > > > Why > > > > > > > > > > would > > > > > > > > > > I > > > > > > > > > > need > > > > > > > > > > anything from the FPGA framework in SPL on Gen5 ? > > > > > > > > > > It is > > > > > > > > > > not > > > > > > > > > > needed > > > > > > > > > > thus > > > > > > > > > > far. Is it because you shuffled some of the code > > > > > > > > > > around > > > > > > > > > > or > > > > > > > > > > what ? > > > > > > > > > > > > > > > > > > > Because we need to know some status and mode type > > > > > > > > > from > > > > > > > > > FPGA > > > > > > > > > even we > > > > > > > > > did > > > > > > > > > not program FPGA in SPL. > > > > > > > > But we didn't have this option enabled before and > > > > > > > > everything > > > > > > > > worked > > > > > > > > on > > > > > > > > gen5, why do we need it now ? > > > > > > > > > > > > > > > Because i already move them into fpga driver, because > > > > > > > those > > > > > > > functions > > > > > > > should be part of fpga driver. So, this moving happen in > > > > > > > patch > > > > > > > 6. > > > > > > I see. Does enabling the FPGA_SPL stuff pull in any of the > > > > > > FPGA > > > > > > framework ? Does the size of the Gen5 SPL change before and > > > > > > after > > > > > > this > > > > > > patchset ? If you did not check, please do. > > > > > Yeah, i confirm FPGA driver is availabled in SPL. A bit > > > > > change in > > > > > size, > > > > > 1~2K more. I did the test on our devkits also. > > > > OK, so that's not acceptable because we're already very close > > > > to > > > > the > > > > size limit of the SPL. > > > > > > > Any safety guideline? > > > I checked the spl.map, we still have 10K left after calculation > > > including bss size. > > > > > I compiled all Intel fpga related defconfigs, and we have 9K free > > based > > on total 64K memory size. SO building PFGA driver would contribute > > around 1~2K only to SPL size. Do you have concern with that? > Yes > > > > > If you have concern, i would remove patch 6, keep fpga_manager > > intact. > Can't you rework things such that they don't add useless code into > the > SPL instead ? > I checked the codes yesterday, mostly are bridge, and HPS-FPGA interface configuration in SPL. So, i think we can try to remove t
Re: [U-Boot] [PATCH v8 4/7] arm: socfpga: Enable FPGA driver on SPL
On 06/07/2017 01:26 PM, Chee, Tien Fong wrote: > On Rab, 2017-06-07 at 16:04 +0800, Chee, Tien Fong wrote: >> On Rab, 2017-06-07 at 08:36 +0200, Marek Vasut wrote: >>> >>> On 06/07/2017 05:06 AM, Chee, Tien Fong wrote: On Sel, 2017-06-06 at 11:50 +0200, Marek Vasut wrote: > > > On 06/06/2017 11:46 AM, Chee, Tien Fong wrote: >> >> >> >> On Sel, 2017-06-06 at 11:41 +0200, Marek Vasut wrote: >>> >>> >>> >>> On 06/06/2017 11:36 AM, Chee, Tien Fong wrote: On Sel, 2017-06-06 at 10:35 +0200, Marek Vasut wrote: > > > > > On 06/06/2017 10:19 AM, Chee, Tien Fong wrote: >> >> >> >> >> >> On Sel, 2017-06-06 at 10:03 +0200, Marek Vasut wrote: >>> >>> >>> >>> >>> >>> On 06/06/2017 08:35 AM, tien.fong.c...@intel.com >>> wrote: From: Tien Fong Chee This patch is for enabling FPGA driver support on SPL >>> Why would we want that on Gen5 ? I believe this is >>> only >>> needed on >>> Gen10. >>> >> I already moved the fpga_manager driver into >> drivers/fpga/ >> on >> patch >> 6, >> and fpga_manager drivers are required on SPL. >> Actually >> fpga_manager >> driver should be part of the drivers/fpga. > I think I miss some fundamental piece of information . > Why > would > I > need > anything from the FPGA framework in SPL on Gen5 ? It is > not > needed > thus > far. Is it because you shuffled some of the code around > or > what ? > Because we need to know some status and mode type from FPGA even we did not program FPGA in SPL. >>> But we didn't have this option enabled before and >>> everything >>> worked >>> on >>> gen5, why do we need it now ? >>> >> Because i already move them into fpga driver, because those >> functions >> should be part of fpga driver. So, this moving happen in >> patch >> 6. > I see. Does enabling the FPGA_SPL stuff pull in any of the FPGA > framework ? Does the size of the Gen5 SPL change before and > after > this > patchset ? If you did not check, please do. Yeah, i confirm FPGA driver is availabled in SPL. A bit change in size, 1~2K more. I did the test on our devkits also. >>> OK, so that's not acceptable because we're already very close to >>> the >>> size limit of the SPL. >>> >> Any safety guideline? >> I checked the spl.map, we still have 10K left after calculation >> including bss size. >> > I compiled all Intel fpga related defconfigs, and we have 9K free based > on total 64K memory size. SO building PFGA driver would contribute > around 1~2K only to SPL size. Do you have concern with that? Yes > If you have concern, i would remove patch 6, keep fpga_manager intact. Can't you rework things such that they don't add useless code into the SPL instead ? >> Thanks. -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v8 4/7] arm: socfpga: Enable FPGA driver on SPL
On 06/07/2017 10:04 AM, Chee, Tien Fong wrote: > On Rab, 2017-06-07 at 08:36 +0200, Marek Vasut wrote: >> On 06/07/2017 05:06 AM, Chee, Tien Fong wrote: >>> >>> On Sel, 2017-06-06 at 11:50 +0200, Marek Vasut wrote: On 06/06/2017 11:46 AM, Chee, Tien Fong wrote: > > > On Sel, 2017-06-06 at 11:41 +0200, Marek Vasut wrote: >> >> >> On 06/06/2017 11:36 AM, Chee, Tien Fong wrote: >>> >>> >>> >>> On Sel, 2017-06-06 at 10:35 +0200, Marek Vasut wrote: On 06/06/2017 10:19 AM, Chee, Tien Fong wrote: > > > > > On Sel, 2017-06-06 at 10:03 +0200, Marek Vasut wrote: >> >> >> >> >> On 06/06/2017 08:35 AM, tien.fong.c...@intel.com >> wrote: >>> >>> >>> >>> >>> >>> From: Tien Fong Chee >>> >>> This patch is for enabling FPGA driver support on >>> SPL >> Why would we want that on Gen5 ? I believe this is >> only >> needed on >> Gen10. >> > I already moved the fpga_manager driver into > drivers/fpga/ > on > patch > 6, > and fpga_manager drivers are required on SPL. Actually > fpga_manager > driver should be part of the drivers/fpga. I think I miss some fundamental piece of information . Why would I need anything from the FPGA framework in SPL on Gen5 ? It is not needed thus far. Is it because you shuffled some of the code around or what ? >>> Because we need to know some status and mode type from FPGA >>> even we >>> did >>> not program FPGA in SPL. >> But we didn't have this option enabled before and everything >> worked >> on >> gen5, why do we need it now ? >> > Because i already move them into fpga driver, because those > functions > should be part of fpga driver. So, this moving happen in patch > 6. I see. Does enabling the FPGA_SPL stuff pull in any of the FPGA framework ? Does the size of the Gen5 SPL change before and after this patchset ? If you did not check, please do. >>> Yeah, i confirm FPGA driver is availabled in SPL. A bit change in >>> size, >>> 1~2K more. I did the test on our devkits also. >> OK, so that's not acceptable because we're already very close to the >> size limit of the SPL. >> > Any safety guideline? > I checked the spl.map, we still have 10K left after calculation > including bss size. Once the size is like 49k , the SPL is too big and it sporadically fails to boot. Why, I don't know. -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v8 4/7] arm: socfpga: Enable FPGA driver on SPL
On Rab, 2017-06-07 at 16:04 +0800, Chee, Tien Fong wrote: > On Rab, 2017-06-07 at 08:36 +0200, Marek Vasut wrote: > > > > On 06/07/2017 05:06 AM, Chee, Tien Fong wrote: > > > > > > > > > On Sel, 2017-06-06 at 11:50 +0200, Marek Vasut wrote: > > > > > > > > > > > > On 06/06/2017 11:46 AM, Chee, Tien Fong wrote: > > > > > > > > > > > > > > > > > > > > On Sel, 2017-06-06 at 11:41 +0200, Marek Vasut wrote: > > > > > > > > > > > > > > > > > > > > > > > > On 06/06/2017 11:36 AM, Chee, Tien Fong wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Sel, 2017-06-06 at 10:35 +0200, Marek Vasut wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On 06/06/2017 10:19 AM, Chee, Tien Fong wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Sel, 2017-06-06 at 10:03 +0200, Marek Vasut wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On 06/06/2017 08:35 AM, tien.fong.c...@intel.com > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > From: Tien Fong Chee > > > > > > > > > > > > > > > > > > > > > > This patch is for enabling FPGA driver support on > > > > > > > > > > > SPL > > > > > > > > > > Why would we want that on Gen5 ? I believe this is > > > > > > > > > > only > > > > > > > > > > needed on > > > > > > > > > > Gen10. > > > > > > > > > > > > > > > > > > > I already moved the fpga_manager driver into > > > > > > > > > drivers/fpga/ > > > > > > > > > on > > > > > > > > > patch > > > > > > > > > 6, > > > > > > > > > and fpga_manager drivers are required on SPL. > > > > > > > > > Actually > > > > > > > > > fpga_manager > > > > > > > > > driver should be part of the drivers/fpga. > > > > > > > > I think I miss some fundamental piece of information . > > > > > > > > Why > > > > > > > > would > > > > > > > > I > > > > > > > > need > > > > > > > > anything from the FPGA framework in SPL on Gen5 ? It is > > > > > > > > not > > > > > > > > needed > > > > > > > > thus > > > > > > > > far. Is it because you shuffled some of the code around > > > > > > > > or > > > > > > > > what ? > > > > > > > > > > > > > > > Because we need to know some status and mode type from > > > > > > > FPGA > > > > > > > even we > > > > > > > did > > > > > > > not program FPGA in SPL. > > > > > > But we didn't have this option enabled before and > > > > > > everything > > > > > > worked > > > > > > on > > > > > > gen5, why do we need it now ? > > > > > > > > > > > Because i already move them into fpga driver, because those > > > > > functions > > > > > should be part of fpga driver. So, this moving happen in > > > > > patch > > > > > 6. > > > > I see. Does enabling the FPGA_SPL stuff pull in any of the FPGA > > > > framework ? Does the size of the Gen5 SPL change before and > > > > after > > > > this > > > > patchset ? If you did not check, please do. > > > Yeah, i confirm FPGA driver is availabled in SPL. A bit change in > > > size, > > > 1~2K more. I did the test on our devkits also. > > OK, so that's not acceptable because we're already very close to > > the > > size limit of the SPL. > > > Any safety guideline? > I checked the spl.map, we still have 10K left after calculation > including bss size. > I compiled all Intel fpga related defconfigs, and we have 9K free based on total 64K memory size. SO building PFGA driver would contribute around 1~2K only to SPL size. Do you have concern with that? If you have concern, i would remove patch 6, keep fpga_manager intact. > Thanks. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v8 4/7] arm: socfpga: Enable FPGA driver on SPL
On Rab, 2017-06-07 at 08:36 +0200, Marek Vasut wrote: > On 06/07/2017 05:06 AM, Chee, Tien Fong wrote: > > > > On Sel, 2017-06-06 at 11:50 +0200, Marek Vasut wrote: > > > > > > On 06/06/2017 11:46 AM, Chee, Tien Fong wrote: > > > > > > > > > > > > On Sel, 2017-06-06 at 11:41 +0200, Marek Vasut wrote: > > > > > > > > > > > > > > > On 06/06/2017 11:36 AM, Chee, Tien Fong wrote: > > > > > > > > > > > > > > > > > > > > > > > > On Sel, 2017-06-06 at 10:35 +0200, Marek Vasut wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > On 06/06/2017 10:19 AM, Chee, Tien Fong wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Sel, 2017-06-06 at 10:03 +0200, Marek Vasut wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On 06/06/2017 08:35 AM, tien.fong.c...@intel.com > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > From: Tien Fong Chee > > > > > > > > > > > > > > > > > > > > This patch is for enabling FPGA driver support on > > > > > > > > > > SPL > > > > > > > > > Why would we want that on Gen5 ? I believe this is > > > > > > > > > only > > > > > > > > > needed on > > > > > > > > > Gen10. > > > > > > > > > > > > > > > > > I already moved the fpga_manager driver into > > > > > > > > drivers/fpga/ > > > > > > > > on > > > > > > > > patch > > > > > > > > 6, > > > > > > > > and fpga_manager drivers are required on SPL. Actually > > > > > > > > fpga_manager > > > > > > > > driver should be part of the drivers/fpga. > > > > > > > I think I miss some fundamental piece of information . > > > > > > > Why > > > > > > > would > > > > > > > I > > > > > > > need > > > > > > > anything from the FPGA framework in SPL on Gen5 ? It is > > > > > > > not > > > > > > > needed > > > > > > > thus > > > > > > > far. Is it because you shuffled some of the code around > > > > > > > or > > > > > > > what ? > > > > > > > > > > > > > Because we need to know some status and mode type from FPGA > > > > > > even we > > > > > > did > > > > > > not program FPGA in SPL. > > > > > But we didn't have this option enabled before and everything > > > > > worked > > > > > on > > > > > gen5, why do we need it now ? > > > > > > > > > Because i already move them into fpga driver, because those > > > > functions > > > > should be part of fpga driver. So, this moving happen in patch > > > > 6. > > > I see. Does enabling the FPGA_SPL stuff pull in any of the FPGA > > > framework ? Does the size of the Gen5 SPL change before and after > > > this > > > patchset ? If you did not check, please do. > > Yeah, i confirm FPGA driver is availabled in SPL. A bit change in > > size, > > 1~2K more. I did the test on our devkits also. > OK, so that's not acceptable because we're already very close to the > size limit of the SPL. > Any safety guideline? I checked the spl.map, we still have 10K left after calculation including bss size. Thanks. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v8 4/7] arm: socfpga: Enable FPGA driver on SPL
On 06/07/2017 05:06 AM, Chee, Tien Fong wrote: > On Sel, 2017-06-06 at 11:50 +0200, Marek Vasut wrote: >> On 06/06/2017 11:46 AM, Chee, Tien Fong wrote: >>> >>> On Sel, 2017-06-06 at 11:41 +0200, Marek Vasut wrote: On 06/06/2017 11:36 AM, Chee, Tien Fong wrote: > > > On Sel, 2017-06-06 at 10:35 +0200, Marek Vasut wrote: >> >> >> On 06/06/2017 10:19 AM, Chee, Tien Fong wrote: >>> >>> >>> >>> On Sel, 2017-06-06 at 10:03 +0200, Marek Vasut wrote: On 06/06/2017 08:35 AM, tien.fong.c...@intel.com wrote: > > > > > From: Tien Fong Chee > > This patch is for enabling FPGA driver support on SPL Why would we want that on Gen5 ? I believe this is only needed on Gen10. >>> I already moved the fpga_manager driver into drivers/fpga/ >>> on >>> patch >>> 6, >>> and fpga_manager drivers are required on SPL. Actually >>> fpga_manager >>> driver should be part of the drivers/fpga. >> I think I miss some fundamental piece of information . Why >> would >> I >> need >> anything from the FPGA framework in SPL on Gen5 ? It is not >> needed >> thus >> far. Is it because you shuffled some of the code around or >> what ? >> > Because we need to know some status and mode type from FPGA > even we > did > not program FPGA in SPL. But we didn't have this option enabled before and everything worked on gen5, why do we need it now ? >>> Because i already move them into fpga driver, because those >>> functions >>> should be part of fpga driver. So, this moving happen in patch 6. >> I see. Does enabling the FPGA_SPL stuff pull in any of the FPGA >> framework ? Does the size of the Gen5 SPL change before and after >> this >> patchset ? If you did not check, please do. > Yeah, i confirm FPGA driver is availabled in SPL. A bit change in size, > 1~2K more. I did the test on our devkits also. OK, so that's not acceptable because we're already very close to the size limit of the SPL. -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v8 4/7] arm: socfpga: Enable FPGA driver on SPL
On Sel, 2017-06-06 at 11:50 +0200, Marek Vasut wrote: > On 06/06/2017 11:46 AM, Chee, Tien Fong wrote: > > > > On Sel, 2017-06-06 at 11:41 +0200, Marek Vasut wrote: > > > > > > On 06/06/2017 11:36 AM, Chee, Tien Fong wrote: > > > > > > > > > > > > On Sel, 2017-06-06 at 10:35 +0200, Marek Vasut wrote: > > > > > > > > > > > > > > > On 06/06/2017 10:19 AM, Chee, Tien Fong wrote: > > > > > > > > > > > > > > > > > > > > > > > > On Sel, 2017-06-06 at 10:03 +0200, Marek Vasut wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > On 06/06/2017 08:35 AM, tien.fong.c...@intel.com wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > From: Tien Fong Chee > > > > > > > > > > > > > > > > This patch is for enabling FPGA driver support on SPL > > > > > > > Why would we want that on Gen5 ? I believe this is only > > > > > > > needed on > > > > > > > Gen10. > > > > > > > > > > > > > I already moved the fpga_manager driver into drivers/fpga/ > > > > > > on > > > > > > patch > > > > > > 6, > > > > > > and fpga_manager drivers are required on SPL. Actually > > > > > > fpga_manager > > > > > > driver should be part of the drivers/fpga. > > > > > I think I miss some fundamental piece of information . Why > > > > > would > > > > > I > > > > > need > > > > > anything from the FPGA framework in SPL on Gen5 ? It is not > > > > > needed > > > > > thus > > > > > far. Is it because you shuffled some of the code around or > > > > > what ? > > > > > > > > > Because we need to know some status and mode type from FPGA > > > > even we > > > > did > > > > not program FPGA in SPL. > > > But we didn't have this option enabled before and everything > > > worked > > > on > > > gen5, why do we need it now ? > > > > > Because i already move them into fpga driver, because those > > functions > > should be part of fpga driver. So, this moving happen in patch 6. > I see. Does enabling the FPGA_SPL stuff pull in any of the FPGA > framework ? Does the size of the Gen5 SPL change before and after > this > patchset ? If you did not check, please do. Yeah, i confirm FPGA driver is availabled in SPL. A bit change in size, 1~2K more. I did the test on our devkits also. > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v8 4/7] arm: socfpga: Enable FPGA driver on SPL
On 06/06/2017 11:46 AM, Chee, Tien Fong wrote: > On Sel, 2017-06-06 at 11:41 +0200, Marek Vasut wrote: >> On 06/06/2017 11:36 AM, Chee, Tien Fong wrote: >>> >>> On Sel, 2017-06-06 at 10:35 +0200, Marek Vasut wrote: On 06/06/2017 10:19 AM, Chee, Tien Fong wrote: > > > On Sel, 2017-06-06 at 10:03 +0200, Marek Vasut wrote: >> >> >> On 06/06/2017 08:35 AM, tien.fong.c...@intel.com wrote: >>> >>> >>> >>> From: Tien Fong Chee >>> >>> This patch is for enabling FPGA driver support on SPL >> Why would we want that on Gen5 ? I believe this is only >> needed on >> Gen10. >> > I already moved the fpga_manager driver into drivers/fpga/ on > patch > 6, > and fpga_manager drivers are required on SPL. Actually > fpga_manager > driver should be part of the drivers/fpga. I think I miss some fundamental piece of information . Why would I need anything from the FPGA framework in SPL on Gen5 ? It is not needed thus far. Is it because you shuffled some of the code around or what ? >>> Because we need to know some status and mode type from FPGA even we >>> did >>> not program FPGA in SPL. >> But we didn't have this option enabled before and everything worked >> on >> gen5, why do we need it now ? >> > Because i already move them into fpga driver, because those functions > should be part of fpga driver. So, this moving happen in patch 6. I see. Does enabling the FPGA_SPL stuff pull in any of the FPGA framework ? Does the size of the Gen5 SPL change before and after this patchset ? If you did not check, please do. -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v8 4/7] arm: socfpga: Enable FPGA driver on SPL
On Sel, 2017-06-06 at 11:41 +0200, Marek Vasut wrote: > On 06/06/2017 11:36 AM, Chee, Tien Fong wrote: > > > > On Sel, 2017-06-06 at 10:35 +0200, Marek Vasut wrote: > > > > > > On 06/06/2017 10:19 AM, Chee, Tien Fong wrote: > > > > > > > > > > > > On Sel, 2017-06-06 at 10:03 +0200, Marek Vasut wrote: > > > > > > > > > > > > > > > On 06/06/2017 08:35 AM, tien.fong.c...@intel.com wrote: > > > > > > > > > > > > > > > > > > > > > > > > From: Tien Fong Chee > > > > > > > > > > > > This patch is for enabling FPGA driver support on SPL > > > > > Why would we want that on Gen5 ? I believe this is only > > > > > needed on > > > > > Gen10. > > > > > > > > > I already moved the fpga_manager driver into drivers/fpga/ on > > > > patch > > > > 6, > > > > and fpga_manager drivers are required on SPL. Actually > > > > fpga_manager > > > > driver should be part of the drivers/fpga. > > > I think I miss some fundamental piece of information . Why would > > > I > > > need > > > anything from the FPGA framework in SPL on Gen5 ? It is not > > > needed > > > thus > > > far. Is it because you shuffled some of the code around or what ? > > > > > Because we need to know some status and mode type from FPGA even we > > did > > not program FPGA in SPL. > But we didn't have this option enabled before and everything worked > on > gen5, why do we need it now ? > Because i already move them into fpga driver, because those functions should be part of fpga driver. So, this moving happen in patch 6. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v8 4/7] arm: socfpga: Enable FPGA driver on SPL
On 06/06/2017 11:36 AM, Chee, Tien Fong wrote: > On Sel, 2017-06-06 at 10:35 +0200, Marek Vasut wrote: >> On 06/06/2017 10:19 AM, Chee, Tien Fong wrote: >>> >>> On Sel, 2017-06-06 at 10:03 +0200, Marek Vasut wrote: On 06/06/2017 08:35 AM, tien.fong.c...@intel.com wrote: > > > From: Tien Fong Chee > > This patch is for enabling FPGA driver support on SPL Why would we want that on Gen5 ? I believe this is only needed on Gen10. >>> I already moved the fpga_manager driver into drivers/fpga/ on patch >>> 6, >>> and fpga_manager drivers are required on SPL. Actually fpga_manager >>> driver should be part of the drivers/fpga. >> I think I miss some fundamental piece of information . Why would I >> need >> anything from the FPGA framework in SPL on Gen5 ? It is not needed >> thus >> far. Is it because you shuffled some of the code around or what ? >> > Because we need to know some status and mode type from FPGA even we did > not program FPGA in SPL. But we didn't have this option enabled before and everything worked on gen5, why do we need it now ? -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v8 4/7] arm: socfpga: Enable FPGA driver on SPL
On Sel, 2017-06-06 at 10:35 +0200, Marek Vasut wrote: > On 06/06/2017 10:19 AM, Chee, Tien Fong wrote: > > > > On Sel, 2017-06-06 at 10:03 +0200, Marek Vasut wrote: > > > > > > On 06/06/2017 08:35 AM, tien.fong.c...@intel.com wrote: > > > > > > > > > > > > From: Tien Fong Chee > > > > > > > > This patch is for enabling FPGA driver support on SPL > > > Why would we want that on Gen5 ? I believe this is only needed on > > > Gen10. > > > > > I already moved the fpga_manager driver into drivers/fpga/ on patch > > 6, > > and fpga_manager drivers are required on SPL. Actually fpga_manager > > driver should be part of the drivers/fpga. > I think I miss some fundamental piece of information . Why would I > need > anything from the FPGA framework in SPL on Gen5 ? It is not needed > thus > far. Is it because you shuffled some of the code around or what ? > Because we need to know some status and mode type from FPGA even we did not program FPGA in SPL. > > > > > > > > > > > > > > > > > Signed-off-by: Tien Fong Chee > > > > --- > > > > configs/socfpga_arria5_defconfig | 1 + > > > > configs/socfpga_cyclone5_defconfig | 1 + > > > > configs/socfpga_de0_nano_soc_defconfig | 1 + > > > > configs/socfpga_de10_nano_defconfig| 1 + > > > > configs/socfpga_de1_soc_defconfig | 1 + > > > > configs/socfpga_is1_defconfig | 1 + > > > > configs/socfpga_mcvevk_defconfig | 1 + > > > > configs/socfpga_sockit_defconfig | 1 + > > > > configs/socfpga_socrates_defconfig | 1 + > > > > configs/socfpga_sr1500_defconfig | 1 + > > > > configs/socfpga_vining_fpga_defconfig | 1 + > > > > 11 files changed, 11 insertions(+) > > > > > > > > diff --git a/configs/socfpga_arria5_defconfig > > > > b/configs/socfpga_arria5_defconfig > > > > index 6f2a06f..4b1e252 100644 > > > > --- a/configs/socfpga_arria5_defconfig > > > > +++ b/configs/socfpga_arria5_defconfig > > > > @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y > > > > CONFIG_SPL=y > > > > CONFIG_SPL_SYS_MALLOC_SIMPLE=y > > > > CONFIG_SPL_STACK_R=y > > > > +CONFIG_SPL_FPGA_SUPPORT=y > > > > CONFIG_HUSH_PARSER=y > > > > CONFIG_CMD_BOOTZ=y > > > > # CONFIG_CMD_IMLS is not set > > > > diff --git a/configs/socfpga_cyclone5_defconfig > > > > b/configs/socfpga_cyclone5_defconfig > > > > index 1047657..fe7ac08 100644 > > > > --- a/configs/socfpga_cyclone5_defconfig > > > > +++ b/configs/socfpga_cyclone5_defconfig > > > > @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y > > > > CONFIG_SPL=y > > > > CONFIG_SPL_SYS_MALLOC_SIMPLE=y > > > > CONFIG_SPL_STACK_R=y > > > > +CONFIG_SPL_FPGA_SUPPORT=y > > > > CONFIG_HUSH_PARSER=y > > > > CONFIG_CMD_BOOTZ=y > > > > # CONFIG_CMD_IMLS is not set > > > > diff --git a/configs/socfpga_de0_nano_soc_defconfig > > > > b/configs/socfpga_de0_nano_soc_defconfig > > > > index 72a9e5d..d86a9d6 100644 > > > > --- a/configs/socfpga_de0_nano_soc_defconfig > > > > +++ b/configs/socfpga_de0_nano_soc_defconfig > > > > @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y > > > > CONFIG_SPL=y > > > > CONFIG_SPL_SYS_MALLOC_SIMPLE=y > > > > CONFIG_SPL_STACK_R=y > > > > +CONFIG_SPL_FPGA_SUPPORT=y > > > > CONFIG_HUSH_PARSER=y > > > > CONFIG_CMD_BOOTZ=y > > > > # CONFIG_CMD_IMLS is not set > > > > diff --git a/configs/socfpga_de10_nano_defconfig > > > > b/configs/socfpga_de10_nano_defconfig > > > > index 67864cf..ac8ca70 100644 > > > > --- a/configs/socfpga_de10_nano_defconfig > > > > +++ b/configs/socfpga_de10_nano_defconfig > > > > @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y > > > > CONFIG_SPL=y > > > > CONFIG_SPL_SYS_MALLOC_SIMPLE=y > > > > CONFIG_SPL_STACK_R=y > > > > +CONFIG_SPL_FPGA_SUPPORT=y > > > > CONFIG_HUSH_PARSER=y > > > > CONFIG_CMD_BOOTZ=y > > > > # CONFIG_CMD_IMLS is not set > > > > diff --git a/configs/socfpga_de1_soc_defconfig > > > > b/configs/socfpga_de1_soc_defconfig > > > > index 35c4484..cc0a35d 100644 > > > > --- a/configs/socfpga_de1_soc_defconfig > > > > +++ b/configs/socfpga_de1_soc_defconfig > > > > @@ -16,6 +16,7 @@ CONFIG_SPL=y > > > > # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set > > > > CONFIG_SPL_SYS_MALLOC_SIMPLE=y > > > > CONFIG_SPL_STACK_R=y > > > > +CONFIG_SPL_FPGA_SUPPORT=y > > > > CONFIG_SPL_YMODEM_SUPPORT=y > > > > CONFIG_HUSH_PARSER=y > > > > CONFIG_CMD_BOOTZ=y > > > > diff --git a/configs/socfpga_is1_defconfig > > > > b/configs/socfpga_is1_defconfig > > > > index ae688f8..ccfed7a 100644 > > > > --- a/configs/socfpga_is1_defconfig > > > > +++ b/configs/socfpga_is1_defconfig > > > > @@ -12,6 +12,7 @@ CONFIG_VERSION_VARIABLE=y > > > > # CONFIG_DISPLAY_BOARDINFO is not set > > > > CONFIG_SPL=y > > > > CONFIG_SPL_STACK_R=y > > > > +CONFIG_SPL_FPGA_SUPPORT=y > > > > CONFIG_HUSH_PARSER=y > > > > CONFIG_CMD_BOOTZ=y > > > > # CONFIG_CMD_IMLS is not set > > > > diff --git a/configs/socfpga_mcvevk_defconfig > > > > b/configs/socfpga_mcvevk_defconfig > > > > index c5e3b7b..9bcb47d 100644 > > > > --- a/configs/socfpga_mcvevk_defconfig > > > > +++ b/configs/socfpga_mcvevk_defcon
Re: [U-Boot] [PATCH v8 4/7] arm: socfpga: Enable FPGA driver on SPL
On 06/06/2017 10:19 AM, Chee, Tien Fong wrote: > On Sel, 2017-06-06 at 10:03 +0200, Marek Vasut wrote: >> On 06/06/2017 08:35 AM, tien.fong.c...@intel.com wrote: >>> >>> From: Tien Fong Chee >>> >>> This patch is for enabling FPGA driver support on SPL >> Why would we want that on Gen5 ? I believe this is only needed on >> Gen10. >> > I already moved the fpga_manager driver into drivers/fpga/ on patch 6, > and fpga_manager drivers are required on SPL. Actually fpga_manager > driver should be part of the drivers/fpga. I think I miss some fundamental piece of information . Why would I need anything from the FPGA framework in SPL on Gen5 ? It is not needed thus far. Is it because you shuffled some of the code around or what ? >>> >>> Signed-off-by: Tien Fong Chee >>> --- >>> configs/socfpga_arria5_defconfig | 1 + >>> configs/socfpga_cyclone5_defconfig | 1 + >>> configs/socfpga_de0_nano_soc_defconfig | 1 + >>> configs/socfpga_de10_nano_defconfig| 1 + >>> configs/socfpga_de1_soc_defconfig | 1 + >>> configs/socfpga_is1_defconfig | 1 + >>> configs/socfpga_mcvevk_defconfig | 1 + >>> configs/socfpga_sockit_defconfig | 1 + >>> configs/socfpga_socrates_defconfig | 1 + >>> configs/socfpga_sr1500_defconfig | 1 + >>> configs/socfpga_vining_fpga_defconfig | 1 + >>> 11 files changed, 11 insertions(+) >>> >>> diff --git a/configs/socfpga_arria5_defconfig >>> b/configs/socfpga_arria5_defconfig >>> index 6f2a06f..4b1e252 100644 >>> --- a/configs/socfpga_arria5_defconfig >>> +++ b/configs/socfpga_arria5_defconfig >>> @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y >>> CONFIG_SPL=y >>> CONFIG_SPL_SYS_MALLOC_SIMPLE=y >>> CONFIG_SPL_STACK_R=y >>> +CONFIG_SPL_FPGA_SUPPORT=y >>> CONFIG_HUSH_PARSER=y >>> CONFIG_CMD_BOOTZ=y >>> # CONFIG_CMD_IMLS is not set >>> diff --git a/configs/socfpga_cyclone5_defconfig >>> b/configs/socfpga_cyclone5_defconfig >>> index 1047657..fe7ac08 100644 >>> --- a/configs/socfpga_cyclone5_defconfig >>> +++ b/configs/socfpga_cyclone5_defconfig >>> @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y >>> CONFIG_SPL=y >>> CONFIG_SPL_SYS_MALLOC_SIMPLE=y >>> CONFIG_SPL_STACK_R=y >>> +CONFIG_SPL_FPGA_SUPPORT=y >>> CONFIG_HUSH_PARSER=y >>> CONFIG_CMD_BOOTZ=y >>> # CONFIG_CMD_IMLS is not set >>> diff --git a/configs/socfpga_de0_nano_soc_defconfig >>> b/configs/socfpga_de0_nano_soc_defconfig >>> index 72a9e5d..d86a9d6 100644 >>> --- a/configs/socfpga_de0_nano_soc_defconfig >>> +++ b/configs/socfpga_de0_nano_soc_defconfig >>> @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y >>> CONFIG_SPL=y >>> CONFIG_SPL_SYS_MALLOC_SIMPLE=y >>> CONFIG_SPL_STACK_R=y >>> +CONFIG_SPL_FPGA_SUPPORT=y >>> CONFIG_HUSH_PARSER=y >>> CONFIG_CMD_BOOTZ=y >>> # CONFIG_CMD_IMLS is not set >>> diff --git a/configs/socfpga_de10_nano_defconfig >>> b/configs/socfpga_de10_nano_defconfig >>> index 67864cf..ac8ca70 100644 >>> --- a/configs/socfpga_de10_nano_defconfig >>> +++ b/configs/socfpga_de10_nano_defconfig >>> @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y >>> CONFIG_SPL=y >>> CONFIG_SPL_SYS_MALLOC_SIMPLE=y >>> CONFIG_SPL_STACK_R=y >>> +CONFIG_SPL_FPGA_SUPPORT=y >>> CONFIG_HUSH_PARSER=y >>> CONFIG_CMD_BOOTZ=y >>> # CONFIG_CMD_IMLS is not set >>> diff --git a/configs/socfpga_de1_soc_defconfig >>> b/configs/socfpga_de1_soc_defconfig >>> index 35c4484..cc0a35d 100644 >>> --- a/configs/socfpga_de1_soc_defconfig >>> +++ b/configs/socfpga_de1_soc_defconfig >>> @@ -16,6 +16,7 @@ CONFIG_SPL=y >>> # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set >>> CONFIG_SPL_SYS_MALLOC_SIMPLE=y >>> CONFIG_SPL_STACK_R=y >>> +CONFIG_SPL_FPGA_SUPPORT=y >>> CONFIG_SPL_YMODEM_SUPPORT=y >>> CONFIG_HUSH_PARSER=y >>> CONFIG_CMD_BOOTZ=y >>> diff --git a/configs/socfpga_is1_defconfig >>> b/configs/socfpga_is1_defconfig >>> index ae688f8..ccfed7a 100644 >>> --- a/configs/socfpga_is1_defconfig >>> +++ b/configs/socfpga_is1_defconfig >>> @@ -12,6 +12,7 @@ CONFIG_VERSION_VARIABLE=y >>> # CONFIG_DISPLAY_BOARDINFO is not set >>> CONFIG_SPL=y >>> CONFIG_SPL_STACK_R=y >>> +CONFIG_SPL_FPGA_SUPPORT=y >>> CONFIG_HUSH_PARSER=y >>> CONFIG_CMD_BOOTZ=y >>> # CONFIG_CMD_IMLS is not set >>> diff --git a/configs/socfpga_mcvevk_defconfig >>> b/configs/socfpga_mcvevk_defconfig >>> index c5e3b7b..9bcb47d 100644 >>> --- a/configs/socfpga_mcvevk_defconfig >>> +++ b/configs/socfpga_mcvevk_defconfig >>> @@ -13,6 +13,7 @@ CONFIG_VERSION_VARIABLE=y >>> CONFIG_SPL=y >>> CONFIG_SPL_SYS_MALLOC_SIMPLE=y >>> CONFIG_SPL_STACK_R=y >>> +CONFIG_SPL_FPGA_SUPPORT=y >>> CONFIG_HUSH_PARSER=y >>> CONFIG_CMD_BOOTZ=y >>> # CONFIG_CMD_IMLS is not set >>> diff --git a/configs/socfpga_sockit_defconfig >>> b/configs/socfpga_sockit_defconfig >>> index 3ff7bb7..ef54e1f 100644 >>> --- a/configs/socfpga_sockit_defconfig >>> +++ b/configs/socfpga_sockit_defconfig >>> @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y >>> CONFIG_SPL=y >>> CONFIG_SPL_SYS_MALLOC_SIMPLE=y >>> CONFIG_SPL_STACK_R=y >>> +CONFIG_SPL_FPGA_SUPPORT=y >>> CONFIG_HUSH_PARSER=y >>> C
Re: [U-Boot] [PATCH v8 4/7] arm: socfpga: Enable FPGA driver on SPL
On Sel, 2017-06-06 at 10:03 +0200, Marek Vasut wrote: > On 06/06/2017 08:35 AM, tien.fong.c...@intel.com wrote: > > > > From: Tien Fong Chee > > > > This patch is for enabling FPGA driver support on SPL > Why would we want that on Gen5 ? I believe this is only needed on > Gen10. > I already moved the fpga_manager driver into drivers/fpga/ on patch 6, and fpga_manager drivers are required on SPL. Actually fpga_manager driver should be part of the drivers/fpga. > > > > Signed-off-by: Tien Fong Chee > > --- > > configs/socfpga_arria5_defconfig | 1 + > > configs/socfpga_cyclone5_defconfig | 1 + > > configs/socfpga_de0_nano_soc_defconfig | 1 + > > configs/socfpga_de10_nano_defconfig| 1 + > > configs/socfpga_de1_soc_defconfig | 1 + > > configs/socfpga_is1_defconfig | 1 + > > configs/socfpga_mcvevk_defconfig | 1 + > > configs/socfpga_sockit_defconfig | 1 + > > configs/socfpga_socrates_defconfig | 1 + > > configs/socfpga_sr1500_defconfig | 1 + > > configs/socfpga_vining_fpga_defconfig | 1 + > > 11 files changed, 11 insertions(+) > > > > diff --git a/configs/socfpga_arria5_defconfig > > b/configs/socfpga_arria5_defconfig > > index 6f2a06f..4b1e252 100644 > > --- a/configs/socfpga_arria5_defconfig > > +++ b/configs/socfpga_arria5_defconfig > > @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y > > CONFIG_SPL=y > > CONFIG_SPL_SYS_MALLOC_SIMPLE=y > > CONFIG_SPL_STACK_R=y > > +CONFIG_SPL_FPGA_SUPPORT=y > > CONFIG_HUSH_PARSER=y > > CONFIG_CMD_BOOTZ=y > > # CONFIG_CMD_IMLS is not set > > diff --git a/configs/socfpga_cyclone5_defconfig > > b/configs/socfpga_cyclone5_defconfig > > index 1047657..fe7ac08 100644 > > --- a/configs/socfpga_cyclone5_defconfig > > +++ b/configs/socfpga_cyclone5_defconfig > > @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y > > CONFIG_SPL=y > > CONFIG_SPL_SYS_MALLOC_SIMPLE=y > > CONFIG_SPL_STACK_R=y > > +CONFIG_SPL_FPGA_SUPPORT=y > > CONFIG_HUSH_PARSER=y > > CONFIG_CMD_BOOTZ=y > > # CONFIG_CMD_IMLS is not set > > diff --git a/configs/socfpga_de0_nano_soc_defconfig > > b/configs/socfpga_de0_nano_soc_defconfig > > index 72a9e5d..d86a9d6 100644 > > --- a/configs/socfpga_de0_nano_soc_defconfig > > +++ b/configs/socfpga_de0_nano_soc_defconfig > > @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y > > CONFIG_SPL=y > > CONFIG_SPL_SYS_MALLOC_SIMPLE=y > > CONFIG_SPL_STACK_R=y > > +CONFIG_SPL_FPGA_SUPPORT=y > > CONFIG_HUSH_PARSER=y > > CONFIG_CMD_BOOTZ=y > > # CONFIG_CMD_IMLS is not set > > diff --git a/configs/socfpga_de10_nano_defconfig > > b/configs/socfpga_de10_nano_defconfig > > index 67864cf..ac8ca70 100644 > > --- a/configs/socfpga_de10_nano_defconfig > > +++ b/configs/socfpga_de10_nano_defconfig > > @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y > > CONFIG_SPL=y > > CONFIG_SPL_SYS_MALLOC_SIMPLE=y > > CONFIG_SPL_STACK_R=y > > +CONFIG_SPL_FPGA_SUPPORT=y > > CONFIG_HUSH_PARSER=y > > CONFIG_CMD_BOOTZ=y > > # CONFIG_CMD_IMLS is not set > > diff --git a/configs/socfpga_de1_soc_defconfig > > b/configs/socfpga_de1_soc_defconfig > > index 35c4484..cc0a35d 100644 > > --- a/configs/socfpga_de1_soc_defconfig > > +++ b/configs/socfpga_de1_soc_defconfig > > @@ -16,6 +16,7 @@ CONFIG_SPL=y > > # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set > > CONFIG_SPL_SYS_MALLOC_SIMPLE=y > > CONFIG_SPL_STACK_R=y > > +CONFIG_SPL_FPGA_SUPPORT=y > > CONFIG_SPL_YMODEM_SUPPORT=y > > CONFIG_HUSH_PARSER=y > > CONFIG_CMD_BOOTZ=y > > diff --git a/configs/socfpga_is1_defconfig > > b/configs/socfpga_is1_defconfig > > index ae688f8..ccfed7a 100644 > > --- a/configs/socfpga_is1_defconfig > > +++ b/configs/socfpga_is1_defconfig > > @@ -12,6 +12,7 @@ CONFIG_VERSION_VARIABLE=y > > # CONFIG_DISPLAY_BOARDINFO is not set > > CONFIG_SPL=y > > CONFIG_SPL_STACK_R=y > > +CONFIG_SPL_FPGA_SUPPORT=y > > CONFIG_HUSH_PARSER=y > > CONFIG_CMD_BOOTZ=y > > # CONFIG_CMD_IMLS is not set > > diff --git a/configs/socfpga_mcvevk_defconfig > > b/configs/socfpga_mcvevk_defconfig > > index c5e3b7b..9bcb47d 100644 > > --- a/configs/socfpga_mcvevk_defconfig > > +++ b/configs/socfpga_mcvevk_defconfig > > @@ -13,6 +13,7 @@ CONFIG_VERSION_VARIABLE=y > > CONFIG_SPL=y > > CONFIG_SPL_SYS_MALLOC_SIMPLE=y > > CONFIG_SPL_STACK_R=y > > +CONFIG_SPL_FPGA_SUPPORT=y > > CONFIG_HUSH_PARSER=y > > CONFIG_CMD_BOOTZ=y > > # CONFIG_CMD_IMLS is not set > > diff --git a/configs/socfpga_sockit_defconfig > > b/configs/socfpga_sockit_defconfig > > index 3ff7bb7..ef54e1f 100644 > > --- a/configs/socfpga_sockit_defconfig > > +++ b/configs/socfpga_sockit_defconfig > > @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y > > CONFIG_SPL=y > > CONFIG_SPL_SYS_MALLOC_SIMPLE=y > > CONFIG_SPL_STACK_R=y > > +CONFIG_SPL_FPGA_SUPPORT=y > > CONFIG_HUSH_PARSER=y > > CONFIG_CMD_BOOTZ=y > > # CONFIG_CMD_IMLS is not set > > diff --git a/configs/socfpga_socrates_defconfig > > b/configs/socfpga_socrates_defconfig > > index fb9c13f..78daf26 100644 > > --- a/configs/socfpga_socrates_defconfig > > +++ b/configs/socfpga_socrates_defconf
Re: [U-Boot] [PATCH v8 4/7] arm: socfpga: Enable FPGA driver on SPL
On 06/06/2017 08:35 AM, tien.fong.c...@intel.com wrote: > From: Tien Fong Chee > > This patch is for enabling FPGA driver support on SPL Why would we want that on Gen5 ? I believe this is only needed on Gen10. > Signed-off-by: Tien Fong Chee > --- > configs/socfpga_arria5_defconfig | 1 + > configs/socfpga_cyclone5_defconfig | 1 + > configs/socfpga_de0_nano_soc_defconfig | 1 + > configs/socfpga_de10_nano_defconfig| 1 + > configs/socfpga_de1_soc_defconfig | 1 + > configs/socfpga_is1_defconfig | 1 + > configs/socfpga_mcvevk_defconfig | 1 + > configs/socfpga_sockit_defconfig | 1 + > configs/socfpga_socrates_defconfig | 1 + > configs/socfpga_sr1500_defconfig | 1 + > configs/socfpga_vining_fpga_defconfig | 1 + > 11 files changed, 11 insertions(+) > > diff --git a/configs/socfpga_arria5_defconfig > b/configs/socfpga_arria5_defconfig > index 6f2a06f..4b1e252 100644 > --- a/configs/socfpga_arria5_defconfig > +++ b/configs/socfpga_arria5_defconfig > @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y > CONFIG_SPL=y > CONFIG_SPL_SYS_MALLOC_SIMPLE=y > CONFIG_SPL_STACK_R=y > +CONFIG_SPL_FPGA_SUPPORT=y > CONFIG_HUSH_PARSER=y > CONFIG_CMD_BOOTZ=y > # CONFIG_CMD_IMLS is not set > diff --git a/configs/socfpga_cyclone5_defconfig > b/configs/socfpga_cyclone5_defconfig > index 1047657..fe7ac08 100644 > --- a/configs/socfpga_cyclone5_defconfig > +++ b/configs/socfpga_cyclone5_defconfig > @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y > CONFIG_SPL=y > CONFIG_SPL_SYS_MALLOC_SIMPLE=y > CONFIG_SPL_STACK_R=y > +CONFIG_SPL_FPGA_SUPPORT=y > CONFIG_HUSH_PARSER=y > CONFIG_CMD_BOOTZ=y > # CONFIG_CMD_IMLS is not set > diff --git a/configs/socfpga_de0_nano_soc_defconfig > b/configs/socfpga_de0_nano_soc_defconfig > index 72a9e5d..d86a9d6 100644 > --- a/configs/socfpga_de0_nano_soc_defconfig > +++ b/configs/socfpga_de0_nano_soc_defconfig > @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y > CONFIG_SPL=y > CONFIG_SPL_SYS_MALLOC_SIMPLE=y > CONFIG_SPL_STACK_R=y > +CONFIG_SPL_FPGA_SUPPORT=y > CONFIG_HUSH_PARSER=y > CONFIG_CMD_BOOTZ=y > # CONFIG_CMD_IMLS is not set > diff --git a/configs/socfpga_de10_nano_defconfig > b/configs/socfpga_de10_nano_defconfig > index 67864cf..ac8ca70 100644 > --- a/configs/socfpga_de10_nano_defconfig > +++ b/configs/socfpga_de10_nano_defconfig > @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y > CONFIG_SPL=y > CONFIG_SPL_SYS_MALLOC_SIMPLE=y > CONFIG_SPL_STACK_R=y > +CONFIG_SPL_FPGA_SUPPORT=y > CONFIG_HUSH_PARSER=y > CONFIG_CMD_BOOTZ=y > # CONFIG_CMD_IMLS is not set > diff --git a/configs/socfpga_de1_soc_defconfig > b/configs/socfpga_de1_soc_defconfig > index 35c4484..cc0a35d 100644 > --- a/configs/socfpga_de1_soc_defconfig > +++ b/configs/socfpga_de1_soc_defconfig > @@ -16,6 +16,7 @@ CONFIG_SPL=y > # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set > CONFIG_SPL_SYS_MALLOC_SIMPLE=y > CONFIG_SPL_STACK_R=y > +CONFIG_SPL_FPGA_SUPPORT=y > CONFIG_SPL_YMODEM_SUPPORT=y > CONFIG_HUSH_PARSER=y > CONFIG_CMD_BOOTZ=y > diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig > index ae688f8..ccfed7a 100644 > --- a/configs/socfpga_is1_defconfig > +++ b/configs/socfpga_is1_defconfig > @@ -12,6 +12,7 @@ CONFIG_VERSION_VARIABLE=y > # CONFIG_DISPLAY_BOARDINFO is not set > CONFIG_SPL=y > CONFIG_SPL_STACK_R=y > +CONFIG_SPL_FPGA_SUPPORT=y > CONFIG_HUSH_PARSER=y > CONFIG_CMD_BOOTZ=y > # CONFIG_CMD_IMLS is not set > diff --git a/configs/socfpga_mcvevk_defconfig > b/configs/socfpga_mcvevk_defconfig > index c5e3b7b..9bcb47d 100644 > --- a/configs/socfpga_mcvevk_defconfig > +++ b/configs/socfpga_mcvevk_defconfig > @@ -13,6 +13,7 @@ CONFIG_VERSION_VARIABLE=y > CONFIG_SPL=y > CONFIG_SPL_SYS_MALLOC_SIMPLE=y > CONFIG_SPL_STACK_R=y > +CONFIG_SPL_FPGA_SUPPORT=y > CONFIG_HUSH_PARSER=y > CONFIG_CMD_BOOTZ=y > # CONFIG_CMD_IMLS is not set > diff --git a/configs/socfpga_sockit_defconfig > b/configs/socfpga_sockit_defconfig > index 3ff7bb7..ef54e1f 100644 > --- a/configs/socfpga_sockit_defconfig > +++ b/configs/socfpga_sockit_defconfig > @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y > CONFIG_SPL=y > CONFIG_SPL_SYS_MALLOC_SIMPLE=y > CONFIG_SPL_STACK_R=y > +CONFIG_SPL_FPGA_SUPPORT=y > CONFIG_HUSH_PARSER=y > CONFIG_CMD_BOOTZ=y > # CONFIG_CMD_IMLS is not set > diff --git a/configs/socfpga_socrates_defconfig > b/configs/socfpga_socrates_defconfig > index fb9c13f..78daf26 100644 > --- a/configs/socfpga_socrates_defconfig > +++ b/configs/socfpga_socrates_defconfig > @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y > CONFIG_SPL=y > CONFIG_SPL_SYS_MALLOC_SIMPLE=y > CONFIG_SPL_STACK_R=y > +CONFIG_SPL_FPGA_SUPPORT=y > CONFIG_HUSH_PARSER=y > CONFIG_CMD_BOOTZ=y > # CONFIG_CMD_IMLS is not set > diff --git a/configs/socfpga_sr1500_defconfig > b/configs/socfpga_sr1500_defconfig > index d90d6a1..4a12379 100644 > --- a/configs/socfpga_sr1500_defconfig > +++ b/configs/socfpga_sr1500_defconfig > @@ -16,6 +16,7 @@ CONFIG_BOARD_EARLY_INIT_F=y > CONFIG_SPL=y > CONF
[U-Boot] [PATCH v8 4/7] arm: socfpga: Enable FPGA driver on SPL
From: Tien Fong Chee This patch is for enabling FPGA driver support on SPL Signed-off-by: Tien Fong Chee --- configs/socfpga_arria5_defconfig | 1 + configs/socfpga_cyclone5_defconfig | 1 + configs/socfpga_de0_nano_soc_defconfig | 1 + configs/socfpga_de10_nano_defconfig| 1 + configs/socfpga_de1_soc_defconfig | 1 + configs/socfpga_is1_defconfig | 1 + configs/socfpga_mcvevk_defconfig | 1 + configs/socfpga_sockit_defconfig | 1 + configs/socfpga_socrates_defconfig | 1 + configs/socfpga_sr1500_defconfig | 1 + configs/socfpga_vining_fpga_defconfig | 1 + 11 files changed, 11 insertions(+) diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index 6f2a06f..4b1e252 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SPL_FPGA_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index 1047657..fe7ac08 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SPL_FPGA_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig index 72a9e5d..d86a9d6 100644 --- a/configs/socfpga_de0_nano_soc_defconfig +++ b/configs/socfpga_de0_nano_soc_defconfig @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SPL_FPGA_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig index 67864cf..ac8ca70 100644 --- a/configs/socfpga_de10_nano_defconfig +++ b/configs/socfpga_de10_nano_defconfig @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SPL_FPGA_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set diff --git a/configs/socfpga_de1_soc_defconfig b/configs/socfpga_de1_soc_defconfig index 35c4484..cc0a35d 100644 --- a/configs/socfpga_de1_soc_defconfig +++ b/configs/socfpga_de1_soc_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SPL_FPGA_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig index ae688f8..ccfed7a 100644 --- a/configs/socfpga_is1_defconfig +++ b/configs/socfpga_is1_defconfig @@ -12,6 +12,7 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_SPL_STACK_R=y +CONFIG_SPL_FPGA_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig index c5e3b7b..9bcb47d 100644 --- a/configs/socfpga_mcvevk_defconfig +++ b/configs/socfpga_mcvevk_defconfig @@ -13,6 +13,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SPL_FPGA_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index 3ff7bb7..ef54e1f 100644 --- a/configs/socfpga_sockit_defconfig +++ b/configs/socfpga_sockit_defconfig @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SPL_FPGA_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index fb9c13f..78daf26 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SPL_FPGA_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig index d90d6a1..4a12379 100644 --- a/configs/socfpga_sr1500_defconfig +++ b/configs/socfpga_sr1500_defconfig @@ -16,6 +16,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SPL_FPGA_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index c3fbe40..3fc37dc 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y C
