Re: [U-Boot] [PATCHv2 09/15] pci: layerscape: add pci driver based on DM

2016-11-14 Thread Z.Q. Hou 
Hi Simon,

> -Original Message-
> From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
> Sent: 2016年11月12日 0:18
> To: Z.Q. Hou 
> Cc: U-Boot Mailing List ; Albert ARIBAUD
> ; Prabhakar Kushwaha
> ; Huan Wang-B18965
> ; Sumit Garg ; Ruchika
> Gupta ; Saksham Jain
> ; york sun ; M.H. Lian
> ; Bin Meng ; Mingkai Hu
> 
> Subject: Re: [PATCHv2 09/15] pci: layerscape: add pci driver based on DM
> 
> On 10 November 2016 at 03:58, Zhiqiang Hou 
> wrote:
> > From: Minghuan Lian 
> >
> > There are more than five kinds of Layerscape SoCs. unfortunately, PCIe
> > controller of each SoC is a little bit different. In order to avoid
> > too many macro definitions, the patch addes a new implementation of
> > PCIe driver based on DM. PCIe dts node is used to describe the
> > difference.
> >
> > Signed-off-by: Minghuan Lian 
> > Signed-off-by: Hou Zhiqiang 
> > ---
> > V2:
> >  - Rebased the driver against the latest code.
> >
> >  drivers/pci/Kconfig   |   8 +
> >  drivers/pci/pcie_layerscape.c | 761
> > ++
> >  2 files changed, 769 insertions(+)
> 
> Reviewed-by: Simon Glass 
> 
> So far as I understand it
> 

Thanks for your review!

Regards,
Zhiqiang
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Re: [U-Boot] [PATCHv2 09/15] pci: layerscape: add pci driver based on DM

2016-11-11 Thread Simon Glass 
On 10 November 2016 at 03:58, Zhiqiang Hou  wrote:
> From: Minghuan Lian 
>
> There are more than five kinds of Layerscape SoCs. unfortunately,
> PCIe controller of each SoC is a little bit different. In order
> to avoid too many macro definitions, the patch addes a new
> implementation of PCIe driver based on DM. PCIe dts node is
> used to describe the difference.
>
> Signed-off-by: Minghuan Lian 
> Signed-off-by: Hou Zhiqiang 
> ---
> V2:
>  - Rebased the driver against the latest code.
>
>  drivers/pci/Kconfig   |   8 +
>  drivers/pci/pcie_layerscape.c | 761 
> ++
>  2 files changed, 769 insertions(+)

Reviewed-by: Simon Glass 

So far as I understand it

- Simon
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[U-Boot] [PATCHv2 09/15] pci: layerscape: add pci driver based on DM

2016-11-10 Thread Zhiqiang Hou 
From: Minghuan Lian 

There are more than five kinds of Layerscape SoCs. unfortunately,
PCIe controller of each SoC is a little bit different. In order
to avoid too many macro definitions, the patch addes a new
implementation of PCIe driver based on DM. PCIe dts node is
used to describe the difference.

Signed-off-by: Minghuan Lian 
Signed-off-by: Hou Zhiqiang 
---
V2:
 - Rebased the driver against the latest code. 

 drivers/pci/Kconfig   |   8 +
 drivers/pci/pcie_layerscape.c | 761 ++
 2 files changed, 769 insertions(+)

diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index b8376b4..07d21ea 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -61,4 +61,12 @@ config PCI_XILINX
  Enable support for the Xilinx AXI bridge for PCI express, an IP block
  which can be used on some generations of Xilinx FPGAs.
 
+config PCIE_LAYERSCAPE
+   bool "Layerscape PCIe support"
+   depends on DM_PCI
+   help
+ Support Layerscape PCIe. The Layerscape SoC may have one or several
+ PCIe controllers. The PCIe may works in RC or EP mode according to
+ RCW setting.
+
 endif
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 2e6b986..f107d1c 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -11,11 +11,14 @@
 #include 
 #include 
 #include 
+#include 
 #ifndef CONFIG_LS102XA
 #include 
 #include 
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifndef CONFIG_SYS_PCI_MEMORY_BUS
 #define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
 #endif
@@ -40,6 +43,7 @@
 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
 #define PCIE_ATU_REGION_INDEX2 (0x2 << 0)
 #define PCIE_ATU_REGION_INDEX3 (0x3 << 0)
+#define PCIE_ATU_REGION_NUM6
 #define PCIE_ATU_CR1   0x904
 #define PCIE_ATU_TYPE_MEM  (0x0 << 0)
 #define PCIE_ATU_TYPE_IO   (0x2 << 0)
@@ -58,6 +62,9 @@
 #define PCIE_ATU_FUNC(x)   (((x) & 0x7) << 16)
 #define PCIE_ATU_UPPER_TARGET  0x91C
 
+/* DBI registers */
+#define PCIE_SRIOV 0x178
+#define PCIE_STRFMR1   0x71c /* Symbol Timer & Filter Mask Register1 */
 #define PCIE_DBI_RO_WR_EN  0x8bc
 
 #define PCIE_LINK_CAP  0x7c
@@ -88,6 +95,8 @@
 #define PCIE_BAR2_SIZE (4 * 1024) /* 4K */
 #define PCIE_BAR4_SIZE (1 * 1024 * 1024) /* 1M */
 
+#ifndef CONFIG_DM_PCI
+
 struct ls_pcie {
int idx;
void __iomem *dbi;
@@ -814,3 +823,755 @@ void ft_pci_setup(void *blob, bd_t *bd)
 {
 }
 #endif
+
+#else
+
+/* LUT registers */
+#define PCIE_LUT_UDR(n)(0x800 + (n) * 8)
+#define PCIE_LUT_LDR(n)(0x804 + (n) * 8)
+#define PCIE_LUT_ENABLE(1 << 31)
+#define PCIE_LUT_ENTRY_COUNT   32
+
+/* PF Controll registers */
+#define PCIE_PF_VF_CTRL0x7F8
+#define PCIE_PF_DBG0x7FC
+
+#define PCIE_SRDS_PRTCL(idx)   (PCIE1 + (idx))
+#define PCIE_SYS_BASE_ADDR 0x340
+#define PCIE_CCSR_SIZE 0x010
+
+/* CS2 */
+#define PCIE_CS2_OFFSET0x1000 /* For PCIe without SR-IOV */
+
+#ifdef CONFIG_LS102XA
+/* LS1021a PCIE space */
+#define LS1021_PCIE_SPACE_OFFSET   0x40ULL
+#define LS1021_PCIE_SPACE_SIZE 0x08ULL
+
+/* LS1021a PEX1/2 Misc Ports Status Register */
+#define LS1021_PEXMSCPORTSR(pex_idx)   (0x94 + (pex_idx) * 4)
+#define LS1021_LTSSM_STATE_SHIFT   20
+#endif
+
+struct ls_pcie {
+   int idx;
+   struct list_head list;
+   struct udevice *bus;
+   struct fdt_resource dbi_res;
+   struct fdt_resource lut_res;
+   struct fdt_resource ctrl_res;
+   struct fdt_resource cfg_res;
+   void __iomem *dbi;
+   void __iomem *lut;
+   void __iomem *ctrl;
+   void __iomem *cfg0;
+   void __iomem *cfg1;
+   bool big_endian;
+   bool enabled;
+   int next_lut_index;
+   struct pci_controller hose;
+};
+
+static LIST_HEAD(ls_pcie_list);
+
+static unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset)
+{
+   return in_le32(pcie->dbi + offset);
+}
+
+static void dbi_writel(struct ls_pcie *pcie, unsigned int value,
+  unsigned int offset)
+{
+   out_le32(pcie->dbi + offset, value);
+}
+
+#ifdef CONFIG_FSL_LSCH3
+static void lut_writel(struct ls_pcie *pcie, unsigned int value,
+  unsigned int offset)
+{
+   if (pcie->big_endian)
+   out_be32(pcie->lut + offset, value);
+   else
+   out_le32(pcie->lut + offset, value);
+}
+#endif
+
+static unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset)
+{
+   if (pcie->big_endian)
+   return in_be32(pcie->ctrl + offset);
+   else
+   return in_le32(pcie->ctrl + offset);
+}
+
+static void ctrl_writel(struct ls_pcie *pcie, unsigned int