Re: [U-Boot] [Patch V6 01/18] armv7/ls1021a: move ns_access to common file

[Hou Zhiqiang]

> -Original Message-
> From: Gong Qianyu [mailto:b52...@rhuath.am.freescale.net]
> Sent: 2015年10月19日 19:59
> To: u-boot@lists.denx.de
> Cc: Hu Mingkai-B21284; Sun York-R58495; Hou Zhiqiang-B48286; Xie Shaohui-
> B21989; Song Wenbin-B53747; Wood Scott-B07421; Kushwaha Prabhakar-B32579;
> Wang Huan-B18965; Gong Qianyu-B52263
> Subject: [Patch V6 01/18] armv7/ls1021a: move ns_access to common file
> 
> From: Mingkai Hu 
> 
> Config Security Level Register is different between different SoCs, so
> put the CSL register definition into the arch specific directory.
> 
> Signed-off-by: Mingkai Hu 
> Signed-off-by: Gong Qianyu 

Qianyu, you lost my Signed-off.

Thanks,
Zhqiang
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Re: [U-Boot] [Patch V6 01/18] armv7/ls1021a: move ns_access to common file

[York Sun]

On 10/19/2015 04:58 AM, Gong Qianyu wrote:
> From: Mingkai Hu 
> 
> Config Security Level Register is different between different SoCs,
> so put the CSL register definition into the arch specific directory.
> 
> Signed-off-by: Mingkai Hu 
> Signed-off-by: Gong Qianyu 
> ---
> V6:
>  - No change.
> V5:
>  - No change.
> V4:
>  - No change.
> V3:
>  - No change.
> V2:
>  - Create include/fsl_csu.h instead of board/freescale/common/ns_access.h
>  
>  arch/arm/include/asm/arch-ls102xa/ns_access.h | 103 
> --
>  board/freescale/common/Makefile   |   2 +-
>  board/freescale/common/ns_access.c|   8 +-
>  board/freescale/ls1021aqds/ls1021aqds.c   | 101 ++---
>  board/freescale/ls1021atwr/ls1021atwr.c   |  92 +--
>  include/configs/ls1021aqds.h  |   2 +-
>  include/configs/ls1021atwr.h  |   2 +-
>  include/fsl_csu.h |  34 +
>  8 files changed, 136 insertions(+), 208 deletions(-)
> 


> diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
> index 87d0578..51d2814 100644
> --- a/board/freescale/common/Makefile
> +++ b/board/freescale/common/Makefile
> @@ -71,7 +71,7 @@ obj-$(CONFIG_P4080DS)   += p_corenet/
>  obj-$(CONFIG_P5020DS)+= p_corenet/
>  obj-$(CONFIG_P5040DS)+= p_corenet/
>  
> -obj-$(CONFIG_LS102XA_NS_ACCESS)  += ns_access.o
> +obj-$(CONFIG_LAYERSCAPE_NS_ACCESS)   += ns_access.o

Looks like you missed two #ifdef CONFIG_LS102XA_NS_ACCESS in
board/freescale/ls1021atwr/ls1021atwr.c.

York
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[U-Boot] [Patch V6 01/18] armv7/ls1021a: move ns_access to common file

[Gong Qianyu]

From: Mingkai Hu 

Config Security Level Register is different between different SoCs,
so put the CSL register definition into the arch specific directory.

Signed-off-by: Mingkai Hu 
Signed-off-by: Gong Qianyu 
---
V6:
 - No change.
V5:
 - No change.
V4:
 - No change.
V3:
 - No change.
V2:
 - Create include/fsl_csu.h instead of board/freescale/common/ns_access.h
 
 arch/arm/include/asm/arch-ls102xa/ns_access.h | 103 --
 board/freescale/common/Makefile   |   2 +-
 board/freescale/common/ns_access.c|   8 +-
 board/freescale/ls1021aqds/ls1021aqds.c   | 101 ++---
 board/freescale/ls1021atwr/ls1021atwr.c   |  92 +--
 include/configs/ls1021aqds.h  |   2 +-
 include/configs/ls1021atwr.h  |   2 +-
 include/fsl_csu.h |  34 +
 8 files changed, 136 insertions(+), 208 deletions(-)

diff --git a/arch/arm/include/asm/arch-ls102xa/ns_access.h 
b/arch/arm/include/asm/arch-ls102xa/ns_access.h
index b53f699..a921fb6 100644
--- a/arch/arm/include/asm/arch-ls102xa/ns_access.h
+++ b/arch/arm/include/asm/arch-ls102xa/ns_access.h
@@ -7,22 +7,6 @@
 #ifndef __FSL_NS_ACCESS_H_
 #define __FSL_NS_ACCESS_H_
 
-enum csu_cslx_access {
-   CSU_NS_SUP_R = 0x08,
-   CSU_NS_SUP_W = 0x80,
-   CSU_NS_SUP_RW = 0x88,
-   CSU_NS_USER_R = 0x04,
-   CSU_NS_USER_W = 0x40,
-   CSU_NS_USER_RW = 0x44,
-   CSU_S_SUP_R = 0x02,
-   CSU_S_SUP_W = 0x20,
-   CSU_S_SUP_RW = 0x22,
-   CSU_S_USER_R = 0x01,
-   CSU_S_USER_W = 0x10,
-   CSU_S_USER_RW = 0x11,
-   CSU_ALL_RW = 0xff,
-};
-
 enum csu_cslx_ind {
CSU_CSLX_PCIE2_IO = 0,
CSU_CSLX_PCIE1_IO,
@@ -108,11 +92,88 @@ enum csu_cslx_ind {
CSU_CSLX_MAX,
 };
 
-struct csu_ns_dev {
-   unsigned long ind;
-   uint32_t val;
+static struct csu_ns_dev ns_dev[] = {
+   { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
+   { CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
+   { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
+   { CSU_CSLX_IFC_MEM, CSU_ALL_RW },
+   { CSU_CSLX_OCRAM, CSU_ALL_RW },
+   { CSU_CSLX_GIC, CSU_ALL_RW },
+   { CSU_CSLX_PCIE1, CSU_ALL_RW },
+   { CSU_CSLX_OCRAM2, CSU_ALL_RW },
+   { CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
+   { CSU_CSLX_PCIE2, CSU_ALL_RW },
+   { CSU_CSLX_SATA, CSU_ALL_RW },
+   { CSU_CSLX_USB3, CSU_ALL_RW },
+   { CSU_CSLX_SERDES, CSU_ALL_RW },
+   { CSU_CSLX_QDMA, CSU_ALL_RW },
+   { CSU_CSLX_LPUART2, CSU_ALL_RW },
+   { CSU_CSLX_LPUART1, CSU_ALL_RW },
+   { CSU_CSLX_LPUART4, CSU_ALL_RW },
+   { CSU_CSLX_LPUART3, CSU_ALL_RW },
+   { CSU_CSLX_LPUART6, CSU_ALL_RW },
+   { CSU_CSLX_LPUART5, CSU_ALL_RW },
+   { CSU_CSLX_DSPI2, CSU_ALL_RW },
+   { CSU_CSLX_DSPI1, CSU_ALL_RW },
+   { CSU_CSLX_QSPI, CSU_ALL_RW },
+   { CSU_CSLX_ESDHC, CSU_ALL_RW },
+   { CSU_CSLX_2D_ACE, CSU_ALL_RW },
+   { CSU_CSLX_IFC, CSU_ALL_RW },
+   { CSU_CSLX_I2C1, CSU_ALL_RW },
+   { CSU_CSLX_USB2, CSU_ALL_RW },
+   { CSU_CSLX_I2C3, CSU_ALL_RW },
+   { CSU_CSLX_I2C2, CSU_ALL_RW },
+   { CSU_CSLX_DUART2, CSU_ALL_RW },
+   { CSU_CSLX_DUART1, CSU_ALL_RW },
+   { CSU_CSLX_WDT2, CSU_ALL_RW },
+   { CSU_CSLX_WDT1, CSU_ALL_RW },
+   { CSU_CSLX_EDMA, CSU_ALL_RW },
+   { CSU_CSLX_SYS_CNT, CSU_ALL_RW },
+   { CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
+   { CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
+   { CSU_CSLX_DDR, CSU_ALL_RW },
+   { CSU_CSLX_QUICC, CSU_ALL_RW },
+   { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
+   { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
+   { CSU_CSLX_SFP, CSU_ALL_RW },
+   { CSU_CSLX_TMU, CSU_ALL_RW },
+   { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
+   { CSU_CSLX_RESERVED0, CSU_ALL_RW },
+   { CSU_CSLX_ETSEC1, CSU_ALL_RW },
+   { CSU_CSLX_SEC5_5, CSU_ALL_RW },
+   { CSU_CSLX_ETSEC3, CSU_ALL_RW },
+   { CSU_CSLX_ETSEC2, CSU_ALL_RW },
+   { CSU_CSLX_GPIO2, CSU_ALL_RW },
+   { CSU_CSLX_GPIO1, CSU_ALL_RW },
+   { CSU_CSLX_GPIO4, CSU_ALL_RW },
+   { CSU_CSLX_GPIO3, CSU_ALL_RW },
+   { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
+   { CSU_CSLX_CSU, CSU_ALL_RW },
+   { CSU_CSLX_ASRC, CSU_ALL_RW },
+   { CSU_CSLX_SPDIF, CSU_ALL_RW },
+   { CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
+   { CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
+   { CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
+   { CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
+   { CSU_CSLX_SAI2, CSU_ALL_RW },
+   { CSU_CSLX_SAI1, CSU_ALL_RW },
+   { CSU_CSLX_SAI4, CSU_ALL_RW },
+   { CSU_CSLX_SAI3, CSU_ALL_RW },
+   { CSU_CSLX_FTM2, CSU_ALL_RW },
+   { CSU_CSLX_FTM1, CSU_ALL_RW },
+   { CSU_CSLX_FTM4, CSU_ALL_RW },
+   { CSU_CSLX_FTM3, CSU_ALL_RW },
+   { CSU_CSLX_FTM6, CSU_ALL_RW },
+   { CSU_CSLX_FTM5, CSU_ALL_RW },
+   { CSU_CSLX_FTM8, CSU_ALL_RW },
+   {