Re: [U-Boot] [Patch V6 11/18] armv8/fsl_lsch3: Change arch to fsl-layerscape

2015-10-22 Thread Hou Zhiqiang 


> -Original Message-
> From: Gong Qianyu [mailto:b52...@rhuath.am.freescale.net]
> Sent: 2015年10月19日 19:59
> To: u-boot@lists.denx.de
> Cc: Hu Mingkai-B21284; Sun York-R58495; Hou Zhiqiang-B48286; Xie Shaohui-
> B21989; Song Wenbin-B53747; Wood Scott-B07421; Kushwaha Prabhakar-B32579;
> Wang Huan-B18965; Gong Qianyu-B52263
> Subject: [Patch V6 11/18] armv8/fsl_lsch3: Change arch to fsl-layerscape
> 
> From: Mingkai Hu 
> 
> There are two LS series processors are built on ARMv8 Layersacpe
> architecture currently, LS2085A and LS1043A. They are based on
> ARMv8 core although use different chassis, so create fsl-layerscape
> to refactor the common code for the LS series processors which also
> paves the way for adding LS1043A platform.
> 
> Signed-off-by: Mingkai Hu 
> Signed-off-by: Gong Qianyu 

Qianyu, you lost my Signed-off.

Thanks,
Zhqiang
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [Patch V6 11/18] armv8/fsl_lsch3: Change arch to fsl-layerscape

2015-10-19 Thread Gong Qianyu 
From: Mingkai Hu 

There are two LS series processors are built on ARMv8 Layersacpe
architecture currently, LS2085A and LS1043A. They are based on
ARMv8 core although use different chassis, so create fsl-layerscape
to refactor the common code for the LS series processors which also
paves the way for adding LS1043A platform.

Signed-off-by: Mingkai Hu 
Signed-off-by: Gong Qianyu 
---
V6:
 - Remove GIC SMMU TZPC macros from ls2085a_common.h to config.h.
 - Modify fsl_lsch3_wake_secondary_cores() to 
fsl_layerscape_wake_seconday_cores()
 - Fix lsch3->layerscape changes for ls2085a emu and simu. 
V5:
 - Move LS2085A ddr macros out of soc #ifdef.
 - Move macros and structs from cpu.c to cpu.h.
 - Wrap le32 and be32 functions for ccsr gur and scfg. Defined in soc.h
 - Modify fsl-layerscape/Makefile.
V4:
 - New patch.

 arch/arm/cpu/armv8/Makefile|   2 +-
 arch/arm/cpu/armv8/fsl-layerscape/Makefile |  21 ++
 .../README => fsl-layerscape/README.lsch3} |   2 +-
 .../cpu/armv8/{fsl-lsch3 => fsl-layerscape}/cpu.c  | 248 ++---
 .../cpu/armv8/{fsl-lsch3 => fsl-layerscape}/cpu.h  |   2 +-
 .../cpu/armv8/{fsl-lsch3 => fsl-layerscape}/fdt.c  |  17 +-
 .../fsl_lsch3_serdes.c |   8 +-
 .../speed.c => fsl-layerscape/fsl_lsch3_speed.c}   |  12 +-
 .../armv8/{fsl-lsch3 => fsl-layerscape}/lowlevel.S |  14 +-
 .../{fsl-lsch3 => fsl-layerscape}/ls2085a_serdes.c |   3 +-
 .../cpu/armv8/{fsl-lsch3 => fsl-layerscape}/mp.c   |  16 +-
 .../cpu/armv8/{fsl-lsch3 => fsl-layerscape}/soc.c  |  35 +--
 arch/arm/cpu/armv8/fsl-layerscape/spl.c|  76 +++
 arch/arm/cpu/armv8/fsl-lsch3/Makefile  |  13 --
 arch/arm/cpu/armv8/fsl-lsch3/speed.h   |   7 -
 .../clock.h|   8 +-
 arch/arm/include/asm/arch-fsl-layerscape/config.h  |  96 
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 165 ++
 .../{arch-fsl-lsch3 => arch-fsl-layerscape}/fdt.h  |   4 +
 .../fsl_serdes.h   |  11 +-
 .../immap_lsch3.h  | 119 --
 .../arm/include/asm/arch-fsl-layerscape/imx-regs.h |  55 +
 .../ls2085a_stream_id.h|   0
 arch/arm/include/asm/arch-fsl-layerscape/mmu.h |  10 +
 .../asm/arch-fsl-layerscape}/mp.h  |  10 +-
 .../{arch-fsl-lsch3 => arch-fsl-layerscape}/soc.h  |  21 +-
 arch/arm/include/asm/arch-fsl-layerscape/speed.h   |  10 +
 arch/arm/include/asm/arch-fsl-lsch3/config.h   | 185 ---
 arch/arm/include/asm/arch-fsl-lsch3/gpio.h |   9 -
 arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h |  13 --
 arch/arm/include/asm/config.h  |   7 +-
 board/freescale/ls2085a/Kconfig|   4 +-
 board/freescale/ls2085a/ls2085a.c  |   2 +-
 board/freescale/ls2085aqds/Kconfig |   2 +-
 board/freescale/ls2085aqds/eth.c   |   1 -
 board/freescale/ls2085aqds/ls2085aqds.c|   2 +-
 board/freescale/ls2085ardb/Kconfig |   2 +-
 board/freescale/ls2085ardb/eth_ls2085rdb.c |   1 -
 board/freescale/ls2085ardb/ls2085ardb.c|   2 +-
 drivers/i2c/mxc_i2c.c  |   4 +-
 drivers/misc/fsl_debug_server.c|   1 -
 drivers/net/ldpaa_eth/ls2085a.c|   2 -
 drivers/pci/pcie_layerscape.c  |   4 +-
 include/common.h   |   3 +
 include/configs/ls2085a_common.h   |  10 +-
 45 files changed, 713 insertions(+), 526 deletions(-)

diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index adb11b3..48c041b 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -15,6 +15,6 @@ obj-y += cache.o
 obj-y  += tlb.o
 obj-y  += transition.o
 
-obj-$(CONFIG_FSL_LSCH3) += fsl-lsch3/
+obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/
 obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/
 obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile 
b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
new file mode 100644
index 000..ccb3aa5
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -0,0 +1,21 @@
+#
+# Copyright 2014-2015, Freescale Semiconductor
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += cpu.o
+obj-y += lowlevel.o
+obj-y += soc.o
+obj-$(CONFIG_MP) += mp.o
+obj-$(CONFIG_OF_LIBFDT) += fdt.o
+obj-$(CONFIG_SPL) += spl.o
+
+ifneq ($(CONFIG_FSL_LSCH3),)
+obj-y += fsl_lsch3_speed.o
+obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch3_serdes.o
+endif
+
+ifneq ($(CONFIG_LS2085A),)
+obj-$(CONFIG_SYS_HAS_SERDES) += ls2085a_serdes.o
+endif
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README 
b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3
similarity index 99%
rename from