From: Hou Zhiqiang <b48...@freescale.com>
After the secondary cores enter U-Boot, use CONFIG_ARMV8_MULTIENTRY to
make secondary cores excute in spin loop.
Signed-off-by: Hou Zhiqiang <b48...@freescale.com>
Signed-off-by: Mingkai Hu <mingkai...@freescale.com>
Signed-off-by: Gong Qianyu <qianyu.g...@freescale.com>
---
V7:
- No change.
V6:
- New patch.
arch/arm/Kconfig | 1 +
arch/arm/cpu/armv8/fsl-layerscape/mp.c | 14 ++++++++++++++
include/configs/ls1043a_common.h | 3 +++
3 files changed, 18 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6584e85..6e30a5d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -634,6 +634,7 @@ config TARGET_LS1021ATWR
config TARGET_LS1043ARDB
bool "Support ls1043ardb"
select ARM64
+ select ARMV8_MULTIENTRY
select SUPPORT_SPL
help
Support for Freescale LS1043ARDB platform.
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
index 1b13d32..0d600db 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
@@ -25,7 +25,11 @@ phys_addr_t determine_mp_bootpg(void)
int fsl_layerscape_wake_seconday_cores(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+#ifdef CONFIG_FSL_LSCH3
struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
+#elif defined(CONFIG_FSL_LSCH2)
+ struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
+#endif
u32 cores, cpu_up_mask = 1;
int i, timeout = 10;
u64 *table = get_spin_tbl_addr();
@@ -48,13 +52,23 @@ int fsl_layerscape_wake_seconday_cores(void)
printf("Waking secondary cores to start from %lx\n", gd->relocaddr);
+#ifdef CONFIG_FSL_LSCH3
gur_out32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32));
gur_out32(&gur->bootlocptrl, (u32)gd->relocaddr);
gur_out32(&gur->scratchrw[6], 1);
asm volatile("dsb st" : : : "memory");
rst->brrl = cores;
asm volatile("dsb st" : : : "memory");
+#elif defined(CONFIG_FSL_LSCH2)
+ scfg_out32(&scfg->scratchrw[0], (u32)(gd->relocaddr >> 32));
+ scfg_out32(&scfg->scratchrw[1], (u32)gd->relocaddr);
+ asm volatile("dsb st" : : : "memory");
+ gur_out32(&gur->brrl, cores);
+ asm volatile("dsb st" : : : "memory");
+ /* Bootup online cores */
+ scfg_out32(&scfg->corebcr, cores);
+#endif
/* This is needed as a precautionary measure.
* If some code before this has accidentally released the secondary
* cores then the pre-bootloader code will trap them in a "wfe" unless
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 85d9426..53745aa 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -13,6 +13,7 @@
#define CONFIG_FSL_LAYERSCAPE
#define CONFIG_FSL_LSCH2
#define CONFIG_LS1043A
+#define CONFIG_MP
#define CONFIG_SYS_FSL_CLK
#define CONFIG_GICV2
@@ -46,6 +47,8 @@
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CPU_RELEASE_ADDR secondary_boot_func
+
/* Generic Timer Definitions */
#define COUNTER_FREQUENCY 25000000 /* 25MHz */
--
2.1.0.27.g96db324
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