Re: [U-Boot] [Patch v1 2/4] armv8/fsl-lsch3: Release secondary cores from boot hold off with Boot Page
> > >> @@ -119,3 +107,94 @@ ENTRY(lowlevel_init) > > >> mov lr, x29 /* Restore LR */ > > >> ret > > >> ENDPROC(lowlevel_init) > > >> + > > >> + /* Keep literals not used by the secondary boot page outside > > it */ > > >> + .ltorg > > >> + > > >> + .align 4 > > > > > > That looks like a small alignment for a page. > > > > > > Should this be larger? Or is the "page" a misnomer here? > > > > I think as far as it is aligned to instruction size and keep "ldr" happy, > > it is OK. The code will be copied to the beginning of DDR to run. Any > > concern here? > > > > "page" is definitely a misnomer here, the comment (and maybe the label > below) should probably be altered. > The align directive is fine I guess. I think it can be dropped to .align 2 if it's just to keep the instruction stream aligned as per York's comment, but it's not harmful to have greater alignment (just slightly confusing when trying to figure out why the .align is there). [...] > > >> +#if defined(CONFIG_GICV3) > > >> + gic_wait_for_interrupt_m x0 > > >> +#endif > > >> + > > >> + bl secondary_switch_to_el2 > > >> +#ifdef CONFIG_ARMV8_SWITCH_TO_EL1 > > >> + secondary_switch_to_el1 > > >> +#endif > > >> + > > >> +slave_cpu: > > >> + wfe > > >> +#ifdef CONFIG_FSL_SMP_RELEASE_ALL > > >> + ldr x1, =CPU_RELEASE_ADDR > > >> + ldr x0, [x1] > > >> +#else > > >> + ldr x0, [x11] > > >> + tbnzx0, #0, slave_cpu > > >> +#endif > > >> + cbz x0, slave_cpu > > >> + br x0 /* branch to the given address > > */ > > > > > > Just to check, I take it CPUs won't ever be in a big-endian mode at > > > this point? > > > > Don't know yet. Any concern if big-endian here? > > I think we missed something here. Mark please correct me if I am > wrong. If the CPU is big-endian then we will need to convert the > address contained at "CPU_RELEASE_ADDR", since it will always be > written as a "single 64-bit little-endian value" (quoting from > Documentation/arm64/booting.txt") It sounds like you figured it out. As far as I am aware, all you need to do is byte-swap the value if CPUs are big-endian at this point. Linux will configure the CPUs to the endianness it desires before it makes any explicit memory accesses. > > > > > > > > >> +ENDPROC(secondary_boot_func) > > >> + > > >> +ENTRY(secondary_switch_to_el2) > > >> + switch_el x0, 1f, 0f, 0f > > >> +0: ret > > >> +1: armv8_switch_to_el2_m x0 > > >> +ENDPROC(secondary_switch_to_el2) > > >> + > > >> +ENTRY(secondary_switch_to_el1) > > >> + switch_el x0, 0f, 1f, 0f > > >> +0: ret > > >> +1: armv8_switch_to_el1_m x0, x1 > > >> +ENDPROC(secondary_switch_to_el1) > > >> + > > >> + /* Ensure that the literals used by the secondary boot page > > are > > >> +* assembled within it > > >> +*/ > > >> + .ltorg > > >> + > > >> + .align 4 > > > > > > Similarly to above, this looks like a small alignment for a page. > > > > Please suggest a proper alignment. > > > > Think this is confusion caused by our use of the term "secondary boot > page". I don't think it needs to be sized or aligned as a page. We > should probably change our terminology. If there's some better terminology we could use, it would certainly make things clearer. I must admit that the alternatives I came up with weren't much better. "Secondary boot region", perhaps? [...] > > >> + /* Initialize SCTLR_EL2 */ > > >> + msr sctlr_el2, xzr > > > > > > What about the RES1 bits (e.g. bits 29 & 28)? > > > > > > We don't seem to initialise them before the eret. > > > > I can't answer this question and below. Adding Arnab as the original > > author for these changes. > > > > York > > > > You are right, will fix this. According to the ARMv8 ARM, RES1 bits > "should be one or preserved". What should the preferred approach be > here? Write one or read modify and update the required bits? As this seems to be the first initialisation of sctlr_el2, I believe the correct thing to do is to write one for those bits, as their value may be UNKNOWN (if not hardwired). Per my reading of the ARM ARM's description of SBOP, after initialization read-modify-write preserving the value of those bits is the preferred way of modifying the register. > > > > > > >> + > > >> + /* Return to the EL2_SP2 mode from EL3 */ > > >> + mov \xreg1, sp > > >> + msr sp_el2, \xreg1 /* Migrate SP */ > > >> + mrs \xreg1, vbar_el3 > > >> + msr vbar_el2, \xreg1/* Migrate VBAR */ > > >> + mov x0, #0x3c9 > > Just noticed a bug here, x0 should in fact be \xreg1. My bad!! > > > >> + msr spsr_el3, \xreg1/* EL2_SP2 | D | A | I | F */ > > >> + msr elr_el3, lr > > >> + eret > > >> +.endm > > >> + > > >> +.macro armv8_switch_to_el1_m, xreg1, xreg2 > > >> + /* Initialize Gener
Re: [U-Boot] [Patch v1 2/4] armv8/fsl-lsch3: Release secondary cores from boot hold off with Boot Page
On Tue, Jul 08, 2014 at 06:56:26PM +0100, York Sun wrote:
> On 07/04/2014 05:31 AM, Mark Rutland wrote:
> > Hi York,
> >
> > I spotted a couple of generic issues below. Most of these are issues
> > with the existing code that you happen to be moving around, rather than
> > with the new code this patch introduces.
> >
> > There are a couple of gotchas around secondary startup that are painful
> > with the bootwrapper for arm64 at present, and I think that we can avoid
> > them by construction for U-Boot. More on that below.
> >
> > On Fri, Jun 27, 2014 at 05:54:08PM +0100, York Sun wrote:
> >> Secondary cores need to be released from holdoff by boot release
> >> registers. With GPP bootrom, they can boot from main memory
> >> directly. Individual spin table is used for each core. If a single
> >> release address is needed, defining macro CONFIG_FSL_SMP_RELEASE_ALL
> >> will use the CPU_RELEASE_ADDR. Spin table and the boot page is reserved
> >> in device tree so OS won't overwrite.
> >>
> >> Signed-off-by: York Sun
> >> Signed-off-by: Arnab Basu
> >> ---
> >> This set depends on this bundle
> >> http://patchwork.ozlabs.org/bundle/yorksun/armv8_fsl-lsch3/
> >>
> >> arch/arm/cpu/armv8/fsl-lsch3/Makefile |2 +
> >> arch/arm/cpu/armv8/fsl-lsch3/cpu.c| 13 ++
> >> arch/arm/cpu/armv8/fsl-lsch3/cpu.h|1 +
> >> arch/arm/cpu/armv8/fsl-lsch3/fdt.c| 56 +++
> >> arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S | 119 +++---
> >> arch/arm/cpu/armv8/fsl-lsch3/mp.c | 171
> >> +
> >> arch/arm/cpu/armv8/fsl-lsch3/mp.h | 36 +
> >> arch/arm/cpu/armv8/transition.S | 63 +---
> >> arch/arm/include/asm/arch-fsl-lsch3/config.h |3 +-
> >> arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h | 35 +
> >> arch/arm/include/asm/macro.h | 81 ++
> >> arch/arm/lib/gic_64.S | 10 +-
> >> common/board_f.c |2 +-
> >> 13 files changed, 502 insertions(+), 90 deletions(-)
> >> create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/fdt.c
> >> create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/mp.c
> >> create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/mp.h
> >
> > [...]
> >
> >> diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
> >> b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
> >> new file mode 100644
> >> index 000..cd34e16
> >> --- /dev/null
> >> +++ b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
> >> @@ -0,0 +1,56 @@
> >> +/*
> >> + * Copyright 2014 Freescale Semiconductor, Inc.
> >> + *
> >> + * SPDX-License-Identifier:GPL-2.0+
> >> + */
> >> +
> >> +#include
> >> +#include
> >> +#include
> >> +#include "mp.h"
> >> +
> >> +#ifdef CONFIG_MP
> >> +void ft_fixup_cpu(void *blob)
> >> +{
> >> + int off;
> >> + __maybe_unused u64 spin_tbl_addr = (u64)get_spin_tbl_addr();
> >> + u64 *reg;
> >> + u64 val;
> >> +
> >> + off = fdt_node_offset_by_prop_value(blob, -1, "device_type",
> >> "cpu", 4);
> >> + while (off != -FDT_ERR_NOTFOUND) {
> >> + reg = (u64 *)fdt_getprop(blob, off, "reg", 0);
> >> + if (reg) {
> >> + val = spin_tbl_addr;
> >> +#ifndef CONFIG_FSL_SMP_RELEASE_ALL
> >> + val += id_to_core(fdt64_to_cpu(*reg)) *
> >> SIZE_BOOT_ENTRY;
> >
> > In Linux we read /cpus/#address-cells to determine the size of a
> > CPU's reg property (and have dts where this is 1 cell). Will the above
> > work for that?
>
> I don't think so. Will have to add the same size check.
Cheers.
> >
> >> +#endif
> >> + val = cpu_to_fdt64(val);
> >> + fdt_setprop_string(blob, off, "enable-method",
> >> + "spin-table");
> >> + fdt_setprop(blob, off, "cpu-release-addr",
> >> + &val, sizeof(val));
> >> + } else {
> >> + puts("cpu NULL\n");
> >> + }
> >> + off = fdt_node_offset_by_prop_value(blob, off,
> >> "device_type",
> >> + "cpu", 4);
> >> + }
> >> + /*
> >> +* Boot page and spin table can be reserved here if not done
> >> staticlly
> >> +* in device tree.
> >> +*
> >> +* fdt_add_mem_rsv(blob, bootpg,
> >> +* *((u64 *)&(__secondary_boot_page_size)));
> >> +* If defined CONFIG_FSL_SMP_RELEASE_ALL, the release address
> >> should
> >> +* also be reserved.
> >> +*/
> >
> > I think that this reservation should _always_ be added by U-Boot unless
> > specifically overridden.
> >
> > A problem I had with the arm64 bootwrapper when adding PSCI support and
> > now (as I am moving stuff about) was that the DTS in the kernel tree had
> > a memreserve out-of-syn
Re: [U-Boot] [Patch v1 2/4] armv8/fsl-lsch3: Release secondary cores from boot hold off with Boot Page
> -Original Message-
> From: Sun York-R58495
> Sent: Tuesday, July 08, 2014 11:26 PM
> To: Mark Rutland
> Cc: u-boot@lists.denx.de; tr...@ti.com; Basu Arnab-B45036
> Subject: Re: [U-Boot] [Patch v1 2/4] armv8/fsl-lsch3: Release secondary
> cores from boot hold off with Boot Page
>
> On 07/04/2014 05:31 AM, Mark Rutland wrote:
> > Hi York,
> >
> > I spotted a couple of generic issues below. Most of these are issues
> > with the existing code that you happen to be moving around, rather
> > than with the new code this patch introduces.
> >
> > There are a couple of gotchas around secondary startup that are
> > painful with the bootwrapper for arm64 at present, and I think that we
> > can avoid them by construction for U-Boot. More on that below.
> >
> > On Fri, Jun 27, 2014 at 05:54:08PM +0100, York Sun wrote:
> >> Secondary cores need to be released from holdoff by boot release
> >> registers. With GPP bootrom, they can boot from main memory directly.
> >> Individual spin table is used for each core. If a single release
> >> address is needed, defining macro CONFIG_FSL_SMP_RELEASE_ALL will use
> >> the CPU_RELEASE_ADDR. Spin table and the boot page is reserved in
> >> device tree so OS won't overwrite.
> >>
> >> Signed-off-by: York Sun
> >> Signed-off-by: Arnab Basu
> >> ---
> >> This set depends on this bundle
> >> http://patchwork.ozlabs.org/bundle/yorksun/armv8_fsl-lsch3/
> >>
> >> arch/arm/cpu/armv8/fsl-lsch3/Makefile |2 +
> >> arch/arm/cpu/armv8/fsl-lsch3/cpu.c| 13 ++
> >> arch/arm/cpu/armv8/fsl-lsch3/cpu.h|1 +
> >> arch/arm/cpu/armv8/fsl-lsch3/fdt.c| 56 +++
> >> arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S | 119 +++-
> --
> >> arch/arm/cpu/armv8/fsl-lsch3/mp.c | 171
> +
> >> arch/arm/cpu/armv8/fsl-lsch3/mp.h | 36 +
> >> arch/arm/cpu/armv8/transition.S | 63 +---
> >> arch/arm/include/asm/arch-fsl-lsch3/config.h |3 +-
> >> arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h | 35 +
> >> arch/arm/include/asm/macro.h | 81 ++
> >> arch/arm/lib/gic_64.S | 10 +-
> >> common/board_f.c |2 +-
> >> 13 files changed, 502 insertions(+), 90 deletions(-) create mode
> >> 100644 arch/arm/cpu/armv8/fsl-lsch3/fdt.c
> >> create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/mp.c create mode
> >> 100644 arch/arm/cpu/armv8/fsl-lsch3/mp.h
> >
> > [...]
> >
> >> diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
> >> b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
> >> new file mode 100644
> >> index 000..cd34e16
> >> --- /dev/null
> >> +++ b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
> >> @@ -0,0 +1,56 @@
> >> +/*
> >> + * Copyright 2014 Freescale Semiconductor, Inc.
> >> + *
> >> + * SPDX-License-Identifier:GPL-2.0+
> >> + */
> >> +
> >> +#include
> >> +#include
> >> +#include
> >> +#include "mp.h"
> >> +
> >> +#ifdef CONFIG_MP
> >> +void ft_fixup_cpu(void *blob)
> >> +{
> >> + int off;
> >> + __maybe_unused u64 spin_tbl_addr = (u64)get_spin_tbl_addr();
> >> + u64 *reg;
> >> + u64 val;
> >> +
> >> + off = fdt_node_offset_by_prop_value(blob, -1, "device_type",
> "cpu", 4);
> >> + while (off != -FDT_ERR_NOTFOUND) {
> >> + reg = (u64 *)fdt_getprop(blob, off, "reg", 0);
> >> + if (reg) {
> >> + val = spin_tbl_addr; #ifndef
> >> +CONFIG_FSL_SMP_RELEASE_ALL
> >> + val += id_to_core(fdt64_to_cpu(*reg)) *
> >> +SIZE_BOOT_ENTRY;
> >
> > In Linux we read /cpus/#address-cells to determine the size of a CPU's
> > reg property (and have dts where this is 1 cell). Will the above work
> > for that?
>
> I don't think so. Will have to add the same size check.
>
> >
> >> +#endif
> >> + val = cpu_to_fdt64(val);
> >> + fdt_setprop_string(blob, off, "enable-method",
> >> + "spin-table");
> >> + fdt_set
Re: [U-Boot] [Patch v1 2/4] armv8/fsl-lsch3: Release secondary cores from boot hold off with Boot Page
On 07/04/2014 05:31 AM, Mark Rutland wrote:
> Hi York,
>
> I spotted a couple of generic issues below. Most of these are issues
> with the existing code that you happen to be moving around, rather than
> with the new code this patch introduces.
>
> There are a couple of gotchas around secondary startup that are painful
> with the bootwrapper for arm64 at present, and I think that we can avoid
> them by construction for U-Boot. More on that below.
>
> On Fri, Jun 27, 2014 at 05:54:08PM +0100, York Sun wrote:
>> Secondary cores need to be released from holdoff by boot release
>> registers. With GPP bootrom, they can boot from main memory
>> directly. Individual spin table is used for each core. If a single
>> release address is needed, defining macro CONFIG_FSL_SMP_RELEASE_ALL
>> will use the CPU_RELEASE_ADDR. Spin table and the boot page is reserved
>> in device tree so OS won't overwrite.
>>
>> Signed-off-by: York Sun
>> Signed-off-by: Arnab Basu
>> ---
>> This set depends on this bundle
>> http://patchwork.ozlabs.org/bundle/yorksun/armv8_fsl-lsch3/
>>
>> arch/arm/cpu/armv8/fsl-lsch3/Makefile |2 +
>> arch/arm/cpu/armv8/fsl-lsch3/cpu.c| 13 ++
>> arch/arm/cpu/armv8/fsl-lsch3/cpu.h|1 +
>> arch/arm/cpu/armv8/fsl-lsch3/fdt.c| 56 +++
>> arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S | 119 +++---
>> arch/arm/cpu/armv8/fsl-lsch3/mp.c | 171
>> +
>> arch/arm/cpu/armv8/fsl-lsch3/mp.h | 36 +
>> arch/arm/cpu/armv8/transition.S | 63 +---
>> arch/arm/include/asm/arch-fsl-lsch3/config.h |3 +-
>> arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h | 35 +
>> arch/arm/include/asm/macro.h | 81 ++
>> arch/arm/lib/gic_64.S | 10 +-
>> common/board_f.c |2 +-
>> 13 files changed, 502 insertions(+), 90 deletions(-)
>> create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/fdt.c
>> create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/mp.c
>> create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/mp.h
>
> [...]
>
>> diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
>> b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
>> new file mode 100644
>> index 000..cd34e16
>> --- /dev/null
>> +++ b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
>> @@ -0,0 +1,56 @@
>> +/*
>> + * Copyright 2014 Freescale Semiconductor, Inc.
>> + *
>> + * SPDX-License-Identifier:GPL-2.0+
>> + */
>> +
>> +#include
>> +#include
>> +#include
>> +#include "mp.h"
>> +
>> +#ifdef CONFIG_MP
>> +void ft_fixup_cpu(void *blob)
>> +{
>> + int off;
>> + __maybe_unused u64 spin_tbl_addr = (u64)get_spin_tbl_addr();
>> + u64 *reg;
>> + u64 val;
>> +
>> + off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu",
>> 4);
>> + while (off != -FDT_ERR_NOTFOUND) {
>> + reg = (u64 *)fdt_getprop(blob, off, "reg", 0);
>> + if (reg) {
>> + val = spin_tbl_addr;
>> +#ifndef CONFIG_FSL_SMP_RELEASE_ALL
>> + val += id_to_core(fdt64_to_cpu(*reg)) *
>> SIZE_BOOT_ENTRY;
>
> In Linux we read /cpus/#address-cells to determine the size of a
> CPU's reg property (and have dts where this is 1 cell). Will the above
> work for that?
I don't think so. Will have to add the same size check.
>
>> +#endif
>> + val = cpu_to_fdt64(val);
>> + fdt_setprop_string(blob, off, "enable-method",
>> + "spin-table");
>> + fdt_setprop(blob, off, "cpu-release-addr",
>> + &val, sizeof(val));
>> + } else {
>> + puts("cpu NULL\n");
>> + }
>> + off = fdt_node_offset_by_prop_value(blob, off, "device_type",
>> + "cpu", 4);
>> + }
>> + /*
>> +* Boot page and spin table can be reserved here if not done
>> staticlly
>> +* in device tree.
>> +*
>> +* fdt_add_mem_rsv(blob, bootpg,
>> +* *((u64 *)&(__secondary_boot_page_size)));
>> +* If defined CONFIG_FSL_SMP_RELEASE_ALL, the release address should
>> +* also be reserved.
>> +*/
>
> I think that this reservation should _always_ be added by U-Boot unless
> specifically overridden.
>
> A problem I had with the arm64 bootwrapper when adding PSCI support and
> now (as I am moving stuff about) was that the DTS in the kernel tree had
> a memreserve out-of-sync with what the wrapper actually needed. While I
> can add a new reservation, I can't remove any in case they are for
> something else, so I end up protecting too much, wasting memory.
>
> Given that the reservation is to protect data which U-Boot is in control
> of choosing the address for, I think
Re: [U-Boot] [Patch v1 2/4] armv8/fsl-lsch3: Release secondary cores from boot hold off with Boot Page
Hi York,
I spotted a couple of generic issues below. Most of these are issues
with the existing code that you happen to be moving around, rather than
with the new code this patch introduces.
There are a couple of gotchas around secondary startup that are painful
with the bootwrapper for arm64 at present, and I think that we can avoid
them by construction for U-Boot. More on that below.
On Fri, Jun 27, 2014 at 05:54:08PM +0100, York Sun wrote:
> Secondary cores need to be released from holdoff by boot release
> registers. With GPP bootrom, they can boot from main memory
> directly. Individual spin table is used for each core. If a single
> release address is needed, defining macro CONFIG_FSL_SMP_RELEASE_ALL
> will use the CPU_RELEASE_ADDR. Spin table and the boot page is reserved
> in device tree so OS won't overwrite.
>
> Signed-off-by: York Sun
> Signed-off-by: Arnab Basu
> ---
> This set depends on this bundle
> http://patchwork.ozlabs.org/bundle/yorksun/armv8_fsl-lsch3/
>
> arch/arm/cpu/armv8/fsl-lsch3/Makefile |2 +
> arch/arm/cpu/armv8/fsl-lsch3/cpu.c| 13 ++
> arch/arm/cpu/armv8/fsl-lsch3/cpu.h|1 +
> arch/arm/cpu/armv8/fsl-lsch3/fdt.c| 56 +++
> arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S | 119 +++---
> arch/arm/cpu/armv8/fsl-lsch3/mp.c | 171
> +
> arch/arm/cpu/armv8/fsl-lsch3/mp.h | 36 +
> arch/arm/cpu/armv8/transition.S | 63 +---
> arch/arm/include/asm/arch-fsl-lsch3/config.h |3 +-
> arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h | 35 +
> arch/arm/include/asm/macro.h | 81 ++
> arch/arm/lib/gic_64.S | 10 +-
> common/board_f.c |2 +-
> 13 files changed, 502 insertions(+), 90 deletions(-)
> create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/fdt.c
> create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/mp.c
> create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/mp.h
[...]
> diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
> b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
> new file mode 100644
> index 000..cd34e16
> --- /dev/null
> +++ b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
> @@ -0,0 +1,56 @@
> +/*
> + * Copyright 2014 Freescale Semiconductor, Inc.
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + */
> +
> +#include
> +#include
> +#include
> +#include "mp.h"
> +
> +#ifdef CONFIG_MP
> +void ft_fixup_cpu(void *blob)
> +{
> + int off;
> + __maybe_unused u64 spin_tbl_addr = (u64)get_spin_tbl_addr();
> + u64 *reg;
> + u64 val;
> +
> + off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu",
> 4);
> + while (off != -FDT_ERR_NOTFOUND) {
> + reg = (u64 *)fdt_getprop(blob, off, "reg", 0);
> + if (reg) {
> + val = spin_tbl_addr;
> +#ifndef CONFIG_FSL_SMP_RELEASE_ALL
> + val += id_to_core(fdt64_to_cpu(*reg)) *
> SIZE_BOOT_ENTRY;
In Linux we read /cpus/#address-cells to determine the size of a
CPU's reg property (and have dts where this is 1 cell). Will the above
work for that?
> +#endif
> + val = cpu_to_fdt64(val);
> + fdt_setprop_string(blob, off, "enable-method",
> + "spin-table");
> + fdt_setprop(blob, off, "cpu-release-addr",
> + &val, sizeof(val));
> + } else {
> + puts("cpu NULL\n");
> + }
> + off = fdt_node_offset_by_prop_value(blob, off, "device_type",
> + "cpu", 4);
> + }
> + /*
> +* Boot page and spin table can be reserved here if not done staticlly
> +* in device tree.
> +*
> +* fdt_add_mem_rsv(blob, bootpg,
> +* *((u64 *)&(__secondary_boot_page_size)));
> +* If defined CONFIG_FSL_SMP_RELEASE_ALL, the release address should
> +* also be reserved.
> +*/
I think that this reservation should _always_ be added by U-Boot unless
specifically overridden.
A problem I had with the arm64 bootwrapper when adding PSCI support and
now (as I am moving stuff about) was that the DTS in the kernel tree had
a memreserve out-of-sync with what the wrapper actually needed. While I
can add a new reservation, I can't remove any in case they are for
something else, so I end up protecting too much, wasting memory.
Given that the reservation is to protect data which U-Boot is in control
of choosing the address for, I think the only sane thing to do is for
U-Boot to always add the reservation.
That way U-Boot can change and existing DTBs will just work. We won't
end up protecting too much or too little.
[...]
> @@ -119,3 +107,94 @@ ENTRY(lowlevel_init)
> mov
[U-Boot] [Patch v1 2/4] armv8/fsl-lsch3: Release secondary cores from boot hold off with Boot Page
Secondary cores need to be released from holdoff by boot release
registers. With GPP bootrom, they can boot from main memory
directly. Individual spin table is used for each core. If a single
release address is needed, defining macro CONFIG_FSL_SMP_RELEASE_ALL
will use the CPU_RELEASE_ADDR. Spin table and the boot page is reserved
in device tree so OS won't overwrite.
Signed-off-by: York Sun
Signed-off-by: Arnab Basu
---
This set depends on this bundle
http://patchwork.ozlabs.org/bundle/yorksun/armv8_fsl-lsch3/
arch/arm/cpu/armv8/fsl-lsch3/Makefile |2 +
arch/arm/cpu/armv8/fsl-lsch3/cpu.c| 13 ++
arch/arm/cpu/armv8/fsl-lsch3/cpu.h|1 +
arch/arm/cpu/armv8/fsl-lsch3/fdt.c| 56 +++
arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S | 119 +++---
arch/arm/cpu/armv8/fsl-lsch3/mp.c | 171 +
arch/arm/cpu/armv8/fsl-lsch3/mp.h | 36 +
arch/arm/cpu/armv8/transition.S | 63 +---
arch/arm/include/asm/arch-fsl-lsch3/config.h |3 +-
arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h | 35 +
arch/arm/include/asm/macro.h | 81 ++
arch/arm/lib/gic_64.S | 10 +-
common/board_f.c |2 +-
13 files changed, 502 insertions(+), 90 deletions(-)
create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/fdt.c
create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/mp.c
create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/mp.h
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/Makefile
b/arch/arm/cpu/armv8/fsl-lsch3/Makefile
index 9249537..f920eeb 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/Makefile
+++ b/arch/arm/cpu/armv8/fsl-lsch3/Makefile
@@ -7,3 +7,5 @@
obj-y += cpu.o
obj-y += lowlevel.o
obj-y += speed.o
+obj-$(CONFIG_MP) += mp.o
+obj-$(CONFIG_OF_LIBFDT) += fdt.o
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
index c129d03..47b947f 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
@@ -11,6 +11,7 @@
#include
#include
#include "cpu.h"
+#include "mp.h"
#include "speed.h"
#include
@@ -434,3 +435,15 @@ int cpu_eth_init(bd_t *bis)
#endif
return error;
}
+
+
+int arch_early_init_r(void)
+{
+ int rv;
+ rv = fsl_lsch3_wake_seconday_cores();
+
+ if (rv)
+ printf("Did not wake secondary cores\n");
+
+ return 0;
+}
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.h
b/arch/arm/cpu/armv8/fsl-lsch3/cpu.h
index 28544d7..2e3312b 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.h
+++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.h
@@ -5,3 +5,4 @@
*/
int fsl_qoriq_core_to_cluster(unsigned int core);
+u32 cpu_mask(void);
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
new file mode 100644
index 000..cd34e16
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include "mp.h"
+
+#ifdef CONFIG_MP
+void ft_fixup_cpu(void *blob)
+{
+ int off;
+ __maybe_unused u64 spin_tbl_addr = (u64)get_spin_tbl_addr();
+ u64 *reg;
+ u64 val;
+
+ off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
+ while (off != -FDT_ERR_NOTFOUND) {
+ reg = (u64 *)fdt_getprop(blob, off, "reg", 0);
+ if (reg) {
+ val = spin_tbl_addr;
+#ifndef CONFIG_FSL_SMP_RELEASE_ALL
+ val += id_to_core(fdt64_to_cpu(*reg)) * SIZE_BOOT_ENTRY;
+#endif
+ val = cpu_to_fdt64(val);
+ fdt_setprop_string(blob, off, "enable-method",
+ "spin-table");
+ fdt_setprop(blob, off, "cpu-release-addr",
+ &val, sizeof(val));
+ } else {
+ puts("cpu NULL\n");
+ }
+ off = fdt_node_offset_by_prop_value(blob, off, "device_type",
+ "cpu", 4);
+ }
+ /*
+* Boot page and spin table can be reserved here if not done staticlly
+* in device tree.
+*
+* fdt_add_mem_rsv(blob, bootpg,
+* *((u64 *)&(__secondary_boot_page_size)));
+* If defined CONFIG_FSL_SMP_RELEASE_ALL, the release address should
+* also be reserved.
+*/
+}
+#endif
+
+void ft_cpu_setup(void *blob, bd_t *bd)
+{
+#ifdef CONFIG_MP
+ ft_fixup_cpu(blob);
+#endif
+}
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
index b4720ae..162d3d6 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
@@ -8,7 +8,9 @@
#include
#include
+#include
