Re: [U-Boot] [RFC] Attempt to Add SPL Support to imx6q_logic

[Lukasz Majewski]

Hi Adam,

> The Logic PD i.MX6 dev kit is capable of SPL.  This patch follows
> a similar method as the mx6sabresd
> 
> Following instructions I found which show to put the SPL and .img
> files on the SD card with dd.
> 
> sudo dd if=SPL of=/dev/xxx bs=1K seek=1; sync
> sudo dd if=u-boot.img of=/dev/xxx bs=1K seek=69

The second line requires the u-boot.img stored at 69KiB offset.

> 
> I would prefer to have the u-boot.img in a standard partition if
> possible similar to how the omap3_logic board is done.
> 
> Unfortunately with DEBUG enabled in SPL, I only see:
> 
> U-Boot SPL 2017.11-rc2-00019-g23d51be-dirty (Oct 21 2017 - 16:14:59)
> >>spl:board_init_r()
> spl_early_init()
> Trying to boot from MMC1

It seems like you have specified the u-boot.img eMMC offset in a wrong
way.

Please look for following option:
SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR

It should configure SPL to load u-boot.img from proper eMMC LBA offset.


> 
> I was hoping someone with an i.MX6 might have some insight.
> 
> Signed-off-by: Adam Ford 
> 
> diff --git a/arch/arm/mach-imx/mx6/Kconfig
> b/arch/arm/mach-imx/mx6/Kconfig index b82db3a..750be47 100644
> --- a/arch/arm/mach-imx/mx6/Kconfig
> +++ b/arch/arm/mach-imx/mx6/Kconfig
> @@ -189,6 +189,7 @@ config TARGET_MX6LOGICPD
>   select DM_PMIC
>   select DM_REGULATOR
>   select OF_CONTROL
> + select SUPPORT_SPL
>  
>  config TARGET_MX6QARM2
>   bool "mx6qarm2"
> diff --git a/board/logicpd/imx6/imx6logic.c
> b/board/logicpd/imx6/imx6logic.c index 1f3e378..4742ab8 100644
> --- a/board/logicpd/imx6/imx6logic.c
> +++ b/board/logicpd/imx6/imx6logic.c
> @@ -61,6 +61,7 @@ static iomux_v3_cfg_t const uart3_pads[] = {
>   MX6_PAD_EIM_EB3__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
>  };
>  
> +#ifndef CONFIG_SPL_BUILD
>  static void fixup_enet_clock(void)
>  {
>   struct iomuxc *iomuxc_regs = (struct iomuxc
> *)IOMUXC_BASE_ADDR; @@ -109,6 +110,7 @@ static void
> fixup_enet_clock(void) dm_gpio_set_value(, 1);
>   mdelay(50);
>  }
> +#endif
>  
>  static void setup_iomux_uart(void)
>  {
> @@ -159,7 +161,9 @@ int overwrite_console(void)
>  
>  int board_early_init_f(void)
>  {
> +#ifndef CONFIG_SPL_BUILD
>   fixup_enet_clock();
> +#endif
>   setup_iomux_uart();
>   setup_nand_pins();
>   return 0;
> @@ -183,3 +187,143 @@ int board_late_init(void)
>  
>   return 0;
>  }
> +
> +#ifdef CONFIG_SPL_BUILD
> +#include 
> +#include 
> +#include 
> +#include 
> +#include "asm/arch-mx6/mx6q-ddr.h"
> +#include "asm/arch-mx6/iomux.h"
> +#include "asm/arch-mx6/crm_regs.h"
> +
> +int spl_start_uboot(void)
> +{
> + return 1;
> +}
> +
> +static void ccgr_init(void)
> +{
> + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg
> *)CCM_BASE_ADDR; +
> + writel(0x00C03F3F, >CCGR0);
> + writel(0x0030FC03, >CCGR1);
> + writel(0x0FFFC000, >CCGR2);
> + writel(0x3FF0, >CCGR3);
> + writel(0xF300, >CCGR4);
> + writel(0x0FF3, >CCGR5);
> + writel(0x0FFF, >CCGR6);
> +}
> +
> +static int mx6q_dcd_table[] = {
> +
> + MX6_IOM_GRP_DDR_TYPE, 0x000C,
> + MX6_IOM_GRP_DDRPKE, 0x,
> + MX6_IOM_DRAM_SDCLK_0, 0x0030,
> + MX6_IOM_DRAM_SDCLK_1, 0x0030,
> + MX6_IOM_DRAM_CAS, 0x0030,
> + MX6_IOM_DRAM_RAS, 0x0030,
> + MX6_IOM_GRP_ADDDS, 0x0030,
> + MX6_IOM_DRAM_RESET, 0x0030,
> + MX6_IOM_DRAM_SDBA2, 0x,
> + MX6_IOM_DRAM_SDODT0, 0x0030,
> + MX6_IOM_DRAM_SDODT1, 0x0030,
> + MX6_IOM_GRP_CTLDS, 0x0030,
> + MX6_IOM_DDRMODE_CTL, 0x0002,
> + MX6_IOM_DRAM_SDQS0, 0x0030,
> + MX6_IOM_DRAM_SDQS1, 0x0030,
> + MX6_IOM_DRAM_SDQS2, 0x0030,
> + MX6_IOM_DRAM_SDQS3, 0x0030,
> + MX6_IOM_GRP_DDRMODE, 0x0002,
> + MX6_IOM_GRP_B0DS, 0x0030,
> + MX6_IOM_GRP_B1DS, 0x0030,
> + MX6_IOM_GRP_B2DS, 0x0030,
> + MX6_IOM_GRP_B3DS, 0x0030,
> + MX6_IOM_DRAM_DQM0, 0x0030,
> + MX6_IOM_DRAM_DQM1, 0x0030,
> + MX6_IOM_DRAM_DQM2, 0x0030,
> + MX6_IOM_DRAM_DQM3, 0x0030,
> + MX6_MMDC_P0_MDSCR, 0x8000,
> + MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
> + MX6_MMDC_P0_MPWLDECTRL0, 0x002D003A,
> + MX6_MMDC_P0_MPWLDECTRL1, 0x0038002B,
> + MX6_MMDC_P0_MPDGCTRL0, 0x03340338,
> + MX6_MMDC_P0_MPDGCTRL1, 0x0334032C,
> + MX6_MMDC_P0_MPRDDLCTL, 0x4036383C,
> + MX6_MMDC_P0_MPWRDLCTL, 0x2E384038,
> + MX6_MMDC_P0_MPRDDQBY0DL, 0x,
> + MX6_MMDC_P0_MPRDDQBY1DL, 0x,
> + MX6_MMDC_P0_MPRDDQBY2DL, 0x,
> + MX6_MMDC_P0_MPRDDQBY3DL, 0x,
> + MX6_MMDC_P0_MPMUR0, 0x0800,
> + MX6_MMDC_P0_MDPDC, 0x00020036,
> + MX6_MMDC_P0_MDOTC, 0x09444040,
> + MX6_MMDC_P0_MDCFG0, 0xB8BE7955,
> + MX6_MMDC_P0_MDCFG1, 0xFF328F64,
> + MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
> + MX6_MMDC_P0_MDMISC, 0x00011740,
> + MX6_MMDC_P0_MDSCR, 0x8000,
> + MX6_MMDC_P0_MDRWD, 0x26D2,
> + 

[U-Boot] [RFC] Attempt to Add SPL Support to imx6q_logic

[Adam Ford]

The Logic PD i.MX6 dev kit is capable of SPL.  This patch follows
a similar method as the mx6sabresd

Following instructions I found which show to put the SPL and .img
files on the SD card with dd.

sudo dd if=SPL of=/dev/xxx bs=1K seek=1; sync
sudo dd if=u-boot.img of=/dev/xxx bs=1K seek=69

I would prefer to have the u-boot.img in a standard partition if
possible similar to how the omap3_logic board is done.

Unfortunately with DEBUG enabled in SPL, I only see:

U-Boot SPL 2017.11-rc2-00019-g23d51be-dirty (Oct 21 2017 - 16:14:59)
>>spl:board_init_r()
spl_early_init()
Trying to boot from MMC1

I was hoping someone with an i.MX6 might have some insight.

Signed-off-by: Adam Ford 

diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index b82db3a..750be47 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -189,6 +189,7 @@ config TARGET_MX6LOGICPD
select DM_PMIC
select DM_REGULATOR
select OF_CONTROL
+   select SUPPORT_SPL
 
 config TARGET_MX6QARM2
bool "mx6qarm2"
diff --git a/board/logicpd/imx6/imx6logic.c b/board/logicpd/imx6/imx6logic.c
index 1f3e378..4742ab8 100644
--- a/board/logicpd/imx6/imx6logic.c
+++ b/board/logicpd/imx6/imx6logic.c
@@ -61,6 +61,7 @@ static iomux_v3_cfg_t const uart3_pads[] = {
MX6_PAD_EIM_EB3__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
+#ifndef CONFIG_SPL_BUILD
 static void fixup_enet_clock(void)
 {
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
@@ -109,6 +110,7 @@ static void fixup_enet_clock(void)
dm_gpio_set_value(, 1);
mdelay(50);
 }
+#endif
 
 static void setup_iomux_uart(void)
 {
@@ -159,7 +161,9 @@ int overwrite_console(void)
 
 int board_early_init_f(void)
 {
+#ifndef CONFIG_SPL_BUILD
fixup_enet_clock();
+#endif
setup_iomux_uart();
setup_nand_pins();
return 0;
@@ -183,3 +187,143 @@ int board_late_init(void)
 
return 0;
 }
+
+#ifdef CONFIG_SPL_BUILD
+#include 
+#include 
+#include 
+#include 
+#include "asm/arch-mx6/mx6q-ddr.h"
+#include "asm/arch-mx6/iomux.h"
+#include "asm/arch-mx6/crm_regs.h"
+
+int spl_start_uboot(void)
+{
+   return 1;
+}
+
+static void ccgr_init(void)
+{
+   struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+   writel(0x00C03F3F, >CCGR0);
+   writel(0x0030FC03, >CCGR1);
+   writel(0x0FFFC000, >CCGR2);
+   writel(0x3FF0, >CCGR3);
+   writel(0xF300, >CCGR4);
+   writel(0x0FF3, >CCGR5);
+   writel(0x0FFF, >CCGR6);
+}
+
+static int mx6q_dcd_table[] = {
+
+   MX6_IOM_GRP_DDR_TYPE, 0x000C,
+   MX6_IOM_GRP_DDRPKE, 0x,
+   MX6_IOM_DRAM_SDCLK_0, 0x0030,
+   MX6_IOM_DRAM_SDCLK_1, 0x0030,
+   MX6_IOM_DRAM_CAS, 0x0030,
+   MX6_IOM_DRAM_RAS, 0x0030,
+   MX6_IOM_GRP_ADDDS, 0x0030,
+   MX6_IOM_DRAM_RESET, 0x0030,
+   MX6_IOM_DRAM_SDBA2, 0x,
+   MX6_IOM_DRAM_SDODT0, 0x0030,
+   MX6_IOM_DRAM_SDODT1, 0x0030,
+   MX6_IOM_GRP_CTLDS, 0x0030,
+   MX6_IOM_DDRMODE_CTL, 0x0002,
+   MX6_IOM_DRAM_SDQS0, 0x0030,
+   MX6_IOM_DRAM_SDQS1, 0x0030,
+   MX6_IOM_DRAM_SDQS2, 0x0030,
+   MX6_IOM_DRAM_SDQS3, 0x0030,
+   MX6_IOM_GRP_DDRMODE, 0x0002,
+   MX6_IOM_GRP_B0DS, 0x0030,
+   MX6_IOM_GRP_B1DS, 0x0030,
+   MX6_IOM_GRP_B2DS, 0x0030,
+   MX6_IOM_GRP_B3DS, 0x0030,
+   MX6_IOM_DRAM_DQM0, 0x0030,
+   MX6_IOM_DRAM_DQM1, 0x0030,
+   MX6_IOM_DRAM_DQM2, 0x0030,
+   MX6_IOM_DRAM_DQM3, 0x0030,
+   MX6_MMDC_P0_MDSCR, 0x8000,
+   MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
+   MX6_MMDC_P0_MPWLDECTRL0, 0x002D003A,
+   MX6_MMDC_P0_MPWLDECTRL1, 0x0038002B,
+   MX6_MMDC_P0_MPDGCTRL0, 0x03340338,
+   MX6_MMDC_P0_MPDGCTRL1, 0x0334032C,
+   MX6_MMDC_P0_MPRDDLCTL, 0x4036383C,
+   MX6_MMDC_P0_MPWRDLCTL, 0x2E384038,
+   MX6_MMDC_P0_MPRDDQBY0DL, 0x,
+   MX6_MMDC_P0_MPRDDQBY1DL, 0x,
+   MX6_MMDC_P0_MPRDDQBY2DL, 0x,
+   MX6_MMDC_P0_MPRDDQBY3DL, 0x,
+   MX6_MMDC_P0_MPMUR0, 0x0800,
+   MX6_MMDC_P0_MDPDC, 0x00020036,
+   MX6_MMDC_P0_MDOTC, 0x09444040,
+   MX6_MMDC_P0_MDCFG0, 0xB8BE7955,
+   MX6_MMDC_P0_MDCFG1, 0xFF328F64,
+   MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
+   MX6_MMDC_P0_MDMISC, 0x00011740,
+   MX6_MMDC_P0_MDSCR, 0x8000,
+   MX6_MMDC_P0_MDRWD, 0x26D2,
+   MX6_MMDC_P0_MDOR, 0x00BE1023,
+   MX6_MMDC_P0_MDASP, 0x0047,
+   MX6_MMDC_P0_MDCTL, 0x8519,
+   MX6_MMDC_P0_MDSCR, 0x00888032,
+   MX6_MMDC_P0_MDSCR, 0x8033,
+   MX6_MMDC_P0_MDSCR, 0x8031,
+   MX6_MMDC_P0_MDSCR, 0x19408030,
+   MX6_MMDC_P0_MDSCR, 0x04008040,
+   MX6_MMDC_P0_MDREF, 0x7800,
+   MX6_MMDC_P0_MPODTCTRL, 0x0007,
+   MX6_MMDC_P0_MDPDC, 0x00025576,
+   MX6_MMDC_P0_MAPSR,