Re: [U-Boot] [RFC PATCH] rockchip: asus c201 support

[Simon Glass]

Hi Marty,

On 3 October 2017 at 16:03, Marty E. Plummer  wrote:
>
> From: "Marty E. Plummer" 
>
> I realize this patch is not up to standards for the sake of mainlining
> right now, but I'm mostly interested in getting some feedback on how
> to make it work before getting into the nicities of mainline inclusion.
>
> As of right now the bulk of this is the rk3288-veyron-speedy.dts file,
> which I assume has a similar enough boot system to the jerry and minnie.
>
> If the resultant u-boot-spl.bin and u-boot-dtb.img are prepared according
> to the instructions in doc/README.rockchip and then flashed to the c201's
> spi memory I get very little in the way of result; the most I/O that to
> be seen is the board reacts to the power switch (led on, led off). I can
> not seem to get it to output the u-boot console to the built-in screen,
> and currently do not have a mini-hdmi cable to see if that is working or
> not (one is ordered, arrives thursday). Can't find a location to purchase
> a servo board for better debugging possibilities.
>
> I was hoping someone on this mailing list could assist me in getting this
> to work; once a working setup is figured I'll do  proper patchset for
> mainline inclusion.

This boots for me:

U-Boot SPL 2017.11-rc2-00017-g6cda208-dirty (Oct 19 2017 - 17:20:26)
Trying to boot from SPI


U-Boot 2017.11-rc2-00017-g6cda208-dirty (Oct 19 2017 - 17:20:26 -0600)

Model: Google Speedy
DRAM:  2 GiB
MMC:   dwmmc@ff0c: 1, dwmmc@ff0d: 2, dwmmc@ff0f: 0
Using default environment

In:cros-ec-keyb
Out:   vidconsole
Err:   vidconsole
Model: Google Speedy
Net:   Net Initialization Skipped
No ethernet found.
Hit any key to stop autoboot:  0
=>

The display and keyboard work also. About 15% of the time it hangs at
'Using default environment' for about 5 seconds. Not sure why.
Sometimes I see a blank screen in that case. Also the screen is very
slow (as if the cache is off), even through the 'dhrystone' command
shows a healthy 2421 DMIPS.

After building in b/chromebook_speedy I use this to write it to an
em100 SPI emulator:

./b/chromebook_speedy/tools/mkimage -n rk3288 -T rkspi -d
b/chromebook_speedy/spl/u-boot-spl.bin spl.bin && dd if=spl.bin
of=spl-out.bin bs=128K conv=sync && cat spl-out.bin
b/chromebook_speedy/u-boot.img >out.bin && dd if=out.bin
of=out.bin.pad bs=4M conv=sync && sudo em100 -s -c GD25LQ32 -d
out.bin.pad -r

The image is out.bin.pad. See here for my version:

https://drive.google.com/open?id=0B7WYZbZ9zd-3ZUJPUHItejR0QnM

I applied your patch to:

0def58f (upstream/master) Merge git://git.denx.de/u-boot-x86

and my only change was to change the model to 'Google Speedy' in the .dts file.

I wonder if you might have a different model to me? You can check this
by booting into dev mode, logging in as root and typing:

cbmem -c |grep -i ram

My 'RAM Config' is 0.

Also with cbmem -c I can see that it has a compat preference of
google,veyron-speedy-rev5

Regards,
Simon
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[U-Boot] [RFC PATCH] rockchip: asus c201 support

[Marty E. Plummer]

From: "Marty E. Plummer" 

I realize this patch is not up to standards for the sake of mainlining
right now, but I'm mostly interested in getting some feedback on how
to make it work before getting into the nicities of mainline inclusion.

As of right now the bulk of this is the rk3288-veyron-speedy.dts file,
which I assume has a similar enough boot system to the jerry and minnie.

If the resultant u-boot-spl.bin and u-boot-dtb.img are prepared according
to the instructions in doc/README.rockchip and then flashed to the c201's
spi memory I get very little in the way of result; the most I/O that to
be seen is the board reacts to the power switch (led on, led off). I can
not seem to get it to output the u-boot console to the built-in screen,
and currently do not have a mini-hdmi cable to see if that is working or
not (one is ordered, arrives thursday). Can't find a location to purchase
a servo board for better debugging possibilities.

I was hoping someone on this mailing list could assist me in getting this
to work; once a working setup is figured I'll do  proper patchset for
mainline inclusion.

Regards,
Marty
---
 arch/arm/dts/Makefile |   1 +
 arch/arm/dts/rk3288-veyron-speedy.dts | 203 ++
 arch/arm/mach-rockchip/rk3288-board-spl.c |   3 +-
 arch/arm/mach-rockchip/rk3288/Kconfig |  11 ++
 board/google/veyron/Kconfig   |  16 +++
 configs/chromebook_speedy_defconfig   |  92 ++
 drivers/mtd/spi/spi_flash_ids.c   |   1 +
 7 files changed, 326 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/rk3288-veyron-speedy.dts
 create mode 100644 configs/chromebook_speedy_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7c062f0cad..c8630889dc 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -41,6 +41,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-veyron-jerry.dtb \
rk3288-veyron-mickey.dtb \
rk3288-veyron-minnie.dtb \
+   rk3288-veyron-speedy.dtb \
rk3288-vyasa.dtb \
rk3328-evb.dtb \
rk3368-lion.dtb \
diff --git a/arch/arm/dts/rk3288-veyron-speedy.dts 
b/arch/arm/dts/rk3288-veyron-speedy.dts
new file mode 100644
index 00..51e155d141
--- /dev/null
+++ b/arch/arm/dts/rk3288-veyron-speedy.dts
@@ -0,0 +1,203 @@
+/*
+ * Google Veyron Speedy Rev 1+ board device tree source
+ *
+ * Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+/dts-v1/;
+#include 
+#include 
+#include 
+#include "rk3288-veyron-chromebook.dtsi"
+#include "cros-ec-sbs.dtsi"
+
+/ {
+   model = "Google Jerry";
+   compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8",
+"google,veyron-speedy-rev7", "google,veyron-speedy-rev6",
+"google,veyron-speedy-rev5", "google,veyron-speedy-rev4",
+"google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
+"google,veyron-speedy", "google,veyron", "rockchip,rk3288";
+
+/* chosen { */
+/* stdout-path =  */
+/* }; */
+
+   panel_regulator: panel-regulator {
+   compatible = "regulator-fixed";
+   enable-active-high;
+   gpio = < RK_PB6 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_enable_h>;
+   regulator-name = "panel_regulator";
+   vin-supply = <_sys>;
+   };
+
+   vcc18_lcd: vcc18-lcd {
+   compatible = "regulator-fixed";
+   enable-active-high;
+   gpio = < RK_PB5 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_1v8_disp_en>;
+   regulator-name = "vcc18_lcd";
+   regulator-always-on;
+   regulator-boot-on;
+   vin-supply = <_wl>;
+   };
+
+   backlight_regulator: backlight-regulator {
+   compatible = "regulator-fixed";
+   enable-active-high;
+   gpio = < RK_PB4 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_pwr_en>;
+   regulator-name = "backlight_regulator";
+   vin-supply = <_sys>;
+   startup-delay-us = <15000>;
+   };
+};
+
+ {
+   rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
+   0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
+   0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
+   0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
+   0x8 0x1f4>;
+   rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
+   0x0 0xc3 0x6 0x1>;
+   rockchip,sdram-params = <0x20D266A4 0x5B6 6 53300 6 13 0>;
+};
+
+_keys {
+   power {
+   gpios = < RK_PA5 GPIO_ACTIVE_LOW>;
+   };
+};
+
+ {
+   power-supply = <_regulator>;
+};
+
+_alert0 {
+   temperature = <65000>;
+};
+
+_alert1 {
+   temperature