On Wed, Sep 10, 2014 at 03:54:59PM +0300, Khoronzhuk, Ivan wrote: > From: Murali Karicheri <m-kariche...@ti.com> > > This patch implements a workaround to fix DDR3 memory issue. > The code for workaround detects PGSR0 errors and then preps for > and executes a software-controlled hard reset.In board_early_init, > where logic has been added to identify whether or not the previous > reset was a PORz. PLL initialization is skipped in the case of a > software-controlled hard reset. > > Signed-off-by: Murali Karicheri <m-kariche...@ti.com> > Signed-off-by: Keegan Garcia <kgar...@ti.com> > Signed-off-by: Ivan Khoronzhuk <ivan.khoronz...@ti.com>
Applied to u-boot-ti/master, thanks! -- Tom
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