Re: [U-Boot] [U-Boot, V3, PATCH 3/3] mips: fix erros on registers macros of pll-ddr-config1-nfrac for QCA956X

2019-03-07 Thread Daniel Schwierzeck 
Am Do., 7. März 2019 um 02:31 Uhr schrieb :
>
> From: Rosy Song 
>
>  See details in chapter 8.6.2 and 8.6.4 (page 140-141) of qca9563 datasheet,
>
>NFRAC[17:0]
>
>  So the mask of [17:5] is 0x1fff not 0x3fff.
>
> Signed-off-by: Rosy Song 
>
> Changes for v2-v3:
>- add more information for this commit
> ---
>  arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)

Reviewed-by: Daniel Schwierzeck 
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[U-Boot] [U-Boot, V3, PATCH 3/3] mips: fix erros on registers macros of pll-ddr-config1-nfrac for QCA956X

2019-03-06 Thread rosysong 
From: Rosy Song 

 See details in chapter 8.6.2 and 8.6.4 (page 140-141) of qca9563 datasheet,

   NFRAC[17:0]

 So the mask of [17:5] is 0x1fff not 0x3fff.

Signed-off-by: Rosy Song 

Changes for v2-v3:
   - add more information for this commit
---
 arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h 
b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
index 7cd16b8d81..5888f6eb28 100644
--- a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
+++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
@@ -554,7 +554,7 @@
 #define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT  0
 #define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK   0x1f
 #define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT  5
-#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK   0x3fff
+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK   0x1fff
 #define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18
 #define QCA956X_PLL_CPU_CONFIG1_NINT_MASK  0x1ff
 
@@ -566,7 +566,7 @@
 #define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT  0
 #define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK   0x1f
 #define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT  5
-#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK   0x3fff
+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK   0x1fff
 #define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18
 #define QCA956X_PLL_DDR_CONFIG1_NINT_MASK  0x1ff
 
-- 
2.17.1

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