Re: [U-Boot] [u-boot-release] [PATCH 1/2] powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers

2011-03-02 Thread Timur Tabi 
York Sun wrote:
 + switch (wrrec_mclk) { /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
 + case 9:
 + wrrec_mclk = 10;
 + break;
 + case 11:
 + wrrec_mclk = 12;
 + break;
 + case 13:
 + wrrec_mclk = 14;
 + break;
 + case 16:

15?

 + wrrec_mclk = 16;
 + break;
 + }

How about something simpler:

if (wrrec_mclk  1)
wrrec_mclk++;

-- 
Timur Tabi
Linux kernel developer at Freescale

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Re: [U-Boot] [u-boot-release] [PATCH 1/2] powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers

2011-03-02 Thread York Sun 
On Wed, 2011-03-02 at 13:31 -0600, Timur Tabi wrote:
 York Sun wrote:
  +   switch (wrrec_mclk) { /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
  +   case 9:
  +   wrrec_mclk = 10;
  +   break;
  +   case 11:
  +   wrrec_mclk = 12;
  +   break;
  +   case 13:
  +   wrrec_mclk = 14;
  +   break;
  +   case 16:
 
 15?


Nice catch. Thank you. I will submit a fixed version.

  +   wrrec_mclk = 16;
  +   break;
  +   }
 
 How about something simpler:
 
 if (wrrec_mclk  1)
   wrrec_mclk++;
 

Only 9, 11, 13, 15 need to round up.

York



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Re: [U-Boot] [u-boot-release] [PATCH 1/2] powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers

2011-03-02 Thread Timur Tabi 
York Sun wrote:
  if (wrrec_mclk  1)
 wrrec_mclk++;
  
 Only 9, 11, 13, 15 need to round up.

What are all the possible values for wrrec_mclk?

-- 
Timur Tabi
Linux kernel developer at Freescale

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Re: [U-Boot] [u-boot-release] [PATCH 1/2] powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers

2011-03-02 Thread York Sun 
On Wed, 2011-03-02 at 13:46 -0600, Timur Tabi wrote:
 York Sun wrote:
   if (wrrec_mclk  1)
wrrec_mclk++;
   
  Only 9, 11, 13, 15 need to round up.
 
 What are all the possible values for wrrec_mclk?
 

There is no limitation on register timing_cfg_1[wrrec_mclk]. It can be
any value. The limitation comes from JEDEC spec on mode register MR0.
The write recovery for autoprecharge is within the values of 5, 6, 7, 8,
10, 12, 14, 16.

York



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Re: [U-Boot] [u-boot-release] [PATCH 1/2] powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers

2011-03-02 Thread Timur Tabi 
York Sun wrote:
 On Wed, 2011-03-02 at 13:46 -0600, Timur Tabi wrote:
 York Sun wrote:
 if (wrrec_mclk  1)
   wrrec_mclk++;

 Only 9, 11, 13, 15 need to round up.

 What are all the possible values for wrrec_mclk?

 
 There is no limitation on register timing_cfg_1[wrrec_mclk]. It can be
 any value. The limitation comes from JEDEC spec on mode register MR0.
 The write recovery for autoprecharge is within the values of 5, 6, 7, 8,
 10, 12, 14, 16.

My point is that we can do something like this:

if (wrrec_mclk  8  wrrec_mclk  16  wrrec_mclk  1)
wrrec_mclk++;

But we can simplify this if I can know what all possible values are.

-- 
Timur Tabi
Linux kernel developer at Freescale

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