[U-Boot] [v2 1/4] USB: Armada100: Add UTMI PHY interface driver

2012-02-13 Thread Ajay Bhargav
This patch adds USB host controller's UTMI PHY interface driver for
Armada100 SOCs.

Signed-off-by: Ajay Bhargav ajay.bhar...@einfochips.com
---
Changes for v2:
- Fix: enable only required clock in MPMU

 arch/arm/include/asm/arch-armada100/armada100.h |8 ++
 drivers/usb/host/utmi-armada100.c   |   87 +++
 drivers/usb/host/utmi-armada100.h   |   79 
 3 files changed, 174 insertions(+), 0 deletions(-)
 create mode 100644 drivers/usb/host/utmi-armada100.c
 create mode 100644 drivers/usb/host/utmi-armada100.h

diff --git a/arch/arm/include/asm/arch-armada100/armada100.h 
b/arch/arm/include/asm/arch-armada100/armada100.h
index 0ed3a8e..70fba27 100644
--- a/arch/arm/include/asm/arch-armada100/armada100.h
+++ b/arch/arm/include/asm/arch-armada100/armada100.h
@@ -43,6 +43,14 @@
 #define SSP2_APBCLK0x01
 #define SSP2_FNCLK 0x02
 
+/* USB Clock/reset control bits */
+#define USB_SPH_AXICLK_EN  0x10
+#define USB_SPH_AXI_RST0x02
+
+/* MPMU Clocks */
+#define APB2_26M_EN(1  20)
+#define AP_26M (1  4)
+
 /* Register Base Addresses */
 #define ARMD1_DRAM_BASE0xB000
 #define ARMD1_FEC_BASE 0xC080
diff --git a/drivers/usb/host/utmi-armada100.c 
b/drivers/usb/host/utmi-armada100.c
new file mode 100644
index 000..1a4d3f2
--- /dev/null
+++ b/drivers/usb/host/utmi-armada100.c
@@ -0,0 +1,87 @@
+/*
+ * (C) Copyright 2012
+ * eInfochips Ltd. www.einfochips.com
+ * Written-by: Ajay Bhargav ajay.bhar...@einfochips.com
+ *
+ * (C) Copyright 2009
+ * Marvell Semiconductor www.marvell.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include common.h
+#include asm/io.h
+#include usb.h
+#include asm/arch/cpu.h
+#include asm/arch/armada100.h
+#include utmi-armada100.h
+
+static void utmi_phy_init(void)
+{
+   struct armd1usb_phy_reg *phy_regs =
+   (struct armd1usb_phy_reg *)UTMI_PHY_BASE;
+
+   setbits_le32(phy_regs-utmi_ctrl, INPKT_DELAY_SOF | PLL_PWR_UP);
+   udelay(1000);
+   setbits_le32(phy_regs-utmi_ctrl, PHY_PWR_UP);
+
+   clrbits_le32(phy_regs-utmi_pll, PLL_FBDIV_MASK | PLL_REFDIV_MASK);
+   setbits_le32(phy_regs-utmi_pll, N_DIVIDER  PLL_FBDIV | M_DIVIDER);
+
+   setbits_le32(phy_regs-utmi_tx, PHSEL_VAL  CK60_PHSEL);
+
+   /* Calibrate pll */
+   while ((readl(phy_regs-utmi_pll)  PLL_READY) == 0)
+   ;
+
+   udelay(200);
+   setbits_le32(phy_regs-utmi_pll, VCOCAL_START);
+   udelay(400);
+   clrbits_le32(phy_regs-utmi_pll, VCOCAL_START);
+
+   udelay(200);
+   setbits_le32(phy_regs-utmi_tx, RCAL_START);
+   udelay(400);
+   clrbits_le32(phy_regs-utmi_tx, RCAL_START);
+
+   while ((readl(phy_regs-utmi_pll)  PLL_READY) == 0)
+   ;
+}
+
+/*
+ * Initialize USB host controller's UTMI Physical interface
+ */
+void utmi_init(void)
+{
+   struct armd1mpmu_registers *mpmu_regs =
+   (struct armd1mpmu_registers *)ARMD1_MPMU_BASE;
+
+   struct armd1apmu_registers *apmu_regs =
+   (struct armd1apmu_registers *)ARMD1_APMU_BASE;
+
+   /* Turn on 26Mhz ref clock for UTMI PLL */
+   setbits_le32(mpmu_regs-acgr, APB2_26M_EN | AP_26M);
+
+   /* USB Clock reset */
+   writel(USB_SPH_AXICLK_EN, apmu_regs-usbcrc);
+   writel(USB_SPH_AXICLK_EN | USB_SPH_AXI_RST, apmu_regs-usbcrc);
+
+   /* Initialize UTMI transceiver */
+   utmi_phy_init();
+}
diff --git a/drivers/usb/host/utmi-armada100.h 
b/drivers/usb/host/utmi-armada100.h
new file mode 100644
index 000..dd0ccdb
--- /dev/null
+++ b/drivers/usb/host/utmi-armada100.h
@@ -0,0 +1,79 @@
+/*
+ * (C) Copyright 2012
+ * eInfochips Ltd. www.einfochips.com
+ * Written-by: Ajay Bhargav ajay.bhar...@einfochips.com
+ *
+ * (C) Copyright 2009
+ * Marvell Semiconductor www.marvell.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your 

Re: [U-Boot] [v2 1/4] USB: Armada100: Add UTMI PHY interface driver

2012-02-13 Thread Marek Vasut
 This patch adds USB host controller's UTMI PHY interface driver for
 Armada100 SOCs.
 
 Signed-off-by: Ajay Bhargav ajay.bhar...@einfochips.com
 ---
 Changes for v2:
   - Fix: enable only required clock in MPMU
 
  arch/arm/include/asm/arch-armada100/armada100.h |8 ++
  drivers/usb/host/utmi-armada100.c   |   87
 +++ drivers/usb/host/utmi-armada100.h   | 
  79  3 files changed, 174 insertions(+), 0
 deletions(-)
  create mode 100644 drivers/usb/host/utmi-armada100.c
  create mode 100644 drivers/usb/host/utmi-armada100.h
 
 diff --git a/arch/arm/include/asm/arch-armada100/armada100.h
 b/arch/arm/include/asm/arch-armada100/armada100.h index 0ed3a8e..70fba27
 100644
 --- a/arch/arm/include/asm/arch-armada100/armada100.h
 +++ b/arch/arm/include/asm/arch-armada100/armada100.h
 @@ -43,6 +43,14 @@
  #define SSP2_APBCLK  0x01
  #define SSP2_FNCLK   0x02
 
 +/* USB Clock/reset control bits */
 +#define USB_SPH_AXICLK_EN0x10
 +#define USB_SPH_AXI_RST  0x02
 +
 +/* MPMU Clocks */
 +#define APB2_26M_EN  (1  20)
 +#define AP_26M   (1  4)
 +
  /* Register Base Addresses */
  #define ARMD1_DRAM_BASE  0xB000
  #define ARMD1_FEC_BASE   0xC080
 diff --git a/drivers/usb/host/utmi-armada100.c
 b/drivers/usb/host/utmi-armada100.c new file mode 100644
 index 000..1a4d3f2
 --- /dev/null
 +++ b/drivers/usb/host/utmi-armada100.c
 @@ -0,0 +1,87 @@
 +/*
 + * (C) Copyright 2012
 + * eInfochips Ltd. www.einfochips.com
 + * Written-by: Ajay Bhargav ajay.bhar...@einfochips.com
 + *
 + * (C) Copyright 2009
 + * Marvell Semiconductor www.marvell.com
 + *
 + * See file CREDITS for list of people who contributed to this
 + * project.
 + *
 + * This program is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU General Public License as
 + * published by the Free Software Foundation; either version 2 of
 + * the License, or (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 + * GNU General Public License for more details.
 + *
 + * You should have received a copy of the GNU General Public License
 + * along with this program; if not, write to the Free Software
 + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 + * MA 02110-1301 USA
 + */
 +
 +#include common.h
 +#include asm/io.h
 +#include usb.h
 +#include asm/arch/cpu.h
 +#include asm/arch/armada100.h
 +#include utmi-armada100.h
 +
 +static void utmi_phy_init(void)
 +{
 + struct armd1usb_phy_reg *phy_regs =
 + (struct armd1usb_phy_reg *)UTMI_PHY_BASE;
 +
 + setbits_le32(phy_regs-utmi_ctrl, INPKT_DELAY_SOF | PLL_PWR_UP);
 + udelay(1000);
 + setbits_le32(phy_regs-utmi_ctrl, PHY_PWR_UP);
 +
 + clrbits_le32(phy_regs-utmi_pll, PLL_FBDIV_MASK | PLL_REFDIV_MASK);
 + setbits_le32(phy_regs-utmi_pll, N_DIVIDER  PLL_FBDIV | M_DIVIDER);
 +
 + setbits_le32(phy_regs-utmi_tx, PHSEL_VAL  CK60_PHSEL);
 +
 + /* Calibrate pll */
 + while ((readl(phy_regs-utmi_pll)  PLL_READY) == 0)
 + ;

No endless loops please.

 +
 + udelay(200);
 + setbits_le32(phy_regs-utmi_pll, VCOCAL_START);
 + udelay(400);
 + clrbits_le32(phy_regs-utmi_pll, VCOCAL_START);
 +
 + udelay(200);
 + setbits_le32(phy_regs-utmi_tx, RCAL_START);
 + udelay(400);
 + clrbits_le32(phy_regs-utmi_tx, RCAL_START);
 +
 + while ((readl(phy_regs-utmi_pll)  PLL_READY) == 0)
 + ;
 +}

DTTO

M
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Re: [U-Boot] [v2 1/4] USB: Armada100: Add UTMI PHY interface driver

2012-02-13 Thread Ajay Bhargav

On Monday 13 February 2012 02:32 PM, Marek Vasut wrote:

+   /* Calibrate pll */
+   while ((readl(phy_regs-utmi_pll)  PLL_READY) == 0)
+   ;

No endless loops please.


missed it somehow... :) will fix

Regards,
Ajay Bhargav
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