Re: [U-Boot] P4080 target with more than 1 dimm on each ddr3 controller?

2011-09-07 Thread York Sun
Robert,

On Tue, 2011-09-06 at 13:34 -0400, Robert Sciuk wrote:
 Has anyone had any experience with a P4080 target which has more than 1
 sodimm slot on each controller?  I'm having some difficulties accessing
 memory on the higher order dimms, but the SPD data are correctly
 enumerated by the FSL ddr3 code.  
 
 Just wondering if this is a known problem before I dig in ...
 ___

I am not aware of any problem of doing this. You may want to double
check the dynamic ODT. I have not verified it with two-slot system. You
can pick up the interactive ddr debugging patch
http://patchwork.ozlabs.org/patch/111818/. You will be able to fine tune
all parameters without reflashing the board. Please post any finding you
have.

York



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[U-Boot] P4080 target with more than 1 dimm on each ddr3 controller?

2011-09-06 Thread Robert Sciuk
Has anyone had any experience with a P4080 target which has more than 1
sodimm slot on each controller?  I'm having some difficulties accessing
memory on the higher order dimms, but the SPD data are correctly
enumerated by the FSL ddr3 code.  

Just wondering if this is a known problem before I dig in ...
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