Re: [U-Boot] socfpga: socdk and socrates share SPI flash config, move it to shared place

[Marek Vasut]

On Monday, April 20, 2015 at 02:16:02 PM, Pavel Machek wrote:
 Both Socrates and SocDK share same QSPI and SPI flash
 configuration. Move the common configuration into common place.
 
 Signed-off-by: Pavel Machek pa...@denx.de

Is my understanding correct that now all SoCFPGA CV boards will be forced
to have this SPI flash ? I believe this is incorrect.

Best regards,
Marek Vasut
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Re: [U-Boot] socfpga: socdk and socrates share SPI flash config, move it to shared place

[Stefan Roese]

On 20.04.2015 14:39, Marek Vasut wrote:

On Monday, April 20, 2015 at 02:16:02 PM, Pavel Machek wrote:

Both Socrates and SocDK share same QSPI and SPI flash
configuration. Move the common configuration into common place.

Signed-off-by: Pavel Machek pa...@denx.de


Is my understanding correct that now all SoCFPGA CV boards will be forced
to have this SPI flash ? I believe this is incorrect.


Yes. Defining such a SPI flash is board specific and shouldn't be moved 
to the common dtsi file.


Thanks,
Stefan

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[U-Boot] socfpga: socdk and socrates share SPI flash config, move it to shared place

[Pavel Machek]

Both Socrates and SocDK share same QSPI and SPI flash
configuration. Move the common configuration into common place.

Signed-off-by: Pavel Machek pa...@denx.de

diff --git a/arch/arm/dts/socfpga_cyclone5.dtsi 
b/arch/arm/dts/socfpga_cyclone5.dtsi
index 234a901..c40ade5 100644
--- a/arch/arm/dts/socfpga_cyclone5.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5.dtsi
@@ -37,4 +37,30 @@
cpu1-start-addr = 0xffd080c4;
};
};
+
+   aliases {
+   spi0 = /spi@ff705000; /* QSPI */
+   spi1 = /spi@fff0;
+   spi2 = /spi@fff01000;
+   };
+};
+
+qspi {
+   status = okay;
+
+   flash0: n25q00@0 {
+   #address-cells = 1;
+   #size-cells = 1;
+   compatible = n25q00;
+   reg = 0;  /* chip select */
+   spi-max-frequency = 5000;
+   m25p,fast-read;
+   page-size = 256;
+   block-size = 16; /* 2^16, 64KB */
+   read-delay = 4;  /* delay value in read data capture register 
*/
+   tshsl-ns = 50;
+   tsd2d-ns = 50;
+   tchsh-ns = 4;
+   tslch-ns = 4;
+   };
 };
diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts 
b/arch/arm/dts/socfpga_cyclone5_socrates.dts
index ea30483..2a64b3c 100644
--- a/arch/arm/dts/socfpga_cyclone5_socrates.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts
@@ -14,12 +14,6 @@
bootargs = console=ttyS0,115200;
};
 
-   aliases {
-   spi0 = /spi@ff705000; /* QSPI */
-   spi1 = /spi@fff0;
-   spi2 = /spi@fff01000;
-   };
-
memory {
name = memory;
device_type = memory;
@@ -44,22 +38,3 @@
status = okay;
 };
 
-qspi {
-   status = okay;
-
-   flash0: n25q00@0 {
-   #address-cells = 1;
-   #size-cells = 1;
-   compatible = n25q00;
-   reg = 0;  /* chip select */
-   spi-max-frequency = 5000;
-   m25p,fast-read;
-   page-size = 256;
-   block-size = 16; /* 2^16, 64KB */
-   read-delay = 4;  /* delay value in read data capture register 
*/
-   tshsl-ns = 50;
-   tsd2d-ns = 50;
-   tchsh-ns = 4;
-   tslch-ns = 4;
-   };
-};

-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) 
http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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