Re: [U-Boot] the mips cache code question ?
On Dec 1, 2010 12:26 AM, 奥刘 happyo...@gmail.com wrote: In the file .\cpu\mips\cache.s , i found some code confounded . line 152 to line 156 : cache_op Index_Store_Tag_I t0 PTR_ADDU t0, a2 bne t0, t1, 1b /* fill once, so data field parity is correct */ PTR_LI t0, INDEX_BASE the code 'PTR_LI t0, INDEX_BASE' is in the branch delay slot , so this instruction will be implement every branch cycle. Is it right ? Then the cache operation logic seems wrong . From a quick glance I think the code is OK. I would suggest disassembling the executable code to make sure of what the assembler did. The answer depends on what mode the assembler is in. For MIPS assembler there is a 'reorder mode' where the assembler will fill in the branch delay slot for you or place a nop if necessary, and the next instruction in the source is really the one after the delay slot, or there is noreorder mode where the next instruction after the branch is what is put in the delay slot. Normally the assembler runs in reorder mode, and you use a '.set reorder' and '.set noreorder' to switch between them. Noreorder mode is commonly used in code that requires precise control of where instructions get executed (cache tlb handling) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] the mips cache code question ?
hello, On Wed, Dec 1, 2010 at 10:27 AM, Andrew Dyer amd...@gmail.com wrote: On Dec 1, 2010 12:26 AM, 奥刘 happyo...@gmail.com wrote: In the file .\cpu\mips\cache.s , i found some code confounded . line 152 to line 156 : cache_op Index_Store_Tag_I t0 PTR_ADDU t0, a2 bne t0, t1, 1b /* fill once, so data field parity is correct */ PTR_LI t0, INDEX_BASE the code 'PTR_LI t0, INDEX_BASE' is in the branch delay slot , so this instruction will be implement every branch cycle. Is it right ? Then the cache operation logic seems wrong . It would seem. a NOP is needed in this case. seem every branch is incorrect. a disassembly would be best way to confirm. assembler might insert it for us. From a quick glance I think the code is OK. I would suggest disassembling the executable code to make sure of what the assembler did. The answer depends on what mode the assembler is in. For MIPS assembler there is a 'reorder mode' where the assembler will fill in the branch delay slot for you or place a nop if necessary, and the next instruction in the source is really the one after the delay slot, or there is noreorder mode where the next instruction after the branch is what is put in the delay slot. Normally the assembler runs in reorder mode, and you use a '.set reorder' and '.set noreorder' to switch between them. Noreorder mode is commonly used in code that requires precise control of where instructions get executed (cache tlb handling) the file does specify noreorder! This is interesting, and of course I will be looking at a disassembly of my u-boot later, it is not available to me now. Tho, the cache's work, and have seen nothing that makes it seem otherwise.. -- Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] the mips cache code question ?
Sorry for the two successive posts, I looked at the disassembly... On Wed, Dec 1, 2010 at 1:26 AM, 奥刘 happyo...@gmail.com wrote: Dear All: Recently , i have build a embedded environment with Uboot . And My Chip is adm5120 , mips4kc code. In the file .\cpu\mips\cache.s , i found some code confounded . line 152 to line 156 : cache_op Index_Store_Tag_I t0 PTR_ADDU t0, a2 bne t0, t1, 1b /* fill once, so data field parity is correct */ PTR_LI t0, INDEX_BASE the code 'PTR_LI t0, INDEX_BASE' is in the branch delay slot , so this instruction will be implement every branch cycle. Is it right ? Then the cache operation logic seems wrong . The assembler does insert a 'NOP' instruction in the branch delay slot, even with .set noreorder, so this is OK: 810005a8: bd14cache 0x14,0(t0) 810005ac: 01064021addut0,t0,a2 810005b0: 1509fffdbne t0,t1,810005a8 mips_init_icache+0x28 810005b4: nop -- Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] the mips cache code question ?
Dear All: Recently , i have build a embedded environment with Uboot . And My Chip is adm5120 , mips4kc code. In the file .\cpu\mips\cache.s , i found some code confounded . line 152 to line 156 : cache_op Index_Store_Tag_I t0 PTR_ADDU t0, a2 bne t0, t1, 1b /* fill once, so data field parity is correct */ PTR_LI t0, INDEX_BASE the code 'PTR_LI t0, INDEX_BASE' is in the branch delay slot , so this instruction will be implement every branch cycle. Is it right ? Then the cache operation logic seems wrong . ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
