The System Control Unit (SCU) controller of Aspeed
SoCs provides the reset control for each peripheral.
This patch refactors the reset method to leverage
the SCU reset control. Thus the driver dependency
on watchdog including dedicated WDT API and reset
flag encoding can be eliminated.
The Kconfig description is also updated accordingly.
Signed-off-by: Chia-Wei, Wang
Reviewed-by: Ryan Chen
---
arch/arm/dts/ast2500-u-boot.dtsi | 7 +-
drivers/reset/Kconfig | 9 +--
drivers/reset/ast2500-reset.c | 97 ---
include/dt-bindings/reset/ast2500-reset.h | 73 +
4 files changed, 97 insertions(+), 89 deletions(-)
diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi
index 51a5244766..ea60e4c8db 100644
--- a/arch/arm/dts/ast2500-u-boot.dtsi
+++ b/arch/arm/dts/ast2500-u-boot.dtsi
@@ -16,7 +16,6 @@
rst: reset-controller {
u-boot,dm-pre-reloc;
compatible = "aspeed,ast2500-reset";
- aspeed,wdt = <>;
#reset-cells = <1>;
};
@@ -27,7 +26,7 @@
0x1e6e0200 0x1d4 >;
#reset-cells = <1>;
clocks = < ASPEED_CLK_MPLL>;
- resets = < AST_RESET_SDRAM>;
+ resets = < ASPEED_RESET_SDRAM>;
};
ahb {
@@ -41,7 +40,7 @@
reg = <0x1e740100>;
#reset-cells = <1>;
clocks = < ASPEED_CLK_SDIO>;
- resets = < AST_RESET_SDIO>;
+ resets = < ASPEED_RESET_SDIO>;
};
sdhci1: sdhci@1e740200 {
@@ -49,7 +48,7 @@
reg = <0x1e740200>;
#reset-cells = <1>;
clocks = < ASPEED_CLK_SDIO>;
- resets = < AST_RESET_SDIO>;
+ resets = < ASPEED_RESET_SDIO>;
};
};
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index b60e11f98b..8b243fdcc6 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -74,13 +74,12 @@ config RESET_UNIPHIER
config AST2500_RESET
bool "Reset controller driver for AST2500 SoCs"
- depends on DM_RESET && WDT_ASPEED
+ depends on DM_RESET
default y if ASPEED_AST2500
help
- Support for reset controller on AST2500 SoC. This controller uses
- watchdog to reset different peripherals and thus only supports
- resets that are supported by watchdog. The main limitation though
- is that some reset signals, like I2C or MISC reset multiple devices.
+ Support for reset controller on AST2500 SoC.
+ Say Y if you want to control reset signals of different peripherals
+ through System Control Unit (SCU).
config RESET_ROCKCHIP
bool "Reset controller driver for Rockchip SoCs"
diff --git a/drivers/reset/ast2500-reset.c b/drivers/reset/ast2500-reset.c
index beb5cd8fa8..e7b5c7deca 100644
--- a/drivers/reset/ast2500-reset.c
+++ b/drivers/reset/ast2500-reset.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2017 Google, Inc
+ * Copyright 2020 ASPEED Technology Inc.
*/
#include
@@ -9,28 +10,26 @@
#include
#include
#include
-#include
+#include
#include
#include
-#include
struct ast2500_reset_priv {
- /* WDT used to perform resets. */
- struct udevice *wdt;
struct ast2500_scu *scu;
};
-static int ast2500_ofdata_to_platdata(struct udevice *dev)
+static int ast2500_reset_request(struct reset_ctl *reset_ctl)
{
- struct ast2500_reset_priv *priv = dev_get_priv(dev);
- int ret;
+ debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+ reset_ctl->dev, reset_ctl->id);
- ret = uclass_get_device_by_phandle(UCLASS_WDT, dev, "aspeed,wdt",
- >wdt);
- if (ret) {
- debug("%s: can't find WDT for reset controller", __func__);
- return ret;
- }
+ return 0;
+}
+
+static int ast2500_reset_free(struct reset_ctl *reset_ctl)
+{
+ debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+ reset_ctl->dev, reset_ctl->id);
return 0;
}
@@ -38,47 +37,52 @@ static int ast2500_ofdata_to_platdata(struct udevice *dev)
static int ast2500_reset_assert(struct reset_ctl *reset_ctl)
{
struct ast2500_reset_priv *priv = dev_get_priv(reset_ctl->dev);
- u32 reset_mode, reset_mask;
- bool reset_sdram;
- int ret;
-
- /*
-* To reset SDRAM, a specifal flag in SYSRESET register
-* needs to be enabled first
-*/
- reset_mode = ast_reset_mode_from_flags(reset_ctl->id);
- reset_mask =
