Re: [PATCH] mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON to control card clock output
On Thu, Feb 4, 2021 at 11:23 PM Bough Chen wrote:
>
> > -Original Message-
> > From: ZHIZHIKIN Andrey [mailto:andrey.zhizhi...@leica-geosystems.com]
> > Sent: 2021年2月1日 19:41
> > To: Bough Chen ; Peng Fan ;
> > u-boot@lists.denx.de
> > Cc: dl-uboot-imx ; thar...@gateworks.com
> > Subject: RE: [PATCH] mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON
> > to control card clock output
> >
> > Hello Haibo,
> >
> > > -Original Message-
> > > From: Bough Chen
> > > Sent: Monday, February 1, 2021 11:10 AM
> > > To: ZHIZHIKIN Andrey ; Peng Fan
> > > ; u-boot@lists.denx.de
> > > Cc: dl-uboot-imx ; thar...@gateworks.com
> > > Subject: RE: [PATCH] mmc: fsl_esdhc_imx: use
> > VENDORSPEC_FRC_SDCLK_ON
> > > to control card clock output
> > >
> > > > -Original Message-
> > > > From: ZHIZHIKIN Andrey
> > > > [mailto:andrey.zhizhi...@leica-geosystems.com]
> > > > Sent: 2021年2月1日 17:52
> > > > To: Bough Chen ; Peng Fan ;
> > > > u-boot@lists.denx.de
> > > > Cc: dl-uboot-imx ; thar...@gateworks.com
> > > > Subject: RE: [PATCH] mmc: fsl_esdhc_imx: use
> > VENDORSPEC_FRC_SDCLK_ON
> > > > to control card clock output
> > > >
> > > > Hello Haibo,
> > > >
> > > > > -Original Message-
> > > > > From: haibo.c...@nxp.com
> > > > > Sent: Wednesday, January 27, 2021 11:47 AM
> > > > > To: peng@nxp.com; u-boot@lists.denx.de
> > > > > Cc: haibo.c...@nxp.com; uboot-...@nxp.com;
> > thar...@gateworks.com;
> > > > > ZHIZHIKIN Andrey
> > > > > Subject: [PATCH] mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON
> > > > > to control card clock output
> > > > >
> > > > > From: Haibo Chen
> > > > >
> > > > > For FSL_USDHC, it do not implement
> > > > VENDORSPEC_CKEN/PEREN/HCKEN/IPGEN,
> > > > > these are reserved bits. Instead, use VENDORSPEC_FRC_SDCLK_ON to
> > > > > gate on/off the card clock output.
> > > > >
> > > > > After commit b5874b552ffa ("mmc: fsl_esdhc_imx: add wait_dat0()
> > > > > support"), we meet SD3.0 card can't work at UHS mode,
> > > > > mmc_switch_voltage() fail because the second mmc_wait_dat0 return
> > > > > -ETIMEDOUT. According to SD spec, during voltage switch, need to
> > > > > gate off/on the card clock. If not set the FRC_SDCLK_ON, after
> > > > > CMD11, hardware will gate off the card clock automatically, so
> > > > > card do not detect the clock off/on behavior, so will draw the
> > > > > data0 line low until next
> > > > command.
> > > > >
> > > > > Fixes: b5874b552ffa ("mmc: fsl_esdhc_imx: add wait_dat0()
> > > > > support")
> > > >
> > > > This patch does not fix the switch of uSDHC to 1v8...
> > > >
> > > > I've applied it locally on the imx8mmevk, and had following log
> > > > during the boot when tried to query SD Card info:
> > > > ---
> > > > U-Boot SPL 2021.01-01004-gb852007333 (Feb 01 2021 - 09:45:42 +0100)
> > > > Normal Boot
> > > > WDT: Started with servicing (60s timeout)
> > > > Trying to boot from MMC1
> > > > NOTICE: BL31: v2.2(release):rel_imx_5.4.70_2.3.0-0-gf1d7187f2
> > > > NOTICE: BL31: Built : 22:29:05, Jan 17 2021
> > > >
> > > >
> > > > U-Boot 2021.01-01004-gb852007333 (Feb 01 2021 - 09:45:42 +0100)
> > > >
> > > > CPU: Freescale i.MX8MMQ rev1.0 at 1200 MHz
> > > > Reset cause: POR
> > > > Model: FSL i.MX8MM EVK board
> > > > DRAM: 2 GiB
> > > > WDT: Started with servicing (60s timeout)
> > > > MMC: FSL_SDHC: 1, FSL_SDHC: 2
> > > > Loading Environment from MMC... Run CMD11 1.8V switch Card did not
> > > > respond to voltage select! : -110
> > >
> > > This do not align with my test result. Can you help identify which
> > > function first return the timeout on your side?
> >
> > I would have a look at the exact function, but it seems to me that it would
> > be
> > wait_dat0() since if I revert the patch introducing it - high speed mode
> > switch is
> > not timing out.
> >
> > > Or can you t
RE: [PATCH] mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON to control card clock output
Hello Haibo,
> -Original Message-
> From: Bough Chen
> Sent: Friday, February 5, 2021 8:24 AM
> To: ZHIZHIKIN Andrey ; Peng Fan
> ; u-boot@lists.denx.de
> Cc: dl-uboot-imx ; thar...@gateworks.com
> Subject: RE: [PATCH] mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON to
> control card clock output
>
> > -Original Message-
> > From: ZHIZHIKIN Andrey [mailto:andrey.zhizhi...@leica-geosystems.com]
> > Sent: 2021年2月1日 19:41
> > To: Bough Chen ; Peng Fan ;
> > u-boot@lists.denx.de
> > Cc: dl-uboot-imx ; thar...@gateworks.com
> > Subject: RE: [PATCH] mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON
> > to control card clock output
> >
> > Hello Haibo,
> >
> > > -Original Message-
> > > From: Bough Chen
> > > Sent: Monday, February 1, 2021 11:10 AM
> > > To: ZHIZHIKIN Andrey ; Peng
> > > Fan ; u-boot@lists.denx.de
> > > Cc: dl-uboot-imx ; thar...@gateworks.com
> > > Subject: RE: [PATCH] mmc: fsl_esdhc_imx: use
> > VENDORSPEC_FRC_SDCLK_ON
> > > to control card clock output
> > >
> > > > -Original Message-
> > > > From: ZHIZHIKIN Andrey
> > > > [mailto:andrey.zhizhi...@leica-geosystems.com]
> > > > Sent: 2021年2月1日 17:52
> > > > To: Bough Chen ; Peng Fan ;
> > > > u-boot@lists.denx.de
> > > > Cc: dl-uboot-imx ; thar...@gateworks.com
> > > > Subject: RE: [PATCH] mmc: fsl_esdhc_imx: use
> > VENDORSPEC_FRC_SDCLK_ON
> > > > to control card clock output
> > > >
> > > > Hello Haibo,
> > > >
> > > > > -Original Message-
> > > > > From: haibo.c...@nxp.com
> > > > > Sent: Wednesday, January 27, 2021 11:47 AM
> > > > > To: peng@nxp.com; u-boot@lists.denx.de
> > > > > Cc: haibo.c...@nxp.com; uboot-...@nxp.com;
> > thar...@gateworks.com;
> > > > > ZHIZHIKIN Andrey
> > > > > Subject: [PATCH] mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON
> > > > > to control card clock output
> > > > >
> > > > > From: Haibo Chen
> > > > >
> > > > > For FSL_USDHC, it do not implement
> > > > VENDORSPEC_CKEN/PEREN/HCKEN/IPGEN,
> > > > > these are reserved bits. Instead, use VENDORSPEC_FRC_SDCLK_ON to
> > > > > gate on/off the card clock output.
> > > > >
> > > > > After commit b5874b552ffa ("mmc: fsl_esdhc_imx: add wait_dat0()
> > > > > support"), we meet SD3.0 card can't work at UHS mode,
> > > > > mmc_switch_voltage() fail because the second mmc_wait_dat0
> > > > > return -ETIMEDOUT. According to SD spec, during voltage switch,
> > > > > need to gate off/on the card clock. If not set the FRC_SDCLK_ON,
> > > > > after CMD11, hardware will gate off the card clock
> > > > > automatically, so card do not detect the clock off/on behavior,
> > > > > so will draw the
> > > > > data0 line low until next
> > > > command.
> > > > >
> > > > > Fixes: b5874b552ffa ("mmc: fsl_esdhc_imx: add wait_dat0()
> > > > > support")
> > > >
> > > > This patch does not fix the switch of uSDHC to 1v8...
> > > >
> > > > I've applied it locally on the imx8mmevk, and had following log
> > > > during the boot when tried to query SD Card info:
> > > > ---
> > > > U-Boot SPL 2021.01-01004-gb852007333 (Feb 01 2021 - 09:45:42
> > > > +0100) Normal Boot
> > > > WDT: Started with servicing (60s timeout)
> > > > Trying to boot from MMC1
> > > > NOTICE: BL31: v2.2(release):rel_imx_5.4.70_2.3.0-0-gf1d7187f2
> > > > NOTICE: BL31: Built : 22:29:05, Jan 17 2021
> > > >
> > > >
> > > > U-Boot 2021.01-01004-gb852007333 (Feb 01 2021 - 09:45:42 +0100)
> > > >
> > > > CPU: Freescale i.MX8MMQ rev1.0 at 1200 MHz
> > > > Reset cause: POR
> > > > Model: FSL i.MX8MM EVK board
> > > > DRAM: 2 GiB
> > > > WDT: Started with servicing (60s timeout)
> > > > MMC: FSL_SDHC: 1, FSL_SDHC: 2
> > > > Loading Environment from MMC... Run CMD11 1.8V switch Card did not
> > > > respond to voltage select! : -110
> > >
> > > This do not align with my test result. Can you help identify which
> > > function first r
Re: [PATCH] mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON to control card clock output
Hi all,
On 2/5/21 4:23 PM, Bough Chen wrote:
>> -Original Message-
>> From: ZHIZHIKIN Andrey [mailto:andrey.zhizhi...@leica-geosystems.com]
>> Sent: 2021年2月1日 19:41
>> To: Bough Chen ; Peng Fan ;
>> u-boot@lists.denx.de
>> Cc: dl-uboot-imx ; thar...@gateworks.com
>> Subject: RE: [PATCH] mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON
>> to control card clock output
>>
>> Hello Haibo,
>>
>>> -Original Message-
>>> From: Bough Chen
>>> Sent: Monday, February 1, 2021 11:10 AM
>>> To: ZHIZHIKIN Andrey ; Peng Fan
>>> ; u-boot@lists.denx.de
>>> Cc: dl-uboot-imx ; thar...@gateworks.com
>>> Subject: RE: [PATCH] mmc: fsl_esdhc_imx: use
>> VENDORSPEC_FRC_SDCLK_ON
>>> to control card clock output
>>>
>>>> -Original Message-
>>>> From: ZHIZHIKIN Andrey
>>>> [mailto:andrey.zhizhi...@leica-geosystems.com]
>>>> Sent: 2021年2月1日 17:52
>>>> To: Bough Chen ; Peng Fan ;
>>>> u-boot@lists.denx.de
>>>> Cc: dl-uboot-imx ; thar...@gateworks.com
>>>> Subject: RE: [PATCH] mmc: fsl_esdhc_imx: use
>> VENDORSPEC_FRC_SDCLK_ON
>>>> to control card clock output
>>>>
>>>> Hello Haibo,
>>>>
>>>>> -Original Message-
>>>>> From: haibo.c...@nxp.com
>>>>> Sent: Wednesday, January 27, 2021 11:47 AM
>>>>> To: peng@nxp.com; u-boot@lists.denx.de
>>>>> Cc: haibo.c...@nxp.com; uboot-...@nxp.com;
>> thar...@gateworks.com;
>>>>> ZHIZHIKIN Andrey
>>>>> Subject: [PATCH] mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON
>>>>> to control card clock output
>>>>>
>>>>> From: Haibo Chen
>>>>>
>>>>> For FSL_USDHC, it do not implement
>>>> VENDORSPEC_CKEN/PEREN/HCKEN/IPGEN,
>>>>> these are reserved bits. Instead, use VENDORSPEC_FRC_SDCLK_ON to
>>>>> gate on/off the card clock output.
>>>>>
>>>>> After commit b5874b552ffa ("mmc: fsl_esdhc_imx: add wait_dat0()
>>>>> support"), we meet SD3.0 card can't work at UHS mode,
>>>>> mmc_switch_voltage() fail because the second mmc_wait_dat0 return
>>>>> -ETIMEDOUT. According to SD spec, during voltage switch, need to
>>>>> gate off/on the card clock. If not set the FRC_SDCLK_ON, after
>>>>> CMD11, hardware will gate off the card clock automatically, so
>>>>> card do not detect the clock off/on behavior, so will draw the
>>>>> data0 line low until next
>>>> command.
>>>>>
>>>>> Fixes: b5874b552ffa ("mmc: fsl_esdhc_imx: add wait_dat0()
>>>>> support")
>>>>
>>>> This patch does not fix the switch of uSDHC to 1v8...
>>>>
>>>> I've applied it locally on the imx8mmevk, and had following log
>>>> during the boot when tried to query SD Card info:
>>>> ---
>>>> U-Boot SPL 2021.01-01004-gb852007333 (Feb 01 2021 - 09:45:42 +0100)
>>>> Normal Boot
>>>> WDT: Started with servicing (60s timeout)
>>>> Trying to boot from MMC1
>>>> NOTICE: BL31: v2.2(release):rel_imx_5.4.70_2.3.0-0-gf1d7187f2
>>>> NOTICE: BL31: Built : 22:29:05, Jan 17 2021
>>>>
>>>>
>>>> U-Boot 2021.01-01004-gb852007333 (Feb 01 2021 - 09:45:42 +0100)
>>>>
>>>> CPU: Freescale i.MX8MMQ rev1.0 at 1200 MHz
>>>> Reset cause: POR
>>>> Model: FSL i.MX8MM EVK board
>>>> DRAM: 2 GiB
>>>> WDT: Started with servicing (60s timeout)
>>>> MMC: FSL_SDHC: 1, FSL_SDHC: 2
>>>> Loading Environment from MMC... Run CMD11 1.8V switch Card did not
>>>> respond to voltage select! : -110
>>>
>>> This do not align with my test result. Can you help identify which
>>> function first return the timeout on your side?
>>
>> I would have a look at the exact function, but it seems to me that it would
>> be
>> wait_dat0() since if I revert the patch introducing it - high speed mode
>> switch is
>> not timing out.
>>
>>> Or can you try a different SD card?
>>
>> It is rather strange, it seems like it is dependent on the SD Card used.
>>
>> So far, I've tried 3 SD Cards I had on hands, one of which being operable:
>> == Working:
>> "Transce
RE: [PATCH] mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON to control card clock output
> -Original Message-
> From: ZHIZHIKIN Andrey [mailto:andrey.zhizhi...@leica-geosystems.com]
> Sent: 2021年2月1日 19:41
> To: Bough Chen ; Peng Fan ;
> u-boot@lists.denx.de
> Cc: dl-uboot-imx ; thar...@gateworks.com
> Subject: RE: [PATCH] mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON
> to control card clock output
>
> Hello Haibo,
>
> > -Original Message-
> > From: Bough Chen
> > Sent: Monday, February 1, 2021 11:10 AM
> > To: ZHIZHIKIN Andrey ; Peng Fan
> > ; u-boot@lists.denx.de
> > Cc: dl-uboot-imx ; thar...@gateworks.com
> > Subject: RE: [PATCH] mmc: fsl_esdhc_imx: use
> VENDORSPEC_FRC_SDCLK_ON
> > to control card clock output
> >
> > > -Original Message-
> > > From: ZHIZHIKIN Andrey
> > > [mailto:andrey.zhizhi...@leica-geosystems.com]
> > > Sent: 2021年2月1日 17:52
> > > To: Bough Chen ; Peng Fan ;
> > > u-boot@lists.denx.de
> > > Cc: dl-uboot-imx ; thar...@gateworks.com
> > > Subject: RE: [PATCH] mmc: fsl_esdhc_imx: use
> VENDORSPEC_FRC_SDCLK_ON
> > > to control card clock output
> > >
> > > Hello Haibo,
> > >
> > > > -Original Message-
> > > > From: haibo.c...@nxp.com
> > > > Sent: Wednesday, January 27, 2021 11:47 AM
> > > > To: peng@nxp.com; u-boot@lists.denx.de
> > > > Cc: haibo.c...@nxp.com; uboot-...@nxp.com;
> thar...@gateworks.com;
> > > > ZHIZHIKIN Andrey
> > > > Subject: [PATCH] mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON
> > > > to control card clock output
> > > >
> > > > From: Haibo Chen
> > > >
> > > > For FSL_USDHC, it do not implement
> > > VENDORSPEC_CKEN/PEREN/HCKEN/IPGEN,
> > > > these are reserved bits. Instead, use VENDORSPEC_FRC_SDCLK_ON to
> > > > gate on/off the card clock output.
> > > >
> > > > After commit b5874b552ffa ("mmc: fsl_esdhc_imx: add wait_dat0()
> > > > support"), we meet SD3.0 card can't work at UHS mode,
> > > > mmc_switch_voltage() fail because the second mmc_wait_dat0 return
> > > > -ETIMEDOUT. According to SD spec, during voltage switch, need to
> > > > gate off/on the card clock. If not set the FRC_SDCLK_ON, after
> > > > CMD11, hardware will gate off the card clock automatically, so
> > > > card do not detect the clock off/on behavior, so will draw the
> > > > data0 line low until next
> > > command.
> > > >
> > > > Fixes: b5874b552ffa ("mmc: fsl_esdhc_imx: add wait_dat0()
> > > > support")
> > >
> > > This patch does not fix the switch of uSDHC to 1v8...
> > >
> > > I've applied it locally on the imx8mmevk, and had following log
> > > during the boot when tried to query SD Card info:
> > > ---
> > > U-Boot SPL 2021.01-01004-gb852007333 (Feb 01 2021 - 09:45:42 +0100)
> > > Normal Boot
> > > WDT: Started with servicing (60s timeout)
> > > Trying to boot from MMC1
> > > NOTICE: BL31: v2.2(release):rel_imx_5.4.70_2.3.0-0-gf1d7187f2
> > > NOTICE: BL31: Built : 22:29:05, Jan 17 2021
> > >
> > >
> > > U-Boot 2021.01-01004-gb852007333 (Feb 01 2021 - 09:45:42 +0100)
> > >
> > > CPU: Freescale i.MX8MMQ rev1.0 at 1200 MHz
> > > Reset cause: POR
> > > Model: FSL i.MX8MM EVK board
> > > DRAM: 2 GiB
> > > WDT: Started with servicing (60s timeout)
> > > MMC: FSL_SDHC: 1, FSL_SDHC: 2
> > > Loading Environment from MMC... Run CMD11 1.8V switch Card did not
> > > respond to voltage select! : -110
> >
> > This do not align with my test result. Can you help identify which
> > function first return the timeout on your side?
>
> I would have a look at the exact function, but it seems to me that it would be
> wait_dat0() since if I revert the patch introducing it - high speed mode
> switch is
> not timing out.
>
> > Or can you try a different SD card?
>
> It is rather strange, it seems like it is dependent on the SD Card used.
>
> So far, I've tried 3 SD Cards I had on hands, one of which being operable:
> == Working:
> "Transcend 32GB"
> Manufacturer ID: 74
> OEM: 4a60
> Name: USDU1
>
> == Failed:
> 1. (Kingston 32GB)
> Manufacturer ID: 41
> OEM: 3432
> Name: SD32G
>
> 2. (Intenso 32 GB)
> Manufacturer ID: 9f
> OEM: 5449
> Name: 0
>
Hi Andrey,
With this patch, can you also add the fo
RE: [PATCH] mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON to control card clock output
Hello Haibo,
> -Original Message-
> From: Bough Chen
> Sent: Monday, February 1, 2021 11:10 AM
> To: ZHIZHIKIN Andrey ; Peng Fan
> ; u-boot@lists.denx.de
> Cc: dl-uboot-imx ; thar...@gateworks.com
> Subject: RE: [PATCH] mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON to
> control card clock output
>
> > -Original Message-
> > From: ZHIZHIKIN Andrey [mailto:andrey.zhizhi...@leica-geosystems.com]
> > Sent: 2021年2月1日 17:52
> > To: Bough Chen ; Peng Fan ;
> > u-boot@lists.denx.de
> > Cc: dl-uboot-imx ; thar...@gateworks.com
> > Subject: RE: [PATCH] mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON
> > to control card clock output
> >
> > Hello Haibo,
> >
> > > -Original Message-
> > > From: haibo.c...@nxp.com
> > > Sent: Wednesday, January 27, 2021 11:47 AM
> > > To: peng@nxp.com; u-boot@lists.denx.de
> > > Cc: haibo.c...@nxp.com; uboot-...@nxp.com; thar...@gateworks.com;
> > > ZHIZHIKIN Andrey
> > > Subject: [PATCH] mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON to
> > > control card clock output
> > >
> > > From: Haibo Chen
> > >
> > > For FSL_USDHC, it do not implement
> > VENDORSPEC_CKEN/PEREN/HCKEN/IPGEN,
> > > these are reserved bits. Instead, use VENDORSPEC_FRC_SDCLK_ON to
> > > gate on/off the card clock output.
> > >
> > > After commit b5874b552ffa ("mmc: fsl_esdhc_imx: add wait_dat0()
> > > support"), we meet SD3.0 card can't work at UHS mode,
> > > mmc_switch_voltage() fail because the second mmc_wait_dat0 return
> > > -ETIMEDOUT. According to SD spec, during voltage switch, need to
> > > gate off/on the card clock. If not set the FRC_SDCLK_ON, after
> > > CMD11, hardware will gate off the card clock automatically, so card
> > > do not detect the clock off/on behavior, so will draw the data0 line
> > > low until next
> > command.
> > >
> > > Fixes: b5874b552ffa ("mmc: fsl_esdhc_imx: add wait_dat0() support")
> >
> > This patch does not fix the switch of uSDHC to 1v8...
> >
> > I've applied it locally on the imx8mmevk, and had following log during
> > the boot when tried to query SD Card info:
> > ---
> > U-Boot SPL 2021.01-01004-gb852007333 (Feb 01 2021 - 09:45:42 +0100)
> > Normal Boot
> > WDT: Started with servicing (60s timeout)
> > Trying to boot from MMC1
> > NOTICE: BL31: v2.2(release):rel_imx_5.4.70_2.3.0-0-gf1d7187f2
> > NOTICE: BL31: Built : 22:29:05, Jan 17 2021
> >
> >
> > U-Boot 2021.01-01004-gb852007333 (Feb 01 2021 - 09:45:42 +0100)
> >
> > CPU: Freescale i.MX8MMQ rev1.0 at 1200 MHz
> > Reset cause: POR
> > Model: FSL i.MX8MM EVK board
> > DRAM: 2 GiB
> > WDT: Started with servicing (60s timeout)
> > MMC: FSL_SDHC: 1, FSL_SDHC: 2
> > Loading Environment from MMC... Run CMD11 1.8V switch Card did not
> > respond to voltage select! : -110
>
> This do not align with my test result. Can you help identify which function
> first
> return the timeout on your side?
I would have a look at the exact function, but it seems to me that it would be
wait_dat0()
since if I revert the patch introducing it - high speed mode switch is not
timing out.
> Or can you try a different SD card?
It is rather strange, it seems like it is dependent on the SD Card used.
So far, I've tried 3 SD Cards I had on hands, one of which being operable:
== Working:
"Transcend 32GB"
Manufacturer ID: 74
OEM: 4a60
Name: USDU1
== Failed:
1. (Kingston 32GB)
Manufacturer ID: 41
OEM: 3432
Name: SD32G
2. (Intenso 32 GB)
Manufacturer ID: 9f
OEM: 5449
Name: 0
This raises a concern that a regular off-the-shelf SD Card might exhibit this
issue or might not -
it is not tight to a one specific SD Card. Hence I believe it is quite
important to look at it further,
as there might be a lot of reports from various users.
Please note, that for all SD Cards I've tested NVCC_SD2 is indeed physically
switched to 1v8.
>
> Best Regards
> Haibo
>
> > *** Warning - No block device, using default environment
> >
> > In:serial
> > Out: serial
> > Err: serial
> > Net: eth0: ethernet@30be
> > Hit any key to stop autoboot: 0
> > u-boot=> mmc dev 1
> > Card did not respond to voltage select! : -110 u-boot=> mmc info MMC
> > Device
> > 0 not found no mmc device at slot 0 u-boot=> mmc dev 2 switch to
> > partitions #0, OK mmc2(part 0) is current device u-boot=> mmc info
> > Device: FSL_SDHC
> > Manufa
RE: [PATCH] mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON to control card clock output
> -Original Message-
> From: ZHIZHIKIN Andrey [mailto:andrey.zhizhi...@leica-geosystems.com]
> Sent: 2021年2月1日 17:52
> To: Bough Chen ; Peng Fan ;
> u-boot@lists.denx.de
> Cc: dl-uboot-imx ; thar...@gateworks.com
> Subject: RE: [PATCH] mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON
> to control card clock output
>
> Hello Haibo,
>
> > -Original Message-
> > From: haibo.c...@nxp.com
> > Sent: Wednesday, January 27, 2021 11:47 AM
> > To: peng@nxp.com; u-boot@lists.denx.de
> > Cc: haibo.c...@nxp.com; uboot-...@nxp.com; thar...@gateworks.com;
> > ZHIZHIKIN Andrey
> > Subject: [PATCH] mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON to
> > control card clock output
> >
> > This email is not from Hexagon’s Office 365 instance. Please be
> > careful while clicking links, opening attachments, or replying to this
> > email.
> >
> >
> > From: Haibo Chen
> >
> > For FSL_USDHC, it do not implement
> VENDORSPEC_CKEN/PEREN/HCKEN/IPGEN,
> > these are reserved bits. Instead, use VENDORSPEC_FRC_SDCLK_ON to gate
> > on/off the card clock output.
> >
> > After commit b5874b552ffa ("mmc: fsl_esdhc_imx: add wait_dat0()
> > support"), we meet SD3.0 card can't work at UHS mode,
> > mmc_switch_voltage() fail because the second mmc_wait_dat0 return
> > -ETIMEDOUT. According to SD spec, during voltage switch, need to gate
> > off/on the card clock. If not set the FRC_SDCLK_ON, after CMD11,
> > hardware will gate off the card clock automatically, so card do not
> > detect the clock off/on behavior, so will draw the data0 line low until next
> command.
> >
> > Fixes: b5874b552ffa ("mmc: fsl_esdhc_imx: add wait_dat0() support")
>
> This patch does not fix the switch of uSDHC to 1v8...
>
> I've applied it locally on the imx8mmevk, and had following log during the
> boot
> when tried to query SD Card info:
> ---
> U-Boot SPL 2021.01-01004-gb852007333 (Feb 01 2021 - 09:45:42 +0100)
> Normal Boot
> WDT: Started with servicing (60s timeout)
> Trying to boot from MMC1
> NOTICE: BL31: v2.2(release):rel_imx_5.4.70_2.3.0-0-gf1d7187f2
> NOTICE: BL31: Built : 22:29:05, Jan 17 2021
>
>
> U-Boot 2021.01-01004-gb852007333 (Feb 01 2021 - 09:45:42 +0100)
>
> CPU: Freescale i.MX8MMQ rev1.0 at 1200 MHz
> Reset cause: POR
> Model: FSL i.MX8MM EVK board
> DRAM: 2 GiB
> WDT: Started with servicing (60s timeout)
> MMC: FSL_SDHC: 1, FSL_SDHC: 2
> Loading Environment from MMC... Run CMD11 1.8V switch Card did not
> respond to voltage select! : -110
This do not align with my test result. Can you help identify which function
first return the timeout on your side?
Or can you try a different SD card?
Best Regards
Haibo
> *** Warning - No block device, using default environment
>
> In:serial
> Out: serial
> Err: serial
> Net: eth0: ethernet@30be
> Hit any key to stop autoboot: 0
> u-boot=> mmc dev 1
> Card did not respond to voltage select! : -110 u-boot=> mmc info MMC Device
> 0 not found no mmc device at slot 0 u-boot=> mmc dev 2 switch to partitions
> #0,
> OK mmc2(part 0) is current device u-boot=> mmc info
> Device: FSL_SDHC
> Manufacturer ID: 45
> OEM: 100
> Name: DG401
> Bus Speed: 2
> Mode: HS400ES (200MHz)
> Rd Block Len: 512
> MMC version 5.1
> High Capacity: Yes
> Capacity: 14.7 GiB
> Bus Width: 8-bit DDR
> Erase Group Size: 512 KiB
> HC WP Group Size: 8 MiB
> User Capacity: 14.7 GiB WRREL
> Boot Capacity: 4 MiB ENH
> RPMB Capacity: 4 MiB ENH
> Boot area 0 is not write protected
> Boot area 1 is not write protected
> ---
>
> Note, that eMMC is not affected and is operating in HS400ES mode without any
> issues.
>
> Reverting patch b5874b552ffa ("mmc: fsl_esdhc_imx: add wait_dat0() support")
> with this patch applied in tree does switch the SD Card to high-speed mode,
> following log is produced:
> ---
> U-Boot SPL 2021.01-01005-gb8aeb689a2 (Feb 01 2021 - 10:38:01 +0100)
> Normal Boot
> WDT: Started with servicing (60s timeout)
> Trying to boot from MMC1
> NOTICE: BL31: v2.2(release):rel_imx_5.4.70_2.3.0-0-gf1d7187f2
> NOTICE: BL31: Built : 22:29:05, Jan 17 2021
>
>
> U-Boot 2021.01-01005-gb8aeb689a2 (Feb 01 2021 - 10:38:01 +0100)
>
> CPU: Freescale i.MX8MMQ rev1.0 at 1200 MHz
> Reset cause: POR
> Model: FSL i.MX8MM EVK board
> DRAM: 2 GiB
> WDT: Started with servicing (60s timeout)
> MMC: FSL_SDHC: 1, FSL_SDHC: 2
> Loading Env
RE: [PATCH] mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON to control card clock output
Hello Haibo,
> -Original Message-
> From: haibo.c...@nxp.com
> Sent: Wednesday, January 27, 2021 11:47 AM
> To: peng@nxp.com; u-boot@lists.denx.de
> Cc: haibo.c...@nxp.com; uboot-...@nxp.com; thar...@gateworks.com;
> ZHIZHIKIN Andrey
> Subject: [PATCH] mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON to
> control card clock output
>
> This email is not from Hexagon’s Office 365 instance. Please be careful while
> clicking links, opening attachments, or replying to this email.
>
>
> From: Haibo Chen
>
> For FSL_USDHC, it do not implement VENDORSPEC_CKEN/PEREN/HCKEN/IPGEN,
> these are reserved bits. Instead, use VENDORSPEC_FRC_SDCLK_ON to gate
> on/off the card clock output.
>
> After commit b5874b552ffa ("mmc: fsl_esdhc_imx: add wait_dat0() support"),
> we meet SD3.0 card can't work at UHS mode, mmc_switch_voltage() fail because
> the second mmc_wait_dat0 return -ETIMEDOUT. According to SD spec, during
> voltage switch, need to gate off/on the card clock. If not set the
> FRC_SDCLK_ON,
> after CMD11, hardware will gate off the card clock automatically, so card do
> not
> detect the clock off/on behavior, so will draw the data0 line low until next
> command.
>
> Fixes: b5874b552ffa ("mmc: fsl_esdhc_imx: add wait_dat0() support")
This patch does not fix the switch of uSDHC to 1v8...
I've applied it locally on the imx8mmevk, and had following log during the boot
when tried
to query SD Card info:
---
U-Boot SPL 2021.01-01004-gb852007333 (Feb 01 2021 - 09:45:42 +0100)
Normal Boot
WDT: Started with servicing (60s timeout)
Trying to boot from MMC1
NOTICE: BL31: v2.2(release):rel_imx_5.4.70_2.3.0-0-gf1d7187f2
NOTICE: BL31: Built : 22:29:05, Jan 17 2021
U-Boot 2021.01-01004-gb852007333 (Feb 01 2021 - 09:45:42 +0100)
CPU: Freescale i.MX8MMQ rev1.0 at 1200 MHz
Reset cause: POR
Model: FSL i.MX8MM EVK board
DRAM: 2 GiB
WDT: Started with servicing (60s timeout)
MMC: FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... Run CMD11 1.8V switch
Card did not respond to voltage select! : -110
*** Warning - No block device, using default environment
In:serial
Out: serial
Err: serial
Net: eth0: ethernet@30be
Hit any key to stop autoboot: 0
u-boot=> mmc dev 1
Card did not respond to voltage select! : -110
u-boot=> mmc info
MMC Device 0 not found
no mmc device at slot 0
u-boot=> mmc dev 2
switch to partitions #0, OK
mmc2(part 0) is current device
u-boot=> mmc info
Device: FSL_SDHC
Manufacturer ID: 45
OEM: 100
Name: DG401
Bus Speed: 2
Mode: HS400ES (200MHz)
Rd Block Len: 512
MMC version 5.1
High Capacity: Yes
Capacity: 14.7 GiB
Bus Width: 8-bit DDR
Erase Group Size: 512 KiB
HC WP Group Size: 8 MiB
User Capacity: 14.7 GiB WRREL
Boot Capacity: 4 MiB ENH
RPMB Capacity: 4 MiB ENH
Boot area 0 is not write protected
Boot area 1 is not write protected
---
Note, that eMMC is not affected and is operating in HS400ES mode without any
issues.
Reverting patch b5874b552ffa ("mmc: fsl_esdhc_imx: add wait_dat0() support")
with this
patch applied in tree does switch the SD Card to high-speed mode, following log
is produced:
---
U-Boot SPL 2021.01-01005-gb8aeb689a2 (Feb 01 2021 - 10:38:01 +0100)
Normal Boot
WDT: Started with servicing (60s timeout)
Trying to boot from MMC1
NOTICE: BL31: v2.2(release):rel_imx_5.4.70_2.3.0-0-gf1d7187f2
NOTICE: BL31: Built : 22:29:05, Jan 17 2021
U-Boot 2021.01-01005-gb8aeb689a2 (Feb 01 2021 - 10:38:01 +0100)
CPU: Freescale i.MX8MMQ rev1.0 at 1200 MHz
Reset cause: POR
Model: FSL i.MX8MM EVK board
DRAM: 2 GiB
WDT: Started with servicing (60s timeout)
MMC: FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... Run CMD11 1.8V switch
*** Warning - bad CRC, using default environment
In:serial
Out: serial
Err: serial
Net: eth0: ethernet@30be
Hit any key to stop autoboot: 0
u-boot=> mmc dev 1
Run CMD11 1.8V switch
switch to partitions #0, OK
mmc1 is current device
u-boot=> mmc info
Device: FSL_SDHC
Manufacturer ID: 41
OEM: 3432
Name: SD32G
Bus Speed: 2
Mode: UHS SDR104 (208MHz)
Rd Block Len: 512
SD version 3.0
High Capacity: Yes
Capacity: 29.3 GiB
Bus Width: 4-bit
Erase Group Size: 512 Bytes
u-boot=> mmc dev 2
switch to partitions #0, OK
mmc2(part 0) is current device
u-boot=> mmc info
Device: FSL_SDHC
Manufacturer ID: 45
OEM: 100
Name: DG401
Bus Speed: 2
Mode: HS400ES (200MHz)
Rd Block Len: 512
MMC version 5.1
High Capacity: Yes
Capacity: 14.7 GiB
Bus Width: 8-bit DDR
Erase Group Size: 512 KiB
HC WP Group Size: 8 MiB
User Capacity: 14.7 GiB WRREL
Boot Capacity: 4 MiB ENH
RPMB Capacity: 4 MiB ENH
Boot area 0 is not write protected
Boot area 1 is not write protected
---
I guess high-level modifications are also required, since the uSDHC does not
follow the SD
Specification in regards to voltage switching, which is currently implement
