Re: [PATCH 2/2] arm64: dts: imx8mm-beacon: Resync imx8mm-beacon-som with 5.11-rc4
On Mon, Jan 18, 2021 at 7:44 PM Peng Fan wrote:
>
> > Subject: [PATCH 2/2] arm64: dts: imx8mm-beacon: Resync
> > imx8mm-beacon-som with 5.11-rc4
> >
> > In order to support the QSPI chip on the SOM, the Flexspi bus needs to be
> > configured to talk with the SPI chip.
> > Resync the som device tree with 5.11-rc4
> >
> > Signed-off-by: Adam Ford
> >
> > diff --git a/arch/arm/dts/imx8mm-beacon-som.dtsi
> > b/arch/arm/dts/imx8mm-beacon-som.dtsi
> > index b88c3c99b0..d897913537 100644
> > --- a/arch/arm/dts/imx8mm-beacon-som.dtsi
> > +++ b/arch/arm/dts/imx8mm-beacon-som.dtsi
> > @@ -4,6 +4,11 @@
> > */
> >
> > / {
> > + aliases {
> > + rtc0 =
> > + rtc1 = _rtc;
>
> Acked-by: Peng Fan
>
> Just have a question here, why you have two RTC here?
The external one consumes much less power than the internal one. It's
used for maintaining time while power is removed. The internal one
was kept enabled because while powered, it can still be used for
alarms, wake, etc. without losing functionality.
adam
>
> > + };
> > +
> > usdhc1_pwrseq: usdhc1_pwrseq {
> > compatible = "mmc-pwrseq-simple";
> > pinctrl-names = "default";
> > @@ -24,6 +29,18 @@
> > cpu-supply = <_reg>;
> > };
> >
> > +_1 {
> > + cpu-supply = <_reg>;
> > +};
> > +
> > +_2 {
> > + cpu-supply = <_reg>;
> > +};
> > +
> > +_3 {
> > + cpu-supply = <_reg>;
> > +};
> > +
> > {
> > operating-points-v2 = <_opp_table>;
> >
> > @@ -63,6 +80,22 @@
> > };
> > };
> >
> > + {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <_flexspi>;
> > + status = "okay";
> > +
> > + flash@0 {
> > + reg = <0>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + compatible = "jedec,spi-nor";
> > + spi-max-frequency = <8000>;
> > + spi-tx-bus-width = <4>;
> > + spi-rx-bus-width = <4>;
> > + };
> > +};
> > +
> > {
> > clock-frequency = <40>;
> > pinctrl-names = "default";
> > @@ -78,6 +111,10 @@
> > interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
> > rohm,reset-snvs-powered;
> >
> > + #clock-cells = <0>;
> > + clocks = <_32k 0>;
> > + clock-output-names = "clk-32k-out";
> > +
> > regulators {
> > buck1_reg: BUCK1 {
> > regulator-name = "buck1";
> > @@ -191,7 +228,7 @@
> > reg = <0x50>;
> > };
> >
> > - rtc@51 {
> > + rtc: rtc@51 {
> > compatible = "nxp,pcf85263";
> > reg = <0x51>;
> > };
> > @@ -258,155 +295,166 @@
> > };
> >
> > {
> > - pinctrl_fec1: fec1grp {
> > - fsl,pins = <
> > - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
> > - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
> > - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
> > - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
> > - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
> > - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
> > - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
> > - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
> > - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
> > - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
> > - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
> > - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
> > -
> > MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
> > - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL
> > 0x1f
> > - MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO220x19
> > - >;
> > - };
> > + pinctrl_fec1: fec1grp {
> > + fsl,pins = <
> > + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
> > + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
> > + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
> > + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
> > + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
> > + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
> > + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
> > + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
> > + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
> > + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
> > + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
> > + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
> > +
RE: [PATCH 2/2] arm64: dts: imx8mm-beacon: Resync imx8mm-beacon-som with 5.11-rc4
> Subject: [PATCH 2/2] arm64: dts: imx8mm-beacon: Resync
> imx8mm-beacon-som with 5.11-rc4
>
> In order to support the QSPI chip on the SOM, the Flexspi bus needs to be
> configured to talk with the SPI chip.
> Resync the som device tree with 5.11-rc4
>
> Signed-off-by: Adam Ford
>
> diff --git a/arch/arm/dts/imx8mm-beacon-som.dtsi
> b/arch/arm/dts/imx8mm-beacon-som.dtsi
> index b88c3c99b0..d897913537 100644
> --- a/arch/arm/dts/imx8mm-beacon-som.dtsi
> +++ b/arch/arm/dts/imx8mm-beacon-som.dtsi
> @@ -4,6 +4,11 @@
> */
>
> / {
> + aliases {
> + rtc0 =
> + rtc1 = _rtc;
Acked-by: Peng Fan
Just have a question here, why you have two RTC here?
> + };
> +
> usdhc1_pwrseq: usdhc1_pwrseq {
> compatible = "mmc-pwrseq-simple";
> pinctrl-names = "default";
> @@ -24,6 +29,18 @@
> cpu-supply = <_reg>;
> };
>
> +_1 {
> + cpu-supply = <_reg>;
> +};
> +
> +_2 {
> + cpu-supply = <_reg>;
> +};
> +
> +_3 {
> + cpu-supply = <_reg>;
> +};
> +
> {
> operating-points-v2 = <_opp_table>;
>
> @@ -63,6 +80,22 @@
> };
> };
>
> + {
> + pinctrl-names = "default";
> + pinctrl-0 = <_flexspi>;
> + status = "okay";
> +
> + flash@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "jedec,spi-nor";
> + spi-max-frequency = <8000>;
> + spi-tx-bus-width = <4>;
> + spi-rx-bus-width = <4>;
> + };
> +};
> +
> {
> clock-frequency = <40>;
> pinctrl-names = "default";
> @@ -78,6 +111,10 @@
> interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
> rohm,reset-snvs-powered;
>
> + #clock-cells = <0>;
> + clocks = <_32k 0>;
> + clock-output-names = "clk-32k-out";
> +
> regulators {
> buck1_reg: BUCK1 {
> regulator-name = "buck1";
> @@ -191,7 +228,7 @@
> reg = <0x50>;
> };
>
> - rtc@51 {
> + rtc: rtc@51 {
> compatible = "nxp,pcf85263";
> reg = <0x51>;
> };
> @@ -258,155 +295,166 @@
> };
>
> {
> - pinctrl_fec1: fec1grp {
> - fsl,pins = <
> - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
> - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
> - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
> - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
> - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
> - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
> - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
> - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
> - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
> - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
> - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
> - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
> -
> MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
> - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL
> 0x1f
> - MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO220x19
> - >;
> - };
> + pinctrl_fec1: fec1grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
> + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
> + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
> + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
> + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
> + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
> + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
> + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
> + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
> + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
> + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
> + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
> + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL
> 0x91
> + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL
> 0x1f
> + MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO220x19
> + >;
> + };
>
> - pinctrl_i2c1: i2c1grp {
> - fsl,pins = <
> - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL
> 0x41c3
> - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA
> 0x41c3
> - >;
> - };
> + pinctrl_i2c1: i2c1grp {
> +
