> -Original Message-
> From: U-Boot On Behalf Of Paul Barker
> Sent: Monday, February 26, 2024 3:06 PM
> To: Marek Vasut ; Nobuhiro Iwamatsu
>
> Cc: Paul Barker ; u-boot@lists.denx.de
> Subject: [PATCH v2 3/7] i2c: rzg2l: Add I2C driver for RZ/G2L family
>
> This driver supports the I2C module on the Renesas RZ/G2L (R9A07G044) SoC,
> also known as the RIIC module.
>
> This patch is based on both the u-boot driver in the Renesas RZ BSP
> 3.0.5 release [1] (commit 7fcc1fdc2534), and the Linux v6.7 driver (commit
> 0dd3ee311255).
>
> Support for deblocking the I2C bus is included as this may be needed after
> triggering a reset via the Power Management IC (PMIC) over I2C (the PMIC
> asserts the reset line before the SoC completes the I2C write transaction
> with obvious bus locking effects). If the SDA line is observed to be low
> during initialisation, we automatically attempt to deblock.
>
> [1]:
>
> Signed-off-by: Paul Barker
> eviewed-by: Marek Vasut
Typo. R is missing in the Rb tag.
Also change log is missing.
> ---
> arch/arm/mach-rmobile/Kconfig | 1 +
> configs/renesas_rzg2l_smarc_defconfig | 2 +
> drivers/i2c/Kconfig | 7 +
> drivers/i2c/Makefile | 1 +
> drivers/i2c/rz_riic.c | 624 ++
> 5 files changed, 635 insertions(+)
> create mode 100644 drivers/i2c/rz_riic.c
>
> diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig
> index 2bb96749fc0d..38ede6e0b5b5 100644
> --- a/arch/arm/mach-rmobile/Kconfig
> +++ b/arch/arm/mach-rmobile/Kconfig
> @@ -78,6 +78,7 @@ config RZG2L
> imply RENESAS_SDHI
> imply RZG2L_GPIO
> imply SCIF_CONSOLE
> + imply SYS_I2C_RZ_RIIC
> imply SYS_MALLOC_F
> help
> Enable support for the Renesas RZ/G2L family of SoCs. Currently
> diff --git a/configs/renesas_rzg2l_smarc_defconfig
> b/configs/renesas_rzg2l_smarc_defconfig
> index e45579ae6b98..ad46297c6619 100644
> --- a/configs/renesas_rzg2l_smarc_defconfig
> +++ b/configs/renesas_rzg2l_smarc_defconfig
> @@ -24,6 +24,7 @@ CONFIG_HUSH_PARSER=y
> CONFIG_SYS_MAXARGS=64
> CONFIG_CMD_CLK=y
> CONFIG_CMD_GPIO=y
> +CONFIG_CMD_I2C=y
> CONFIG_CMD_MMC=y
> CONFIG_CMD_PART=y
> CONFIG_CMD_EXT2=y
> @@ -44,6 +45,7 @@ CONFIG_CLK=y
> CONFIG_CLK_RENESAS=y
> # CONFIG_CLK_RCAR_GEN3 is not set
> CONFIG_GPIO_HOG=y
> +CONFIG_DM_I2C=y
> CONFIG_MMC_IO_VOLTAGE=y
> CONFIG_MMC_UHS_SUPPORT=y
> CONFIG_MMC_HS400_SUPPORT=y
> diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index
> 4f42200f3923..d2a3a13493aa 100644
> --- a/drivers/i2c/Kconfig
> +++ b/drivers/i2c/Kconfig
> @@ -524,6 +524,13 @@ config SYS_I2C_ROCKCHIP
> have several I2C ports and all are provided, controlled by the
> device tree.
>
> +config SYS_I2C_RZ_RIIC
> + bool "Renesas RZ/G2L RIIC driver"
> + depends on RZG2L && DM_I2C
> + help
> + Support for the I2C controller (RIIC) on the Renesas RZ/G2L SoC
> + family.
> +
> config SYS_I2C_SANDBOX
> bool "Sandbox I2C driver"
> depends on SANDBOX && DM_I2C
> diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index
> a96a8c7e955e..692f63bafd02 100644
> --- a/drivers/i2c/Makefile
> +++ b/drivers/i2c/Makefile
> @@ -40,6 +40,7 @@ obj-$(CONFIG_SYS_I2C_QUP) += qup_i2c.o
> obj-$(CONFIG_SYS_I2C_RCAR_I2C) += rcar_i2c.o
> obj-$(CONFIG_SYS_I2C_RCAR_IIC) += rcar_iic.o
> obj-$(CONFIG_SYS_I2C_ROCKCHIP) += rk_i2c.o
> +obj-$(CONFIG_SYS_I2C_RZ_RIIC) += rz_riic.o
> obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o exynos_hs_i2c.o
> obj-$(CONFIG_SYS_I2C_SANDBOX) += sandbox_i2c.o i2c-emul-uclass.o
> obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
> diff --git a/drivers/i2c/rz_riic.c b/drivers/i2c/rz_riic.c new file mode
> 100644 index ..5f3f8d1b24b7
> --- /dev/null
> +++ b/drivers/i2c/rz_riic.c
> @@ -0,0 +1,624 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * RZ/G2L I2C (RIIC) driver
> + *
> + * Copyright (C) 2021-2023 Renesas Electronics Corp.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#define RIIC_ICCR1 0x00
> +#define RIIC_ICCR2 0x04
> +#define RIIC_ICMR1 0x08
> +#define RIIC_ICMR2 0x0c
> +#define RIIC_ICMR3 0x10
> +#define RIIC_ICFER 0x14
> +#define RIIC_ICSER 0x18
> +#define RIIC_ICIER 0x1c
> +#define RIIC_ICSR1 0x20
> +#define RIIC_ICSR2 0x24
> +#define RIIC_ICSAR0 0x28
> +#define RIIC_ICBRL 0x34
> +#define RIIC_ICBRH 0x38
> +#define RIIC_ICDRT 0x3c
> +#define RIIC_ICDRR 0x40
> +
> +/* ICCR1 */
> +#define ICCR1_ICEBIT(7)
> +#define ICCR1_IICRST BIT(6)
> +#define ICCR1_CLOBIT(5)
> +#define ICCR1_SOWP BIT(4)
> +#define ICCR1_SCLO BIT(3)
> +#define ICCR1_SDAO BIT(2)
> +#define ICCR1_SCLI BIT(1)
> +#define ICCR1_SDAI BIT(0)
> +
> +/* ICCR2 */
> +#define ICCR2_BBSY BIT(7)
> +#define ICCR2_MSTBIT(6)
> +#define ICCR2_TRSBIT(5)
> +#define ICCR2_SP
