>-----Original Message----- >From: Sean Anderson <sean...@gmail.com> >Sent: 01 September 2020 16:02 >To: u-boot@lists.denx.de >Cc: Rick Chen <rickche...@gmail.com>; Bin Meng <bmeng...@gmail.com>; >Pragnesh Patel <pragnesh.pa...@openfive.com>; Sean Anderson ><sean...@gmail.com> >Subject: [PATCH v3 4/7] riscv: Rework Sifive CLINT as UCLASS_TIMER driver > >[External Email] Do not click links or attachments unless you recognize the >sender and know the content is safe > >This converts the clint driver from the riscv-specific interface to be a >DM-based >UCLASS_TIMER driver. We also need to re-add the initialization for IPI back >into >the SPL code. This was previously implicitly done when the timer was >initialized. >In addition, the SiFive DDR driver previously implicitly depended on the CLINT >to >select REGMAP. > >Unlike Andes's PLMT/PLIC (which AFAIK never have anything pass it a dtb), the >SiFive CLINT is part of the device tree passed in by qemu. This device tree >doesn't >have a clocks or clock-frequency property on clint, so we need to fall back on >the >timebase-frequency property. Perhaps in the future we can get a clock-frequency >property added to the qemu dtb. > >Unlike with the Andes PLMT, the Sifive CLINT is also an IPI controller. >RISCV_SYSCON_CLINT is retained for this purpose. > >Signed-off-by: Sean Anderson <sean...@gmail.com> >--- >This patch builds but has only been tested on the K210 and QEMU. It has NOT >been tested on a HiFive. > >Changes in v3: >- Don't initialize the IPI in spl_invoke_opensbi. Further testing has > revealed it to be unnecessary. > > arch/riscv/Kconfig | 4 -- > arch/riscv/lib/sifive_clint.c | 87 +++++++++++++++++++++++------------ > drivers/ram/sifive/Kconfig | 2 + > 3 files changed, 59 insertions(+), 34 deletions(-)
Reviewed-by: Pragnesh Patel <pragnesh.pa...@openfive.com>