On Sat, 11 Nov 2023 12:10:00 +0300
Mikhail Kalashnikov wrote:
Hi Mikhail,
> From: iuncuim
>
> The H616 SoC family has support for several types of DRAM: DDR3,
> LPDDR3, DDR4 and LPDDR4.
> At the moment, the driver only supports DDR3 and LPDDR3 memory.
> Let's extend the driver to support the LPDDR4 memory. This type
> of memory widely used in device with T507(-H) SoC and new orangepi
> zero3 with H618.
> The compatibility with T507 is not yet complete, because there
> is difference in the phy_init array.
> The LPDDR4-2133 timings correspond to DRAM Rayson RS1G32LO4D2BDS-53BT
> found on the NOR SPI from the Orangepi Zero 3 4GB.
>
> Signed-off-by: Mikhail Kalashnikov
many thanks for staying on this and posting a new version of this patch!
I cannot judge the LPDDR4 changes really, other than saying they work
for me (TM). But it fills me with confidence that basically every change
is guarded by the new LPDDR4 symbol, so the chances for regressions are
very slim. I quickly boot tested on my X96 Mate without issues, so:
Acked-by: Andre Przywara
Also many thanks to Piotr and Jernej for participating in the
development efforts and for testing this!
So I will take this patch and send a pull request later today.
There are some smaller things below, but those actually don't affect
the compiled code and can be fixed later, if needed.
> ---
> .../include/asm/arch-sunxi/dram_sun50i_h616.h | 2 +
> arch/arm/mach-sunxi/Kconfig | 17 ++
> arch/arm/mach-sunxi/dram_sun50i_h616.c| 218 ++
> arch/arm/mach-sunxi/dram_timings/Makefile | 1 +
> .../dram_timings/h616_lpddr4_2133.c | 95
> 5 files changed, 294 insertions(+), 39 deletions(-)
> create mode 100644 arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c
>
> diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
> b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
> index 11774deded..a8fdda124a 100644
> --- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
> +++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
> @@ -130,6 +130,7 @@ check_member(sunxi_mctl_ctl_reg, unk_0x4240, 0x4240);
> #define MSTR_DEVICETYPE_LPDDR2 BIT(2)
> #define MSTR_DEVICETYPE_LPDDR3 BIT(3)
> #define MSTR_DEVICETYPE_DDR4 BIT(4)
> +#define MSTR_DEVICETYPE_LPDDR4 BIT(5)
> #define MSTR_DEVICETYPE_MASK GENMASK(5, 0)
> #define MSTR_2TMODE BIT(10)
> #define MSTR_BUSWIDTH_FULL (0 << 12)
> @@ -154,6 +155,7 @@ struct dram_para {
> u32 odt_en;
> u32 tpr0;
> u32 tpr2;
> + u32 tpr6;
> u32 tpr10;
> u32 tpr11;
> u32 tpr12;
> diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> index 9d5df2c102..e65bcb36a2 100644
> --- a/arch/arm/mach-sunxi/Kconfig
> +++ b/arch/arm/mach-sunxi/Kconfig
> @@ -85,6 +85,12 @@ config DRAM_SUN50I_H616_TPR2
> help
> TPR2 value from vendor DRAM settings.
>
> +config DRAM_SUN50I_H616_TPR6
> + hex "H616 DRAM TPR6 parameter"
> + default 0x3300c080
> + help
> + TPR6 value from vendor DRAM settings.
> +
> config DRAM_SUN50I_H616_TPR10
> hex "H616 DRAM TPR10 parameter"
> help
> @@ -441,6 +447,9 @@ config SUNXI_DRAM_DDR2
> config SUNXI_DRAM_LPDDR3
> bool
>
> +config SUNXI_DRAM_LPDDR4
> + bool
> +
> choice
> prompt "DRAM Type and Timing"
> default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
> @@ -484,6 +493,14 @@ config SUNXI_DRAM_H616_LPDDR3
> This option is the LPDDR3 timing used by the stock boot0 by
> Allwinner.
>
> +config SUNXI_DRAM_H616_LPDDR4
> + bool "LPDDR4 DRAM chips on the H616 DRAM controller"
> + select SUNXI_DRAM_LPDDR4
> + depends on DRAM_SUN50I_H616
> + help
> + This option is the LPDDR4 timing used by the stock boot0 by
> + Allwinner.
> +
> config SUNXI_DRAM_H616_DDR3_1333
> bool "DDR3-1333 boot0 timings on the H616 DRAM controller"
> select SUNXI_DRAM_DDR3
> diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c
> b/arch/arm/mach-sunxi/dram_sun50i_h616.c
> index ba5659d409..e7e39d3f6a 100644
> --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
> +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
> @@ -6,8 +6,8 @@
> * unknown. That's why this driver has plenty of magic numbers. Some
> * meaning was nevertheless deduced from strings found in boot0 and
> * known meaning of some dram parameters.
> - * This driver only supports DDR3 memory and omits logic for all
> - * other supported types supported by hardware.
> + * This driver supports DDR3, LPDDR3 and LPDDR4 memory. There is no
> + * DDR4 support yet.
> *
> * (C) Copyright 2020 Jernej Skrabec
> *
> @@ -238,6 +238,11 @@ static const u8 phy_init[] = {
> 0x08, 0x01, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
> 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x07,
> 0x17, 0x19, 0x1a
> +#elif defined(CONFIG_SUNXI_DRAM_H616_LPDDR4)
> + 0x02, 0x00, 0x17, 0x05, 0x04, 0x19, 0x06, 0x07,
> + 0x08, 0x09,
