> Add pll14xx driver
>
> Signed-off-by: Peng Fan
> ---
> drivers/clk/imx/clk-pll14xx.c | 381
> ++
> drivers/clk/imx/clk.h | 25 +++
> 2 files changed, 406 insertions(+)
> create mode 100644 drivers/clk/imx/clk-pll14xx.c
>
> diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c
> new file mode 100644
> index 00..2246beb21b
> --- /dev/null
> +++ b/drivers/clk/imx/clk-pll14xx.c
> @@ -0,0 +1,381 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright 2017-2019 NXP.
> + *
> + * Peng Fan
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "clk.h"
> +
> +#define UBOOT_DM_CLK_IMX_PLL1443X "imx_clk_pll1443x"
> +#define UBOOT_DM_CLK_IMX_PLL1416X "imx_clk_pll1416x"
> +
> +#define GNRL_CTL 0x0
> +#define DIV_CTL 0x4
> +#define LOCK_STATUS BIT(31)
> +#define LOCK_SEL_MASKBIT(29)
> +#define CLKE_MASKBIT(11)
> +#define RST_MASK BIT(9)
> +#define BYPASS_MASK BIT(4)
> +#define MDIV_SHIFT 12
> +#define MDIV_MASKGENMASK(21, 12)
> +#define PDIV_SHIFT 4
> +#define PDIV_MASKGENMASK(9, 4)
> +#define SDIV_SHIFT 0
> +#define SDIV_MASKGENMASK(2, 0)
> +#define KDIV_SHIFT 0
> +#define KDIV_MASKGENMASK(15, 0)
> +
> +#define LOCK_TIMEOUT_US 1
> +
> +struct clk_pll14xx {
> + struct clk clk;
> + void __iomem*base;
> + enum imx_pll14xx_type type;
> + const struct imx_pll14xx_rate_table *rate_table;
> + int rate_count;
> +};
> +
> +#define to_clk_pll14xx(_clk) container_of(_clk, struct clk_pll14xx, clk)
> +
> +static const struct imx_pll14xx_rate_table *imx_get_pll_settings(
> + struct clk_pll14xx *pll, unsigned long rate)
> +{
> + const struct imx_pll14xx_rate_table *rate_table = pll->rate_table;
> + int i;
> +
> + for (i = 0; i < pll->rate_count; i++)
> + if (rate == rate_table[i].rate)
> + return _table[i];
> +
> + return NULL;
> +}
> +
> +static unsigned long clk_pll1416x_recalc_rate(struct clk *clk)
> +{
> + struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
> + u64 fvco = clk_get_parent_rate(clk);
> + u32 mdiv, pdiv, sdiv, pll_div;
> +
> + pll_div = readl(pll->base + 4);
> + mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
> + pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
> + sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT;
> +
> + fvco *= mdiv;
> + do_div(fvco, pdiv << sdiv);
> +
> + return fvco;
> +}
> +
> +static unsigned long clk_pll1443x_recalc_rate(struct clk *clk)
> +{
> + struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
> + u64 fvco = clk_get_parent_rate(clk);
> + u32 mdiv, pdiv, sdiv, pll_div_ctl0, pll_div_ctl1;
> + short int kdiv;
> +
> + pll_div_ctl0 = readl(pll->base + 4);
> + pll_div_ctl1 = readl(pll->base + 8);
> + mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
> + pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
> + sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT;
> + kdiv = pll_div_ctl1 & KDIV_MASK;
> +
> + /* fvco = (m * 65536 + k) * Fin / (p * 65536) */
> + fvco *= (mdiv * 65536 + kdiv);
> + pdiv *= 65536;
> +
> + do_div(fvco, pdiv << sdiv);
> +
> + return fvco;
> +}
> +
> +static inline bool clk_pll1416x_mp_change(const struct
> imx_pll14xx_rate_table *rate,
> + u32 pll_div)
> +{
> + u32 old_mdiv, old_pdiv;
> +
> + old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
> + old_pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
> +
> + return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv;
> +}
> +
> +static inline bool clk_pll1443x_mpk_change(const struct
> imx_pll14xx_rate_table *rate,
> +u32 pll_div_ctl0, u32 pll_div_ctl1)
> +{
> + u32 old_mdiv, old_pdiv, old_kdiv;
> +
> + old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
> + old_pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
> + old_kdiv = (pll_div_ctl1 & KDIV_MASK) >> KDIV_SHIFT;
> +
> + return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
> + rate->kdiv != old_kdiv;
> +}
> +
> +static inline bool clk_pll1443x_mp_change(const struct
> imx_pll14xx_rate_table *rate,
> + u32 pll_div_ctl0, u32 pll_div_ctl1)
> +{
> + u32 old_mdiv, old_pdiv, old_kdiv;
> +
> + old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
> + old_pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
> + old_kdiv = (pll_div_ctl1 & KDIV_MASK) >> KDIV_SHIFT;
> +
> + return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
> + rate->kdiv != old_kdiv;
> +}
> +
> +static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll)
> +{
> + u32 val;
> +
> + return readl_poll_timeout(pll->base, val,
