Re: [U-Boot] [PATCH v1 7/9] sunxi: mmc support
On Fri, 2014-03-14 at 17:36 +0200, Pantelis Antoniou wrote:
[...]
Thanks for your review. It seems there are still quite a few issues
dating back to the original allwinner dumps here.
@linux-sunxi: if anyone wants to volunteer to help cleanup this
particular driver I'd be very happy -- there's a lot of it!
+
+static void dumpmmcreg(struct sunxi_mmc *reg)
+{
+ debug(dump mmc registers:\n);
+ debug(gctrl 0x%08x\n, reg-gctrl);
+ debug(clkcr 0x%08x\n, reg-clkcr);
+ debug(timeout 0x%08x\n, reg-timeout);
+ debug(width 0x%08x\n, reg-width);
+ debug(blksz 0x%08x\n, reg-blksz);
[...] lots more debug(foo)
+}
^^^ #ifdef DEBUG here?
I can if you prefer but debug() itself effectively includes the same
ifdef so the end result is already the same.
[...]
+/* support 4 mmc hosts */
+struct mmc mmc_dev[4];
+struct sunxi_mmc_host mmc_host[4];
+
^ hosts mmc structs can be allocated even for SPL now
Can be or must be?
+ struct sunxi_mmc_host *mmchost = mmc_host[sdc_no];
+ static struct sunxi_gpio *gpio_c =
+ ((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)-gpio_bank[SUNXI_GPIO_C];
+ static struct sunxi_gpio *gpio_f =
+ ((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)-gpio_bank[SUNXI_GPIO_F];
+#if CONFIG_MMC1_PG
+ static struct sunxi_gpio *gpio_g =
+ ((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)-gpio_bank[SUNXI_GPIO_G];
+#endif
+ static struct sunxi_gpio *gpio_h =
+ ((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)-gpio_bank[SUNXI_GPIO_H];
+ static struct sunxi_gpio *gpio_i =
+ ((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)-gpio_bank[SUNXI_GPIO_I];
+ struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
^ Castings are ugly; rework with a temporary variable.
Ack.
The static's here are odd too and date back to the original alwinner
code dumps. I'll get rid of them too.
[...]
+ case 3:
+ /* PI4-CMD, PI5-CLK, PI6~9-D0~D3 : 2 */
+ writel(0x 16, gpio_i-cfg[0]);
+ writel(0x22, gpio_i-cfg[1]);
+ writel(0x555 8, gpio_i-pull[0]);
+ writel(0x555 8, gpio_i-drv[0]);
+ break;
+
+ default:
+ return -1;
+ }
+
Lots of magic constants. I have no idea what's going on here.
Use a few defines.
Right. These came from the original allwinner dumps so I was worried
that they might be undocumented magic, but actually since the are gpio
frobbing I reckon I can figure them out.
[...] + cmd = (0x1 31) | (0x1 21) | (0x1 13);
+ writel(cmd, mmchost-reg-cmd);
+ while ((readl(mmchost-reg-cmd) (0x1 31)) timeout--);
+ if (!timeout)
+ return -1;
+
^ Eeek! Use udelay and a time based timeout.
Ack.
+ writel(readl(mmchost-reg-rint), mmchost-reg-rint);
+
^ Same here - Not even a timeout?
No loop here though?
[...]
+ rval |= (0x1 16);
#define ?
Ack
[...]
Ambiguous formatting. Use { }
Ack
[...]
+ /* Reset controller */
+ writel(0x7, mmchost-reg-gctrl);
+
Magic value again.
The sum total of the docs for this one are:
* GCTRLREG
* GCTRL[2] : DMA reset
* GCTRL[5] : DMA enable
But I'll see what I can do.
[...]
+ } else {
+ buff = (unsigned int *)data-src;
+ for (i = 0; i (byte_cnt 2); i++) {
+ while (--timeout
+(readl(mmchost-reg-status) (0x1 3)));
+ if (timeout = 0)
+ goto out;
+ writel(buff[i], mmchost-database);
+ timeout = 0xf;
+ }
+ }
+
^ Timeouts using time values? udelay? See above.
Ack.
[]
+ writel(rval, mmchost-reg-idie);
+ writel((u32) pdes, mmchost-reg-dlba);
+ writel((0x2 28) | (0x7 16) | (0x01 3),
+ mmchost-reg-ftrglevel);
+
^ #define again?
Some of these (ftrgllevel) have no docs whatsoever, but I'll do what I
can.
[...]
+ timeout = 0xf;
+ do {
+ status = readl(mmchost-reg-rint);
+ if (!timeout-- || (status 0xbfc2)) {
+ error = status 0xbfc2;
+ debug(cmd timeout %x\n, error);
+ error = TIMEOUT;
+ goto out;
+ }
^ Again timeouts without using time values.
I'm getting the picture ;-)
[...]
+int sunxi_mmc_init(int sdc_no)
+{
+ struct mmc *mmc;
+
+ memset(mmc_dev[sdc_no], 0, sizeof(struct mmc));
+ memset(mmc_host[sdc_no], 0, sizeof(struct sunxi_mmc_host));
+ mmc = mmc_dev[sdc_no];
+
+ sprintf(mmc-name, SUNXI SD/MMC);
+ mmc-priv = mmc_host[sdc_no];
+ mmc-send_cmd = mmc_send_cmd;
+ mmc-set_ios = mmc_set_ios;
+ mmc-init = mmc_core_init;
+
+ mmc-voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
+ mmc-host_caps = MMC_MODE_4BIT;
+ mmc-host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
+
+
Re: [U-Boot] [PATCH v1 7/9] sunxi: mmc support
On Fri, Mar 14, 2014 at 10:33:49AM +, Ian Campbell wrote: Based linux-sunxi#sunxi commit d854c4de2f57 arm: Handle .gnu.hash section in ldscripts vs v2014.01. As well as the following signed-off-by the sunxi branch shows commits to these files authored by the following: Stefan Roese Tom Cubie yemao Signed-off-by: Henrik Nordstrom hen...@henriknordstrom.net Signed-off-by: Luke Leighton l...@lkcl.net Signed-off-by: Oliver Schinagl oli...@schinagl.nl Signed-off-by: Wills Wang wills.wang.o...@gmail.com Signed-off-by: Ian Campbell i...@hellion.org.uk Just the general problems. Pantelis? -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v1 7/9] sunxi: mmc support
Hi Ian,
On Mar 14, 2014, at 12:33 PM, Ian Campbell wrote:
Based linux-sunxi#sunxi commit d854c4de2f57 arm: Handle .gnu.hash section in
ldscripts vs v2014.01.
As well as the following signed-off-by the sunxi branch shows commits to these
files authored by the following:
Stefan Roese
Tom Cubie
yemao
Signed-off-by: Henrik Nordstrom hen...@henriknordstrom.net
Signed-off-by: Luke Leighton l...@lkcl.net
Signed-off-by: Oliver Schinagl oli...@schinagl.nl
Signed-off-by: Wills Wang wills.wang.o...@gmail.com
Signed-off-by: Ian Campbell i...@hellion.org.uk
---
arch/arm/include/asm/arch-sunxi/mmc.h | 66
board/sunxi/board.c | 13 +
drivers/mmc/Makefile | 1 +
drivers/mmc/sunxi_mmc.c | 650 ++
include/configs/sunxi-common.h| 11 +
5 files changed, 741 insertions(+)
create mode 100644 arch/arm/include/asm/arch-sunxi/mmc.h
create mode 100755 drivers/mmc/sunxi_mmc.c
diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h
b/arch/arm/include/asm/arch-sunxi/mmc.h
new file mode 100644
index 000..639a7fc
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/mmc.h
@@ -0,0 +1,66 @@
+/*
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. www.allwinnertech.com
+ * Aaron leafy.m...@allwinnertech.com
+ *
+ * MMC register definition for allwinner sunxi platform.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SUNXI_MMC_H
+#define _SUNXI_MMC_H
+
+#include linux/types.h
+
+struct sunxi_mmc {
+ u32 gctrl; /* (0x00) SMC Global Control Register */
+ u32 clkcr; /* (0x04) SMC Clock Control Register */
+ u32 timeout;/* (0x08) SMC Time Out Register */
+ u32 width; /* (0x0c) SMC Bus Width Register */
+ u32 blksz; /* (0x10) SMC Block Size Register */
+ u32 bytecnt;/* (0x14) SMC Byte Count Register */
+ u32 cmd;/* (0x18) SMC Command Register */
+ u32 arg;/* (0x1c) SMC Argument Register */
+ u32 resp0; /* (0x20) SMC Response Register 0 */
+ u32 resp1; /* (0x24) SMC Response Register 1 */
+ u32 resp2; /* (0x28) SMC Response Register 2 */
+ u32 resp3; /* (0x2c) SMC Response Register 3 */
+ u32 imask; /* (0x30) SMC Interrupt Mask Register */
+ u32 mint; /* (0x34) SMC Masked Interrupt Status Reg */
+ u32 rint; /* (0x38) SMC Raw Interrupt Status Register */
+ u32 status; /* (0x3c) SMC Status Register */
+ u32 ftrglevel; /* (0x40) SMC FIFO Threshold Watermark Reg */
+ u32 funcsel;/* (0x44) SMC Function Select Register */
+ u32 cbcr; /* (0x48) SMC CIU Byte Count Register */
+ u32 bbcr; /* (0x4c) SMC BIU Byte Count Register */
+ u32 dbgc; /* (0x50) SMC Debug Enable Register */
+ u32 res0[11]; /* (0x54~0x7c) */
+ u32 dmac; /* (0x80) SMC IDMAC Control Register */
+ u32 dlba; /* (0x84) SMC IDMAC Descr List Base Addr Reg */
+ u32 idst; /* (0x88) SMC IDMAC Status Register */
+ u32 idie; /* (0x8c) SMC IDMAC Interrupt Enable Register */
+ u32 chda; /* (0x90) */
+ u32 cbda; /* (0x94) */
+ u32 res1[26]; /* (0x98~0xff) */
+ u32 fifo; /* (0x100) SMC FIFO Access Address */
+};
+
+int sunxi_mmc_init(int sdc_no);
+#endif /* _SUNXI_MMC_H */
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index bffef4f..5dbcf2a 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -30,6 +30,7 @@
#include common.h
#include asm/arch/clock.h
#include asm/arch/dram.h
+#include asm/arch/mmc.h
DECLARE_GLOBAL_DATA_PTR;
@@ -59,6 +60,18 @@ int dram_init(void)
return 0;
}
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+ sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
+#if !defined (CONFIG_SPL_BUILD) defined (CONFIG_MMC_SUNXI_SLOT_EXTRA)
+
