Re: [U-Boot] [PATCH 26/27] ARM64: zynqmp: Add clocks for LPDDMA

[Michal Simek]

On 11.11.2016 18:49, Soren Brinkmann wrote:
> 
> 
>> -Original Message-
>> From: Michal Simek [mailto:mon...@monstr.eu] On Behalf Of Michal Simek
>> Sent: November 11, 2016 05:42
>> To: u-boot@lists.denx.de
>> Cc: Appana Durga Kedareswara Rao ; Naga Sureshkumar
>> Relli ; Bharat Kumar Gogada ;
>> Hyun Kwon ; Albert Aribaud
>> ; Soren Brinkmann ; Filip
>> Drazic 
>> Subject: [PATCH 26/27] ARM64: zynqmp: Add clocks for LPDDMA
>>
>> From: Kedareswara rao Appana 
>>
>> Zynqmp DMA driver expects two clocks (main clock and apb clock)
>> For LPDDMA channels the two clocks are missing in the
>> Dma node resulting probe failure.
>>
>> xilinx-zynqmp-dma ffa8.dma: main clock not found.
>> xilinx-zynqmp-dma ffa8.dma: Probing channel failed
>> xilinx-zynqmp-dma: probe of ffa8.dma failed with error -2
>>
>> This patch fixes this issue.
>>
>> Signed-off-by: Kedareswara rao Appana 
>> Signed-off-by: Michal Simek 
>> ---
>>
>>  arch/arm/dts/zynqmp.dtsi | 8 
>>  1 file changed, 8 insertions(+)
>>
>> diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
>> index aeeccbf9e9d0..5b4fe0962e05 100644
>> --- a/arch/arm/dts/zynqmp.dtsi
>> +++ b/arch/arm/dts/zynqmp.dtsi
>> @@ -428,6 +428,7 @@
>>  lpd_dma_chan1: dma@ffa8 {
>>  status = "disabled";
>>  compatible = "xlnx,zynqmp-dma-1.0";
>> +clock-names = "clk_main", "clk_apb";
>>  reg = <0x0 0xffa8 0x0 0x1000>;
>>  interrupt-parent = <>;
>>  interrupts = <0 77 4>;
> 
> Am I missing something? Adding 'clock-names' without 'clocks' doesn't seem 
> right.

Clocks were added in 1/27
http://lists.denx.de/pipermail/u-boot/2016-November/272338.html

The reason for this split is that this is cherry-pick of patches we did
in Xilinx tree.

Thanks,
Michal

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Re: [U-Boot] [PATCHv2 03/15] dm: pci: remove pci_bus_to_hose(0) calling

[Z.Q. Hou]

Hi Simon,

Thanks for your comments!

> -Original Message-
> From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
> Sent: 2016年11月12日 0:18
> To: Z.Q. Hou 
> Cc: U-Boot Mailing List ; Albert ARIBAUD
> ; Prabhakar Kushwaha
> ; Huan Wang-B18965
> ; Sumit Garg ; Ruchika
> Gupta ; Saksham Jain
> ; york sun ; M.H. Lian
> ; Bin Meng ; Mingkai Hu
> 
> Subject: Re: [PATCHv2 03/15] dm: pci: remove pci_bus_to_hose(0) calling
> 
> Hi,
> 
> On 10 November 2016 at 03:58, Zhiqiang Hou 
> wrote:
> > From: Minghuan Lian 
> >
> > There may be multiple PCIe controllers in a SoC.
> > It is not correct that always calling pci_bus_to_hose(0) to get the
> > first PCIe controller for the PCIe device connected other controllers.
> > We just remove this calling because hose always point the correct PCIe
> > controller.
> >
> > Signed-off-by: Minghuan Lian 
> > Signed-off-by: Hou Zhiqiang 
> > ---
> > V2:
> >  - No change
> >
> >  drivers/pci/pci_common.c | 10 --
> >  1 file changed, 10 deletions(-)
> 
> So is 'hose' always a root PCI controller now? If so, can you comment these in
> the header? I'm a bit confused by this

Yes, the patch 02 of this patchset statement that the function 
pci_bus_to_hose() will return the root pci controller.
And will add the comment for the function.

> 
> We should perhaps move the regions[] array into its own struct separate from
> pci_controller.

Could you let this patch set in first? Because I think this is a big task, and 
so far we have no effort to do that.

> 
> >
> > diff --git a/drivers/pci/pci_common.c b/drivers/pci/pci_common.c index
> > 1755914..448e814 100644
> > --- a/drivers/pci/pci_common.c
> > +++ b/drivers/pci/pci_common.c
> > @@ -181,11 +181,6 @@ phys_addr_t pci_hose_bus_to_phys(struct
> pci_controller *hose,
> > return phys_addr;
> > }
> >
> > -#ifdef CONFIG_DM_PCI
> > -   /* The root controller has the region information */
> > -   hose = pci_bus_to_hose(0);
> > -#endif
> > -
> > /*
> >  * if PCI_REGION_MEM is set we do a two pass search with
> preference
> >  * on matches that don't have PCI_REGION_SYS_MEMORY set
> @@
> > -248,11 +243,6 @@ pci_addr_t pci_hose_phys_to_bus(struct pci_controller
> *hose,
> > return bus_addr;
> > }
> >
> > -#ifdef CONFIG_DM_PCI
> > -   /* The root controller has the region information */
> > -   hose = pci_bus_to_hose(0);
> > -#endif
> > -
> > /*
> >  * if PCI_REGION_MEM is set we do a two pass search with
> preference
> >  * on matches that don't have PCI_REGION_SYS_MEMORY set
> > --
> > 2.1.0.27.g96db324
> >

Thanks,
Zhiqiang
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Re: [U-Boot] [PATCH] arm: sunxi: do not force USB for arch-sunxi

[Hans de Goede]

Hi,

On 31-10-16 22:33, Yann E. MORIN wrote:

Currently, USB is forced-enabled for the sunxi familly, and there is no
way to disable it.

However, USB takes a long time to initiliase, delaying the boot by up to
5 seconds (without any USB device attached!). This is a very long delay,
especially in cases where USB booting is not wanted at all, and where
the device is expected to boot relatively often (even in production).

Change the way the dependencies are handled, by only forcibly selecting
USB when CONFIG_DISTRO_DEFAULTS ("defaults suitable for booting general
purpose Linux distributions") is set. This option defaults to y for the
sunxi familly, so the current default behaviour is kept unchanged. Users
interested in boot time and/or size will be able to disable this to
further disable USB.

With USB disabled, the time spent in U-Boot before handing control to
the Linux kernel is about 1s now, down from ~5s (Nanopi Neo, sunxi H3).

Signed-off-by: "Yann E. MORIN" 
Cc: Ian Campbell 
Cc: Hans De Goede 

---
This is a tentative patch, acting as an RFC (unless it is good to go as
is, of course!).


I cannot come up with a better approach either, so this LGTM:

Reviewed-by: Hans de Goede 

Regards,

Hans



This has been discussed on IRC with  and , and this
solution is what emerged from the discussions as a first step.

The second step would be to defer intialisation of drivers until they
are actually needed, i.e. if main boot is not from USB, then don't
initiliase USB; if main boot fails, then initialise addtional drivers,
like USB... Or something along those lines... That's a much tougher
work for me, though...

There are other features that are currently forced like USB, but USB
is by far the worst "offender" and a low-hanging fruit. Those other
"offenders" can be handled in follow up changes.
---
 arch/arm/Kconfig | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d7a9b11..c13f60f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -561,22 +561,22 @@ config ARCH_SUNXI
bool "Support sunxi (Allwinner) SoCs"
select CMD_GPIO
select CMD_MMC if MMC
-   select CMD_USB
+   select CMD_USB if DISTRO_DEFAULTS
select DM
select DM_ETH
select DM_GPIO
select DM_KEYBOARD
select DM_SERIAL
-   select DM_USB
+   select DM_USB if DISTRO_DEFAULTS
select OF_BOARD_SETUP
select OF_CONTROL
select OF_SEPARATE
select SPL_STACK_R if SUPPORT_SPL
select SPL_SYS_MALLOC_SIMPLE if SUPPORT_SPL
select SYS_NS16550
-   select USB
-   select USB_STORAGE
-   select USB_KEYBOARD
+   select USB if DISTRO_DEFAULTS
+   select USB_STORAGE if DISTRO_DEFAULTS
+   select USB_KEYBOARD if DISTRO_DEFAULTS
select USE_TINY_PRINTF

 config TARGET_TS4800


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Re: [U-Boot] [PATCH] drivers: SPI: sunxi SPL: fix warning

[Hans de Goede]

Hi,

On 03-11-16 01:58, Andre Przywara wrote:

Somehow an int returning function without a return statement sneaked
in. Fix it.

Signed-off-by: Andre Przywara 


LGTM:

Reviewed-by: Hans de Goede 

Regards,

Hans



---
 drivers/mtd/spi/sunxi_spi_spl.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi/sunxi_spi_spl.c b/drivers/mtd/spi/sunxi_spi_spl.c
index 67c7edd..7502314 100644
--- a/drivers/mtd/spi/sunxi_spi_spl.c
+++ b/drivers/mtd/spi/sunxi_spi_spl.c
@@ -158,9 +158,10 @@ static void spi0_disable_clock(void)
 (1 << AHB_RESET_SPI0_SHIFT));
 }

-static int spi0_init(void)
+static void spi0_init(void)
 {
unsigned int pin_function = SUNXI_GPC_SPI0;
+
if (IS_ENABLED(CONFIG_MACH_SUN50I))
pin_function = SUN50I_GPC_SPI0;



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[U-Boot] Please pull: u-boot-video/master

[Anatolij Gustschin]

Hi Tom,

The following changes since commit 38cacdab3b5a6d8efd16a4b2620f7ab72144a624:

  Merge branch 'master' of git://git.denx.de/u-boot-tegra (2016-11-08 10:36:57 
-0500)

are available in the git repository at:

  git://git.denx.de/u-boot-video.git master

for you to fetch changes up to 9f6ce7defeb3786739bb55eabb9bb20f5b50cd0f:

  video: bmp: Fix compilation errors with CONFIG_BMP_xxBPP enabled (2016-11-12 
21:03:11 +0100)


Stefan Roese (1):
  video: bmp: Fix compilation errors with CONFIG_BMP_xxBPP enabled

 drivers/video/video_bmp.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

Please pull. Thanks!

Anatolij
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Re: [U-Boot] [PATCH] sunxi: Use the available Kconfig option for AHCI

[Hans de Goede]

Hi,

On 31-10-16 21:05, Jelle van der Waa wrote:

Use the already available Kconfig option for AHCI. Tested on the
BananaPi.

Signed-off-by: Jelle van der Waa 


Patch LGTM:

Reviewed-by: Hans de Goede 

Regards,

Hans



---
 configs/A10-OLinuXino-Lime_defconfig   | 3 ++-
 configs/A20-OLinuXino-Lime2_defconfig  | 3 ++-
 configs/A20-OLinuXino-Lime_defconfig   | 3 ++-
 configs/A20-OLinuXino_MICRO_defconfig  | 3 ++-
 configs/A20-Olimex-SOM-EVB_defconfig   | 3 ++-
 configs/Bananapi_defconfig | 3 ++-
 configs/Bananapro_defconfig| 3 ++-
 configs/Cubieboard2_defconfig  | 3 ++-
 configs/Cubieboard_defconfig   | 3 ++-
 configs/Cubietruck_defconfig   | 3 ++-
 configs/Itead_Ibox_A20_defconfig   | 3 ++-
 configs/Lamobo_R1_defconfig| 3 ++-
 configs/Linksprite_pcDuino3_Nano_defconfig | 3 ++-
 configs/Linksprite_pcDuino3_defconfig  | 3 ++-
 configs/Marsboard_A10_defconfig| 3 ++-
 configs/Mele_A1000_defconfig   | 3 ++-
 configs/Mele_M5_defconfig  | 3 ++-
 configs/Orangepi_defconfig | 3 ++-
 configs/Orangepi_mini_defconfig| 3 ++-
 configs/Wits_Pro_A20_DKT_defconfig | 3 ++-
 20 files changed, 40 insertions(+), 20 deletions(-)

diff --git a/configs/A10-OLinuXino-Lime_defconfig 
b/configs/A10-OLinuXino-Lime_defconfig
index 04b720d..bb7eaf8 100644
--- a/configs/A10-OLinuXino-Lime_defconfig
+++ b/configs/A10-OLinuXino-Lime_defconfig
@@ -8,7 +8,8 @@ CONFIG_SYS_CLK_FREQ=91200
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-olinuxino-lime"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPC(3)"
+CONFIG_AHCI=y
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,SATAPWR=SUNXI_GPC(3)"
 CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/A20-OLinuXino-Lime2_defconfig 
b/configs/A20-OLinuXino-Lime2_defconfig
index 4751fe0..d48e35d 100644
--- a/configs/A20-OLinuXino-Lime2_defconfig
+++ b/configs/A20-OLinuXino-Lime2_defconfig
@@ -8,7 +8,8 @@ CONFIG_USB0_VBUS_PIN="PC17"
 CONFIG_USB0_VBUS_DET="PH5"
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3)"
+CONFIG_AHCI=y
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,SATAPWR=SUNXI_GPC(3)"
 CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/A20-OLinuXino-Lime_defconfig 
b/configs/A20-OLinuXino-Lime_defconfig
index 024dc2d..7c5d84d 100644
--- a/configs/A20-OLinuXino-Lime_defconfig
+++ b/configs/A20-OLinuXino-Lime_defconfig
@@ -6,7 +6,8 @@ CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPC(3)"
+CONFIG_AHCI=y
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,SATAPWR=SUNXI_GPC(3)"
 CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/A20-OLinuXino_MICRO_defconfig 
b/configs/A20-OLinuXino_MICRO_defconfig
index 5809345..9eb5f1b 100644
--- a/configs/A20-OLinuXino_MICRO_defconfig
+++ b/configs/A20-OLinuXino_MICRO_defconfig
@@ -9,7 +9,8 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=3
 CONFIG_VIDEO_VGA=y
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-micro"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
+CONFIG_AHCI=y
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,SATAPWR=SUNXI_GPB(8)"
 CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/A20-Olimex-SOM-EVB_defconfig 
b/configs/A20-Olimex-SOM-EVB_defconfig
index 7a14a7b..a6bf45f 100644
--- a/configs/A20-Olimex-SOM-EVB_defconfig
+++ b/configs/A20-Olimex-SOM-EVB_defconfig
@@ -11,7 +11,8 @@ CONFIG_USB0_VBUS_PIN="PB9"
 CONFIG_USB0_VBUS_DET="PH5"
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olimex-som-evb"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3)"
+CONFIG_AHCI=y
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,SATAPWR=SUNXI_GPC(3)"
 CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig
index 366ef24..3da1cf7 100644
--- a/configs/Bananapi_defconfig
+++ b/configs/Bananapi_defconfig
@@ -7,7 +7,8 @@ CONFIG_VIDEO_COMPOSITE=y
 CONFIG_GMAC_TX_DELAY=3
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapi"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
+CONFIG_AHCI=y
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23)"
 CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig
index 9b39124..2b9c865 

Re: [U-Boot] [PATCH] spl: mmc: fix build without CONFIG_SPL_LIBCOMMON_SUPPORT

[Tom Rini]

On Sun, Nov 13, 2016 at 10:46:19PM +0100, Yann E. MORIN wrote:
> When CONFIG_SPL_LIBCOMMON_SUPPORT is disabled, the last case statement
> is missing a proper statement, which makes the compiler whine.
> 
> Signed-off-by: "Yann E. MORIN" 
> Cc: Pantelis Antoniou 
> ---
>  common/spl/spl_mmc.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
> index c674e61..cc81d19 100644
> --- a/common/spl/spl_mmc.c
> +++ b/common/spl/spl_mmc.c
> @@ -343,6 +343,7 @@ static int spl_mmc_load_image(struct spl_image_info 
> *spl_image,
>  
>   break;
>   case MMCSD_MODE_UNDEFINED:
> + ;
>  #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
>   default:
>   puts("spl: mmc: wrong boot mode\n");

I thought we had applied https://patchwork.ozlabs.org/patch/689910/
already but I see it hasn't.  I do prefer that patch however.

-- 
Tom


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Re: [U-Boot] [PATCH 1/4] mmc: Retry the switch command

[Tom Rini]

On Sun, Nov 13, 2016 at 07:50:53PM +0100, Hans de Goede wrote:
> Hi,
> 
> On 04-11-16 16:18, Maxime Ripard wrote:
> >Some eMMC will fail at the first switch, but would succeed in a subsequent
> >one.
> >
> >Make sure we try several times to cover those cases. The number of retries
> >(and the behaviour) is currently what is being used in Linux.
> >
> >Signed-off-by: Maxime Ripard 
> 
> LGTM:
> 
> Reviewed-by: Hans de Goede 

Reviewed-by: Tom Rini 

> Pantelis or Tom, can you pick this up please ?

Want to just pick it up with the rest of the series in the sunxi tree?

-- 
Tom


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[U-Boot] FDT retrived varaibles appear to have different properties fom other u-boot variables - and are corrupted on get, set, get sequence

[dh]

Cédric
I move the fdt to 0x100
fdt move ${fdt_addr}  100
fdt addr 100

then
fdt get value bootargs /chosen bootargs
printenv bootargs 
bootargs=all the boot args...but setenv abc $bootargs fails...as 
does printenv $bootargs

fdt set bootargs /chosen bootargsfdt get value bootargs /chosen 
bootargsbootargs=bootargs
The variable name bootargs replaces the values contained in the variable 
bootargs in the fdt.
Something is not right in the world of fdt code.
 Duncan Hare

714 931 7952

  From: Cédric Schieli 
 To: d...@synoia.com 
 Sent: Sunday, November 13, 2016 2:21 AM
 Subject: Re: Fw: [U-Boot] Fw: FDT pointer value, passed by the PI firmware, is 
not set in u-boot
   
Hello Duncan,

2016-11-13 3:04 GMT+01:00 :

> If appending to "/chosen bootargs" (making it longer), does the fdt command
> automatically relocate the fdt, or does the u-boot script have to do that
> itself?
>
> The fdt doc at http://www.denx.de/wiki/view/ DULG/UBootCmdFDT
> Is quite unclear on how the fdt size is managed, especially when the fdt is
> located close to the end of memory.

I'm not an expert here, but looking at cmd/fdt.c I didn't find any kind of 
relocation code. So I guess the safe bet is to move the blob before making any 
(growing) change to the tree:

# load the blob from the firmware provided address (at the end of memory)
fdt addr ${fdt_addr}

# move the blob to the (previously) default location (0x100)
fdt move ${fdt_addr_r}

# make needed changes
setenv bootargs "..."

# boot from the new location
bootz ${kernel_addr_r} - ${fdt_addr_r}


Another solution is to force the firmware to load the blob at a fixed location 
(as before) by updating config.txt:
device_tree_address=0x100

Regards,
Cédric


   
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Re: [U-Boot] [PATCH 1/4] mmc: Retry the switch command

[Jaehoon Chung]

On 11/14/2016 07:50 AM, Tom Rini wrote:
> On Sun, Nov 13, 2016 at 07:50:53PM +0100, Hans de Goede wrote:
>> Hi,
>>
>> On 04-11-16 16:18, Maxime Ripard wrote:
>>> Some eMMC will fail at the first switch, but would succeed in a subsequent
>>> one.
>>>
>>> Make sure we try several times to cover those cases. The number of retries
>>> (and the behaviour) is currently what is being used in Linux.
>>>
>>> Signed-off-by: Maxime Ripard 
>>
>> LGTM:
>>
>> Reviewed-by: Hans de Goede 
> 
> Reviewed-by: Tom Rini 
> 
>> Pantelis or Tom, can you pick this up please ?
> 
> Want to just pick it up with the rest of the series in the sunxi tree?

Sorry for late..If you are ok, i will pick these on today.
If you already picked this..let me know, plz.

Best Regards,
Jaehoon Chung

> 

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Re: [U-Boot] [PATCH 4/4] sunxi: sina33: Enable the LCD

[Hans de Goede]

Hi,

On 04-11-16 16:18, Maxime Ripard wrote:

The SinA33 comes with an optional 7" display. Enable it in the
configuration.

Signed-off-by: Maxime Ripard 


LGTM:

Reviewed-by: Hans de Goede 

Regards,

Hans




---
 configs/Sinlinx_SinA33_defconfig | 4 
 1 file changed, 4 insertions(+), 0 deletions(-)

diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig
index f4719db2d501..26b119a9b92f 100644
--- a/configs/Sinlinx_SinA33_defconfig
+++ b/configs/Sinlinx_SinA33_defconfig
@@ -6,6 +6,10 @@ CONFIG_DRAM_ZQ=15291
 CONFIG_MMC0_CD_PIN="PB4"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 CONFIG_USB0_ID_DET="PH8"
+CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:66000,le:90,ri:160,up:3,lo:127,hs:70,vs:20,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_DCLK_PHASE=0
+CONFIG_VIDEO_LCD_BL_EN="PH6"
+CONFIG_VIDEO_LCD_BL_PWM="PH0"
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-sinlinx-sina33"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y


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Re: [U-Boot] [PATCH] sunxi: mmc: Set CONFIG_SYS_MMC_MAX_DEVICE

[Hans de Goede]

Hi,

On 05-11-16 20:51, Emmanuel Vadot wrote:

Set CONFIG_SYS_MMC_MAX_DEVICE to 4 for sunxi SoC.
This define is needed in the API code.

Signed-off-by: Emmanuel Vadot 


LGTM:

Reviewed-by: Hans de Goede 

Regards,

Hans



---
 include/configs/sunxi-common.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 8363414..edb3ff7 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -145,6 +145,7 @@
 #define CONFIG_MMC_SUNXI_SLOT  0
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV 0   /* first detected MMC 
controller */
+#define CONFIG_SYS_MMC_MAX_DEVICE  4
 #endif

 /* 64MB of malloc() pool */


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Re: [U-Boot] [PATCH 3/4] sunxi: sina33: Enable the eMMC

[Hans de Goede]

Hi,

On 04-11-16 16:18, Maxime Ripard wrote:

The SinA33 has an 4GB Toshiba eMMC connected to the MMC2 controller.
Enable it.

Signed-off-by: Maxime Ripard 


LGTM:

Reviewed-by: Hans de Goede 

Regards,

Hans



---
 configs/Sinlinx_SinA33_defconfig | 1 +
 1 file changed, 1 insertion(+), 0 deletions(-)

diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig
index 2a5f985dd303..f4719db2d501 100644
--- a/configs/Sinlinx_SinA33_defconfig
+++ b/configs/Sinlinx_SinA33_defconfig
@@ -4,6 +4,7 @@ CONFIG_MACH_SUN8I_A33=y
 CONFIG_DRAM_CLK=552
 CONFIG_DRAM_ZQ=15291
 CONFIG_MMC0_CD_PIN="PB4"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 CONFIG_USB0_ID_DET="PH8"
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-sinlinx-sina33"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set


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[U-Boot] [PATCH v2 2/4] buildman: Add an option to just create the config

[Simon Glass]

Normally buildman does a full build of a board. This includes creating the
u-boot.cfg file which contains all the configuration options. Buildman uses
this file with the -K option, to show differences in effective configuration
for each commit.

Doing a full build of U-Boot just to create the u-boot.cfg file is wasteful.
Add a -D option which causes buildman to only create the configuration. This
is enough to support use of -K and can be done much more quickly (typically
5-10 times faster).

Signed-off-by: Simon Glass 
---

Changes in v2:
- Fix failure to reconfigure when needed

 tools/buildman/builder.py   |  5 -
 tools/buildman/builderthread.py | 14 +-
 tools/buildman/cmdline.py   |  2 ++
 tools/buildman/control.py   |  3 ++-
 4 files changed, 17 insertions(+), 7 deletions(-)

diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py
index e27a285..d834d31 100644
--- a/tools/buildman/builder.py
+++ b/tools/buildman/builder.py
@@ -207,7 +207,8 @@ class Builder:
 def __init__(self, toolchains, base_dir, git_dir, num_threads, num_jobs,
  gnu_make='make', checkout=True, show_unknown=True, step=1,
  no_subdirs=False, full_path=False, verbose_build=False,
- incremental=False, per_board_out_dir=False):
+ incremental=False, per_board_out_dir=False,
+ config_only=False):
 """Create a new Builder object
 
 Args:
@@ -230,6 +231,7 @@ class Builder:
 mrproper when configuring
 per_board_out_dir: Build in a separate persistent directory per
 board rather than a thread-specific directory
+config_only: Only configure each build, don't build it
 """
 self.toolchains = toolchains
 self.base_dir = base_dir
@@ -257,6 +259,7 @@ class Builder:
 self.no_subdirs = no_subdirs
 self.full_path = full_path
 self.verbose_build = verbose_build
+self.config_only = config_only
 
 self.col = terminal.Color()
 
diff --git a/tools/buildman/builderthread.py b/tools/buildman/builderthread.py
index 8974351..926f267 100644
--- a/tools/buildman/builderthread.py
+++ b/tools/buildman/builderthread.py
@@ -110,8 +110,8 @@ class BuilderThread(threading.Thread):
 return self.builder.do_make(commit, brd, stage, cwd, *args,
 **kwargs)
 
-def RunCommit(self, commit_upto, brd, work_dir, do_config, force_build,
-  force_build_failures):
+def RunCommit(self, commit_upto, brd, work_dir, do_config, do_build,
+  force_build, force_build_failures):
 """Build a particular commit.
 
 If the build is already done, and we are not forcing a build, we skip
@@ -122,6 +122,7 @@ class BuilderThread(threading.Thread):
 brd: Board object to build
 work_dir: Directory to which the source will be checked out
 do_config: True to run a make _defconfig on the source
+do_build: Try to build the source
 force_build: Force a build even if one was previously done
 force_build_failures: Force a bulid if the previous result showed
 failure
@@ -231,6 +232,8 @@ class BuilderThread(threading.Thread):
 config_out += result.combined
 do_config = False   # No need to configure next time
 if result.return_code == 0:
+if not do_build:
+args.append('cfg')
 result = self.Make(commit, brd, 'build', cwd, *args,
 env=env)
 result.stderr = result.stderr.replace(src_dir + '/', '')
@@ -401,7 +404,7 @@ class BuilderThread(threading.Thread):
 force_build = False
 for commit_upto in range(0, len(job.commits), job.step):
 result, request_config = self.RunCommit(commit_upto, brd,
-work_dir, do_config,
+work_dir, do_config, not self.builder.config_only,
 force_build or self.builder.force_build,
 self.builder.force_build_failures)
 failed = result.return_code or result.stderr
@@ -411,7 +414,7 @@ class BuilderThread(threading.Thread):
 # with a reconfig.
 if self.builder.force_config_on_failure:
 result, request_config = self.RunCommit(commit_upto,
-brd, work_dir, True, True, False)
+brd, work_dir, True, False, True, False)
 did_config = True
 if not self.builder.force_reconfig:
 do_config = request_config
@@ -455,7 +458,8 @@ class BuilderThread(threading.Thread):
 else:
 # Just build the currently checked-out build
 result, request_config = 

[U-Boot] [PATCH v2 4/4] buildman: Squash useless output from -K

[Simon Glass]

When using #define CONFIG_SOME_OPTION, the value it set to '1'. When using
defconfig (i.e. CONFIG_SOME_OPTION=y) the value is set to 'y'. This results
in differences showing up with -K. These differences are seldom useful.

Adjust buildman to suppress these differences by default.

Signed-off-by: Simon Glass 
---

Changes in v2:
- Drop patches previously applied

 tools/buildman/README | 12 
 tools/buildman/builder.py | 34 ++
 tools/buildman/cmdline.py |  2 ++
 tools/buildman/control.py |  3 ++-
 4 files changed, 38 insertions(+), 13 deletions(-)

diff --git a/tools/buildman/README b/tools/buildman/README
index 89df94d..62ab7b7 100644
--- a/tools/buildman/README
+++ b/tools/buildman/README
@@ -1004,6 +1004,18 @@ configuration you can in fact avoid doing a full build, 
using -D. This tells
 buildman to configuration U-Boot and create the .cfg files, but not actually
 build the source. This is 5-10 times faster than doing a full build.
 
+By default buildman considers the follow two configuration methods
+equivalent:
+
+   #define CONFIG_SOME_OPTION
+
+   CONFIG_SOME_OPTION=y
+
+The former would appear in a header filer and the latter in a defconfig
+file. The achieve this, buildman considers 'y' to be '1' in configuration
+variables. This avoids lots of useless output when converting a CONFIG
+option to Kconfig. To disable this behaviour, use --squash-config-y.
+
 
 Other options
 =
diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py
index d834d31..6905ed9 100644
--- a/tools/buildman/builder.py
+++ b/tools/buildman/builder.py
@@ -98,19 +98,22 @@ OUTCOME_OK, OUTCOME_WARNING, OUTCOME_ERROR, OUTCOME_UNKNOWN 
= range(4)
 # Translate a commit subject into a valid filename
 trans_valid_chars = string.maketrans("/: ", "---")
 
-CONFIG_FILENAMES = [
+BASE_CONFIG_FILENAMES = [
+'u-boot.cfg', 'u-boot-spl.cfg', 'u-boot-tpl.cfg'
+]
+
+EXTRA_CONFIG_FILENAMES = [
 '.config', '.config-spl', '.config-tpl',
 'autoconf.mk', 'autoconf-spl.mk', 'autoconf-tpl.mk',
 'autoconf.h', 'autoconf-spl.h','autoconf-tpl.h',
-'u-boot.cfg', 'u-boot-spl.cfg', 'u-boot-tpl.cfg'
 ]
 
 class Config:
 """Holds information about configuration settings for a board."""
-def __init__(self, target):
+def __init__(self, config_filename, target):
 self.target = target
 self.config = {}
-for fname in CONFIG_FILENAMES:
+for fname in config_filename:
 self.config[fname] = {}
 
 def Add(self, fname, key, value):
@@ -208,7 +211,7 @@ class Builder:
  gnu_make='make', checkout=True, show_unknown=True, step=1,
  no_subdirs=False, full_path=False, verbose_build=False,
  incremental=False, per_board_out_dir=False,
- config_only=False):
+ config_only=False, squash_config_y=False):
 """Create a new Builder object
 
 Args:
@@ -232,6 +235,7 @@ class Builder:
 per_board_out_dir: Build in a separate persistent directory per
 board rather than a thread-specific directory
 config_only: Only configure each build, don't build it
+squash_config_y: Convert CONFIG options with the value 'y' to '1'
 """
 self.toolchains = toolchains
 self.base_dir = base_dir
@@ -260,6 +264,10 @@ class Builder:
 self.full_path = full_path
 self.verbose_build = verbose_build
 self.config_only = config_only
+self.squash_config_y = squash_config_y
+self.config_filenames = BASE_CONFIG_FILENAMES
+if not self.squash_config_y:
+self.config_filenames += EXTRA_CONFIG_FILENAMES
 
 self.col = terminal.Color()
 
@@ -586,13 +594,15 @@ class Builder:
 key, value = values
 else:
 key = values[0]
-value = ''
+value = '1' if self.squash_config_y else ''
 if not key.startswith('CONFIG_'):
 continue
 elif not line or line[0] in ['#', '*', '/']:
 continue
 else:
 key, value = line.split('=', 1)
+if self.squash_config_y and value == 'y':
+value = '1'
 config[key] = value
 return config
 
@@ -659,7 +669,7 @@ class Builder:
 
 if read_config:
 output_dir = self.GetBuildDir(commit_upto, target)
-for name in CONFIG_FILENAMES:
+for name in self.config_filenames:
 fname = os.path.join(output_dir, name)
 config[name] = self._ProcessConfig(fname)
 
@@ -736,8 +746,8 @@ class Builder:
 line, board)
 last_was_warning = 

[U-Boot] [PATCH v2 3/4] buildman: Add documentation for CONFIG checking

[Simon Glass]

The -K option is not mentioned in the README at present. Add some notes
to describe how this is used.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 tools/buildman/README | 37 +
 1 file changed, 37 insertions(+)

diff --git a/tools/buildman/README b/tools/buildman/README
index 514bebc..89df94d 100644
--- a/tools/buildman/README
+++ b/tools/buildman/README
@@ -968,6 +968,43 @@ of the source tree, thus allowing rapid tested evolution 
of the code.
 SOURCE_DATE_EPOCH=0 ./tools/buildman/buildman -I -P tegra
 
 
+Checking configuration
+==
+
+A common requirement when converting CONFIG options to Kconfig is to check
+that the effective configuration has not changed due to the conversion.
+Buildman supports this with the -K option, used after a build. This shows
+differences in effective configuration between one commit and the next.
+
+For example:
+
+$ buildman -b kc4 -sK
+...
+43: Convert CONFIG_SPL_USBETH_SUPPORT to Kconfig
+arm:
++ u-boot.cfg: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_NET_SUPPORT=1
++ u-boot-spl.cfg: CONFIG_SPL_MMC_SUPPORT=1 CONFIG_SPL_NAND_SUPPORT=1
++ all: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_MMC_SUPPORT=1 
CONFIG_SPL_NAND_SUPPORT=1 CONFIG_SPL_NET_SUPPORT=1
+am335x_evm_usbspl :
++ u-boot.cfg: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_NET_SUPPORT=1
++ u-boot-spl.cfg: CONFIG_SPL_MMC_SUPPORT=1 CONFIG_SPL_NAND_SUPPORT=1
++ all: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_MMC_SUPPORT=1 
CONFIG_SPL_NAND_SUPPORT=1 CONFIG_SPL_NET_SUPPORT=1
+44: Convert CONFIG_SPL_USB_HOST_SUPPORT to Kconfig
+...
+
+This shows that commit 44 enabled three new options for the board
+am335x_evm_usbspl which were not enabled in commit 43. There is also a
+summary for 'arm' showing all the changes detected for that architecture.
+In this case there is only one board with changes, so 'arm' output is the
+same as 'am335x_evm_usbspl'/
+
+The -K option uses the u-boot.cfg, spl/u-boot-spl.cfg and tpl/u-boot-tpl.cfg
+files which are produced by a build. If all you want is to check the
+configuration you can in fact avoid doing a full build, using -D. This tells
+buildman to configuration U-Boot and create the .cfg files, but not actually
+build the source. This is 5-10 times faster than doing a full build.
+
+
 Other options
 =
 
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH] fastboot: simplify the Kconfig logic

[Yann E. MORIN]

Currently, the fastboot item in menuconfig is a comment followed by a
boolean option withan empty prompt, followed by a menu:

*** FASTBOOT ***
[*]
  Fastboot support  --->

This is not "nice-looking" at all...

Change the logic to make the boolean option a "menuconfig" rather than a
mere "config", so that all dependent options gets groupped under a menu.
The layout is now:

*** FASTBOOT ***
[*] Fastboot support  --->

Signed-off-by: "Yann E. MORIN" 
Cc: Simon Glass 
---
 cmd/fastboot/Kconfig | 9 -
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/cmd/fastboot/Kconfig b/cmd/fastboot/Kconfig
index 5d2facc..b806902 100644
--- a/cmd/fastboot/Kconfig
+++ b/cmd/fastboot/Kconfig
@@ -1,10 +1,9 @@
 comment "FASTBOOT"
 
-config FASTBOOT
-   bool ""
+menuconfig FASTBOOT
+   bool "Fastboot support"
 
-menu "Fastboot support"
-   depends on FASTBOOT
+if FASTBOOT
 
 config USB_FUNCTION_FASTBOOT
bool "Enable USB fastboot gadget"
@@ -81,4 +80,4 @@ config FASTBOOT_MBR_NAME
 
 endif # USB_FUNCTION_FASTBOOT
 
-endmenu
+endif # FASTBOOT
-- 
2.7.4

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Re: [U-Boot] [PATCH 1/4] mmc: Retry the switch command

[Hans de Goede]

Hi,

On 04-11-16 16:18, Maxime Ripard wrote:

Some eMMC will fail at the first switch, but would succeed in a subsequent
one.

Make sure we try several times to cover those cases. The number of retries
(and the behaviour) is currently what is being used in Linux.

Signed-off-by: Maxime Ripard 


LGTM:

Reviewed-by: Hans de Goede 

Pantelis or Tom, can you pick this up please ?

Regards,

Hans



---
 drivers/mmc/mmc.c | 15 +++
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 4380c7c195a6..d6b7e4f510c9 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -494,6 +494,7 @@ int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
 {
struct mmc_cmd cmd;
int timeout = 1000;
+   int retries = 3;
int ret;

cmd.cmdidx = MMC_CMD_SWITCH;
@@ -502,11 +503,17 @@ int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 
value)
 (index << 16) |
 (value << 8);

-   ret = mmc_send_cmd(mmc, , NULL);
+   while (retries > 0) {
+   ret = mmc_send_cmd(mmc, , NULL);

-   /* Waiting for the ready status */
-   if (!ret)
-   ret = mmc_send_status(mmc, timeout);
+   /* Waiting for the ready status */
+   if (!ret) {
+   ret = mmc_send_status(mmc, timeout);
+   return ret;
+   }
+
+   retries--;
+   }

return ret;



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Re: [U-Boot] [PATCH 2/4] mmc: sunxi: Enable 8bits bus width for sun8i

[Hans de Goede]

Hi,

On 04-11-16 16:18, Maxime Ripard wrote:

The sun8i SoCs also have a 8 bits capable MMC2 controller. Enable the
support for those too.

Signed-off-by: Maxime Ripard 


LGTM:

Reviewed-by: Hans de Goede 

Regards,

Hans



---
 drivers/mmc/sunxi_mmc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 6953accce123..b8716c93cb06 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -463,7 +463,7 @@ struct mmc *sunxi_mmc_init(int sdc_no)

cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
cfg->host_caps = MMC_MODE_4BIT;
-#ifdef CONFIG_MACH_SUN50I
+#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I)
if (sdc_no == 2)
cfg->host_caps = MMC_MODE_8BIT;
 #endif


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[U-Boot] [PATCH] sunxi: Mele_M5_defconfig: Drop non existing STATUSLED setting

[Hans de Goede]

And also remove it from scripts/config_whitelist.txt as the
Mele_M5_defconfig was the only one defining it.

Signed-off-by: Hans de Goede 
---
 configs/Mele_M5_defconfig| 2 +-
 scripts/config_whitelist.txt | 1 -
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/configs/Mele_M5_defconfig b/configs/Mele_M5_defconfig
index fffc332..09addc5 100644
--- a/configs/Mele_M5_defconfig
+++ b/configs/Mele_M5_defconfig
@@ -9,7 +9,7 @@ CONFIG_VIDEO_COMPOSITE=y
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m5"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_AHCI=y
-CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,STATUSLED=234"
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
 CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index d476367..5a471fe 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -4329,7 +4329,6 @@ CONFIG_STAMP_CF
 CONFIG_STANDALONE_LOAD_ADDR
 CONFIG_STATIC_BOARD_REV
 CONFIG_STATIC_RELA
-CONFIG_STATUSLED
 CONFIG_STATUS_LED
 CONFIG_STD_DEVICES_SETTINGS
 CONFIG_STK52XX
-- 
2.9.3

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Re: [U-Boot] [PATCH 05/10] sunxi: Add PRCM register definition for sun9i/A80

[Hans de Goede]

Hi,

On 09-11-16 11:21, Chen-Yu Tsai wrote:

The A80 has a different PRCM register layout.

Signed-off-by: Chen-Yu Tsai 


LGTM:

Reviewed-by: Hans de Goede 

Regards,

Hans



---
 arch/arm/include/asm/arch-sunxi/prcm_sun9i.h | 55 
 1 file changed, 55 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-sunxi/prcm_sun9i.h

diff --git a/arch/arm/include/asm/arch-sunxi/prcm_sun9i.h 
b/arch/arm/include/asm/arch-sunxi/prcm_sun9i.h
new file mode 100644
index ..f4732335fbcc
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/prcm_sun9i.h
@@ -0,0 +1,55 @@
+/*
+ * Sunxi A80 Power Reset and Clock Module register definition
+ *
+ * (C) Copyright 2016 Chen-Yu Tsai 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _SUNXI_PRCM_SUN9I_H
+#define _SUNXI_PRCM_SUN9I_H
+
+struct __packed sunxi_prcm_reg {
+   u32 cpus_rst;   /* 0x000 */
+   u32 cpu_rst[2]; /* 0x004 */
+   u8 res0[0x4];   /* 0x00c */
+   u32 cpus_cfg;   /* 0x010 */
+   u8 res1[0x8];   /* 0x014 */
+   u32 apbs_ratio; /* 0x01c */
+   u8 res2[0x8];   /* 0x020 */
+   u32 apbs_gate;  /* 0x028 */
+   u8 res3[0x18];  /* 0x02c */
+   u32 pll_ctrl1;  /* 0x044 */
+   u8 res4[0xc];   /* 0x048 */
+   u32 clk_cir;/* 0x054 */
+   u32 clk_i2s0;   /* 0x058 */
+   u32 clk_i2s1;   /* 0x05c */
+   u8 res5[0x50];  /* 0x060 */
+   u32 apb0_reset; /* 0x0b0 */
+   u8 res6[0x4c];  /* 0x0b4 */
+   u32 cpu_pwroff[2];  /* 0x100 */
+   u8 res7[0x8];   /* 0x108 */
+   u32 vdd_sys_pwroff; /* 0x110 */
+   u8 res8[0x4];   /* 0x114 */
+   u32 gpu_pwroff; /* 0x118 */
+   u8 res9[0x4];   /* 0x11c */
+   u32 vdd_sys_rst;/* 0x120 */
+   u8 res10[0x1c]; /* 0x124 */
+   u32 cpu_pwr_clamp[2][4]; /* 0x140 */
+   u32 super_standby_flag; /* 0x160 */
+   u32 cpu_soft_entry; /* 0x164 */
+   u32 super_standby_entry; /* 0x168 */
+   u8 res11[0x34]; /* 0x16c */
+   u32 nmi_irq_ctrl;   /* 0x1a0 */
+   u32 nmi_irq_en; /* 0x1a4 */
+   u32 nmi_irq_status; /* 0x1a8 */
+   u8 res12[0x14]; /* 0x1ac */
+   u32 pll_audio_ctrl; /* 0x1c0 */
+   u32 pll_audio_bias; /* 0x1c4 */
+   u32 pll_audio_pat_cfg;  /* 0x1c8 */
+   u32 pll_audio_ctrl_sw;  /* 0x1cc */
+   u8 res13[0x20]; /* 0x1d0 */
+   u32 osc24m_ctrl;/* 0x1f0 */
+};
+
+#endif /* _SUNXI_PRCM_SUN9I_H */


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Re: [U-Boot] [PATCH 06/10] sunxi: Add CPUCFG register definitions for sun9i/A80

[Hans de Goede]

Hi,

On 09-11-16 11:21, Chen-Yu Tsai wrote:

The A80 has a different CPUCFG register layout, likely due to having
2 clusters.

Signed-off-by: Chen-Yu Tsai 


LGTM:

Reviewed-by: Hans de Goede 

Regards,

Hans



---
 arch/arm/include/asm/arch-sunxi/cpucfg_sun9i.h | 51 ++
 1 file changed, 51 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-sunxi/cpucfg_sun9i.h

diff --git a/arch/arm/include/asm/arch-sunxi/cpucfg_sun9i.h 
b/arch/arm/include/asm/arch-sunxi/cpucfg_sun9i.h
new file mode 100644
index ..0ee6a63e441b
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/cpucfg_sun9i.h
@@ -0,0 +1,51 @@
+/*
+ * Sunxi A80 CPUCFG register definition.
+ *
+ * (C) Copyright 2016 Chen-Yu Tsai 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _SUNXI_CPUCFG_SUN9I_H
+#define _SUNXI_CPUCFG_SUN9I_H
+
+#include 
+#include 
+
+#define CPUCFG_CX_CTRL0_L1_RST_DISABLE(core)   BIT(core)
+
+#define CPUCFG_CX_STATUS_STANDBYWFI(core)  BIT(16 + core)
+
+#define CPUCFG_CX_RST_CORE(core)   BIT(core)
+#define CPUCFG_CX_RST_NEON(core)   BIT(4 + core) /* A15 only */
+#define CPUCFG_CX_RST_L2   BIT(8)
+#define CPUCFG_CX_RST_HRESET   BIT(12)
+#define CPUCFG_CX_RST_DBG(core)BIT(16 + core)
+#define CPUCFG_CX_RST_ETM(core)BIT(20 + core)
+#define CPUCFG_CX_RST_SOC_DBG  BIT(24)
+
+#ifndef __ASSEMBLY__
+
+struct __packed sunxi_cpucfg_cluster {
+   u32 ctrl0;  /* base + 0x0 */
+   u32 ctrl1;  /* base + 0x4 */
+   u32 adb400_pwrdnreqn;   /* base + 0x8 */
+   u8 res[0x4];/* base + 0xc */
+};
+
+struct __packed sunxi_cpucfg_reg {
+   struct sunxi_cpucfg_cluster cluster[2]; /* 0x00 */
+   u8 res0[0x8];   /* 0x20 */
+   u32 gen_ctrl0;  /* 0x28 */
+   u32 gen_ctrl1;  /* 0x2c */
+   u32 cluster_status[2];  /* 0x30 */
+   u8 res1[0x4];   /* 0x38 */
+   u32 irq_fiq_status; /* 0x3c */
+   u32 irq_fiq_mask;   /* 0x40 */
+   u8 res2[0x3c];  /* 0x44 */
+   u32 cluster_reset[2];   /* 0x80 */
+   u32 gic_jtag_reset; /* 0x88 */
+};
+
+#endif /* __ASSEMBLY__ */
+#endif /* _SUNXI_CPUCFG_SUN9I_H */


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Re: [U-Boot] [PATCH 02/10] sunxi: Add CCI-400 and CPUCFG registers base address for sun9i/A80

[Hans de Goede]

Hi,

On 09-11-16 11:21, Chen-Yu Tsai wrote:

The A80, having 2 clusters of 4 cores each, has an ARM CCI-400 hardware
block for cache coherency.

Add the base address for CCI-400, and also add the base address for CPUCFG.

Signed-off-by: Chen-Yu Tsai 


LGTM:

Reviewed-by: Hans de Goede 

Regards,

Hans

---
 arch/arm/include/asm/arch-sunxi/cpu_sun9i.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h 
b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
index c775bcc515a0..88b48c644c06 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
@@ -17,6 +17,9 @@
 #define REGS_APB1_BASE 0x0700
 #define REGS_RCPUS_BASE0x0800

+#define SUNXI_CPUCFG_BASE  0x0170
+#define SUNXI_CCI400_BASE  0x0179
+
 #define SUNXI_SRAM_D_BASE  0x0810

 /* AHB0 Module */


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Re: [U-Boot] [PATCH 03/10] sunxi: Add base address of secure SRAM B for sun9i/A80

[Hans de Goede]

Hi,

On 09-11-16 11:21, Chen-Yu Tsai wrote:

The A80 has a 256 kiB secure SRAM. However the first 4 kiB are reserved
for CPU0 hotplug flags.

Signed-off-by: Chen-Yu Tsai 


LGTM:

Reviewed-by: Hans de Goede 

Regards,

Hans



---
 arch/arm/include/asm/arch-sunxi/cpu_sun9i.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h 
b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
index 88b48c644c06..e9839eecaa92 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
@@ -20,6 +20,7 @@
 #define SUNXI_CPUCFG_BASE  0x0170
 #define SUNXI_CCI400_BASE  0x0179

+#define SUNXI_SRAM_B_BASE  0x0002
 #define SUNXI_SRAM_D_BASE  0x0810

 /* AHB0 Module */


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Re: [U-Boot] [PATCH 01/10] ARM: PSCI: Set ARMV7_PSCI_NR_CPUS default to 8 for sun9i/A80

[Hans de Goede]

Hi,

On 09-11-16 11:21, Chen-Yu Tsai wrote:

The A80 is a big.LITTLE SoC with 4x Cortex-A7 in cluster 0 and 4x
Cortex-A15 in cluster 1.

Signed-off-by: Chen-Yu Tsai 


LGTM:

Reviewed-by: Hans de Goede 

Regards,

Hans



---
 arch/arm/cpu/armv7/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig
index b9c4f4e79b9b..e37f1f328a34 100644
--- a/arch/arm/cpu/armv7/Kconfig
+++ b/arch/arm/cpu/armv7/Kconfig
@@ -44,6 +44,7 @@ config ARMV7_PSCI
 config ARMV7_PSCI_NR_CPUS
int "Maximum supported CPUs for PSCI"
depends on ARMV7_NONSEC
+   default 8 if MACH_SUN9I
default 4
help
  The maximum number of CPUs supported in the PSCI firmware.


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[U-Boot] FDT retrived varaibles appear to have different properties fom other u-boot variables

[dh]

I have retrieved a string  "fdt get value bootargs /chosen bootargs" 

But, when I try "setenv a $bootargs" I get the error message:
setenv [-f] name value...
Is appears the variable set by the "fdt get" command hasdifferent properties 
from a u-boot variable where the content are available with $ operator.
The string variables retrieved with the fdt command appear to have different 
properties then strings in the u-boot variables. 

I can printenv bootargs, I cannot append to it by 
setenv ip ip=102.168.1.97
"setenv a $bootargs $ip"

Is this by design or is it a bug?

Duncan Hare

714 931 7952

 

   
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Re: [U-Boot] [PATCH] sunxi: Mele_M5_defconfig: Drop non existing STATUSLED setting

[Ian Campbell]

On Sun, 2016-11-13 at 19:54 +0100, Hans de Goede wrote:
> And also remove it from scripts/config_whitelist.txt as the
> Mele_M5_defconfig was the only one defining it.
> 
> Signed-off-by: Hans de Goede 

Acked-by: Ian Campbell 

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Re: [U-Boot] board: am335x/mux: Do not hang when encountering a bad EEPROM

[Tom Rini]

On Tue, Nov 08, 2016 at 08:48:44PM -0800, Alex G. wrote:

> In most cases, the SPL and u-boot.img will be on the same boot media.
> Since the SPL was loaded by the boot rom, the pinmux will already have
> been configured for this media. This, the board will still be able to
> boot successfully, or at least reach the u-boot console, where more
> recovery options are available.
> 
> I've encountered this on a beaglebone black with a corrupted EEPROM.
> Removing this check allowed the board to boot successfully. I've also
> seen this on EVM-based boards with an unprogrammed EEPROM. On those
> boards, for some reason there were no UART messages. This made it look
> as if the SOC was dead.
> 
> Remove the hang(), as it is not a fatal error. Also reformat the error
> message to be clearer as to the cause. The original message made it
> appear as if the wrong binary was being loaded.
> 
> Signed-off-by: Alexandru Gagniuc 
> Reviewed-by: Tom Rini 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [U-Boot] ARM: keystone2: PLL: Enable glitch free initialization sequence

[Tom Rini]

On Thu, Nov 03, 2016 at 03:32:51PM +0530, Lokesh Vutla wrote:

> Update the PLL initialization sequence to avoid glitches while
> programming. User guide for the same is available at[1].
> 
> [1] http://www.ti.com/lit/ug/sprugv2h/sprugv2h.pdf
> 
> Signed-off-by: Lokesh Vutla 
> Reviewed-by: Tom Rini 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [U-Boot] davinci: omapl138_lcdk: keep booting even when MAC address is invalid

[Tom Rini]

On Thu, Nov 10, 2016 at 05:16:35PM +0100, Fabien Parent wrote:

> If the MAC address specified on the EEPROM is invalid (multicast or
> zero address), then u-boot fails to boot. Having a bad MAC address
> in the EEPROM should not prevent the system from booting.
> 
> This commit changes the error path to just print an error messages
> in case of bad MAC address.
> 
> Signed-off-by: Fabien Parent 
> Reviewed-by: Tom Rini 

Applied to u-boot/master, thanks!

-- 
Tom


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[U-Boot] [PATCH v2 16/22] rockchip: Rename jerry files to veyron

[Simon Glass]

At present we have a single rk3288-based Chromebook: chromebook_jerry. But
all such Chromebooks can use the same binary with only device-tree
differences. The family name is 'veyron', so rename the files accordingly.

Also update the device-tree filename since this currently differs from
Linux.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 arch/arm/dts/Makefile  | 2 +-
 arch/arm/dts/{rk3288-jerry.dts => rk3288-veyron-jerry.dts} | 0
 arch/arm/mach-rockchip/rk3288/Kconfig  | 2 +-
 board/google/{chromebook_jerry => veyron}/Kconfig  | 4 ++--
 board/google/{chromebook_jerry => veyron}/MAINTAINERS  | 4 ++--
 board/google/{chromebook_jerry => veyron}/Makefile | 2 +-
 board/google/{chromebook_jerry/jerry.c => veyron/veyron.c} | 0
 configs/chromebook_jerry_defconfig | 2 +-
 include/configs/{chromebook_jerry.h => veyron.h}   | 0
 9 files changed, 8 insertions(+), 8 deletions(-)
 rename arch/arm/dts/{rk3288-jerry.dts => rk3288-veyron-jerry.dts} (100%)
 rename board/google/{chromebook_jerry => veyron}/Kconfig (74%)
 rename board/google/{chromebook_jerry => veyron}/MAINTAINERS (60%)
 rename board/google/{chromebook_jerry => veyron}/Makefile (81%)
 rename board/google/{chromebook_jerry/jerry.c => veyron/veyron.c} (100%)
 rename include/configs/{chromebook_jerry.h => veyron.h} (100%)

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 836a8c4..af8b0de 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -29,7 +29,7 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
 dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-firefly.dtb \
-   rk3288-jerry.dtb \
+   rk3288-veyron-jerry.dtb \
rk3288-rock2-square.dtb \
rk3288-evb.dtb \
rk3288-fennec.dtb \
diff --git a/arch/arm/dts/rk3288-jerry.dts 
b/arch/arm/dts/rk3288-veyron-jerry.dts
similarity index 100%
rename from arch/arm/dts/rk3288-jerry.dts
rename to arch/arm/dts/rk3288-veyron-jerry.dts
diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig 
b/arch/arm/mach-rockchip/rk3288/Kconfig
index c53d2e2..30c557b 100644
--- a/arch/arm/mach-rockchip/rk3288/Kconfig
+++ b/arch/arm/mach-rockchip/rk3288/Kconfig
@@ -88,7 +88,7 @@ source "board/chipspark/popmetal_rk3288/Kconfig"
 
 source "board/firefly/firefly-rk3288/Kconfig"
 
-source "board/google/chromebook_jerry/Kconfig"
+source "board/google/veyron/Kconfig"
 
 source "board/radxa/rock2/Kconfig"
 
diff --git a/board/google/chromebook_jerry/Kconfig b/board/google/veyron/Kconfig
similarity index 74%
rename from board/google/chromebook_jerry/Kconfig
rename to board/google/veyron/Kconfig
index 3640513..b1f51ce 100644
--- a/board/google/chromebook_jerry/Kconfig
+++ b/board/google/veyron/Kconfig
@@ -1,13 +1,13 @@
 if TARGET_CHROMEBOOK_JERRY
 
 config SYS_BOARD
-   default "chromebook_jerry"
+   default "veyron"
 
 config SYS_VENDOR
default "google"
 
 config SYS_CONFIG_NAME
-   default "chromebook_jerry"
+   default "veyron"
 
 config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
diff --git a/board/google/chromebook_jerry/MAINTAINERS 
b/board/google/veyron/MAINTAINERS
similarity index 60%
rename from board/google/chromebook_jerry/MAINTAINERS
rename to board/google/veyron/MAINTAINERS
index b01b6cd..d641eed 100644
--- a/board/google/chromebook_jerry/MAINTAINERS
+++ b/board/google/veyron/MAINTAINERS
@@ -1,6 +1,6 @@
 CHROMEBOOK JERRY BOARD
 M: Simon Glass 
 S: Maintained
-F: board/google/chromebook_jerry/
-F: include/configs/chromebook_jerry.h
+F: board/google/veyron/
+F: include/configs/veyron.h
 F: configs/chromebook_jerry_defconfig
diff --git a/board/google/chromebook_jerry/Makefile 
b/board/google/veyron/Makefile
similarity index 81%
rename from board/google/chromebook_jerry/Makefile
rename to board/google/veyron/Makefile
index d29a063..9868357 100644
--- a/board/google/chromebook_jerry/Makefile
+++ b/board/google/veyron/Makefile
@@ -4,4 +4,4 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-y  += jerry.o
+obj-y  += veyron.o
diff --git a/board/google/chromebook_jerry/jerry.c 
b/board/google/veyron/veyron.c
similarity index 100%
rename from board/google/chromebook_jerry/jerry.c
rename to board/google/veyron/veyron.c
diff --git a/configs/chromebook_jerry_defconfig 
b/configs/chromebook_jerry_defconfig
index 6f4ae18..46df1a6 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -7,7 +7,7 @@ CONFIG_TARGET_CHROMEBOOK_JERRY=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_SPL_STACK_R_ADDR=0x8
-CONFIG_DEFAULT_DEVICE_TREE="rk3288-jerry"
+CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-jerry"
 CONFIG_SILENT_CONSOLE=y
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL_STACK_R=y
diff --git a/include/configs/chromebook_jerry.h b/include/configs/veyron.h
similarity index 100%

[U-Boot] [PATCH v2 12/22] video: Use cache-alignment in video_sync()

[Simon Glass]

Sometimes the frame buffer is not a multiple of the cache line size.
Adjust the cache-flushing code to avoid cache warnings/errors in this
case.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 drivers/video/video-uclass.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c
index 11ca793..3036e3a 100644
--- a/drivers/video/video-uclass.c
+++ b/drivers/video/video-uclass.c
@@ -117,7 +117,8 @@ void video_sync(struct udevice *vid)
 
if (priv->flush_dcache) {
flush_dcache_range((ulong)priv->fb,
-  (ulong)priv->fb + priv->fb_size);
+  ALIGN((ulong)priv->fb + priv->fb_size,
+CONFIG_SYS_CACHELINE_SIZE));
}
 #elif defined(CONFIG_VIDEO_SANDBOX_SDL)
struct video_priv *priv = dev_get_uclass_priv(vid);
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH v2 15/22] rockchip: Move jerry to use of-platdata

[Simon Glass]

Adjust jerry to use of-platdata like other rk3288 boards. This reduces the
SPL size enough that it boots again.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 configs/chromebook_jerry_defconfig | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/configs/chromebook_jerry_defconfig 
b/configs/chromebook_jerry_defconfig
index 876adc4..6f4ae18 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -1,12 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_SPL_MMC_SUPPORT is not set
-CONFIG_SPL_POWER_SUPPORT=y
 CONFIG_ROCKCHIP_RK3288=y
 CONFIG_TARGET_CHROMEBOOK_JERRY=y
-CONFIG_ROCKCHIP_FAST_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_SPL_STACK_R_ADDR=0x8
@@ -36,7 +33,7 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names 
interrupt-parent"
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names 
interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
 CONFIG_SYSCON=y
@@ -71,6 +68,7 @@ CONFIG_DEBUG_UART_BASE=0xff69
 CONFIG_DEBUG_UART_CLOCK=2400
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550=y
+CONFIG_ROCKCHIP_SERIAL=y
 CONFIG_ROCKCHIP_SPI=y
 CONFIG_SYSRESET=y
 CONFIG_DM_VIDEO=y
@@ -80,3 +78,5 @@ CONFIG_CONSOLE_SCROLL_LINES=10
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
+CONFIG_SPL_OF_PLATDATA=y
+# CONFIG_SPL_OF_LIBFDT is not set
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH v2 13/22] video: Track whether a display is in use

[Simon Glass]

Mark a display as in use when display_enable() is called. This can avoid
a display being used by multiple video-output devices.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 drivers/video/display-uclass.c | 18 +-
 include/display.h  | 10 ++
 2 files changed, 27 insertions(+), 1 deletion(-)

diff --git a/drivers/video/display-uclass.c b/drivers/video/display-uclass.c
index e4763de..e752eb0 100644
--- a/drivers/video/display-uclass.c
+++ b/drivers/video/display-uclass.c
@@ -23,10 +23,19 @@ int display_enable(struct udevice *dev, int panel_bpp,
const struct display_timing *timing)
 {
struct dm_display_ops *ops = display_get_ops(dev);
+   struct display_plat *disp_uc_plat;
+   int ret;
 
if (!ops || !ops->enable)
return -ENOSYS;
-   return ops->enable(dev, panel_bpp, timing);
+   ret = ops->enable(dev, panel_bpp, timing);
+   if (ret)
+   return ret;
+
+   disp_uc_plat = dev_get_uclass_platdata(dev);
+   disp_uc_plat->in_use = true;
+
+   return 0;
 }
 
 int display_read_timing(struct udevice *dev, struct display_timing *timing)
@@ -48,6 +57,13 @@ int display_read_timing(struct udevice *dev, struct 
display_timing *timing)
return edid_get_timing(buf, ret, timing, _bits_per_colour);
 }
 
+bool display_in_use(struct udevice *dev)
+{
+   struct display_plat *disp_uc_plat = dev_get_uclass_platdata(dev);
+
+   return disp_uc_plat->in_use;
+}
+
 UCLASS_DRIVER(display) = {
.id = UCLASS_DISPLAY,
.name   = "display",
diff --git a/include/display.h b/include/display.h
index b1c4766..d0a08d4 100644
--- a/include/display.h
+++ b/include/display.h
@@ -16,10 +16,12 @@ struct display_timing;
  * @source_id: ID for the source of the display data, typically a video
  * controller
  * @src_dev:   Source device providing the video
+ * @in_use:Display is being used
  */
 struct display_plat {
int source_id;
struct udevice *src_dev;
+   bool in_use;
 };
 
 /**
@@ -41,6 +43,14 @@ int display_read_timing(struct udevice *dev, struct 
display_timing *timing);
 int display_enable(struct udevice *dev, int panel_bpp,
   const struct display_timing *timing);
 
+/**
+ * display_in_use() - Check if a display is in use by any device
+ *
+ * @return true if the device is in use (display_enable() has been called
+ * successfully), else false
+ */
+bool display_in_use(struct udevice *dev);
+
 struct dm_display_ops {
/**
 * read_timing() - Read information directly
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH v2 14/22] rockchip: video: Check for device in use

[Simon Glass]

Check whether a display device is in use before using it. Add a comment as
to why two displays cannot currently be used at the same time.

This allows us to remove the device-tree change that disables vopb on
jerry.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 arch/arm/dts/rk3288-jerry.dts  | 5 -
 arch/arm/dts/rk3288-veyron-chromebook.dtsi | 2 ++
 drivers/video/rockchip/rk_vop.c| 9 +
 3 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/arch/arm/dts/rk3288-jerry.dts b/arch/arm/dts/rk3288-jerry.dts
index 2aa3b9f..da37ea8 100644
--- a/arch/arm/dts/rk3288-jerry.dts
+++ b/arch/arm/dts/rk3288-jerry.dts
@@ -108,11 +108,6 @@
pinctrl-0 = <_hdmi_en>;
 };
 
- {
-   /* Disable this so that we use vopl */
-   status = "disabled";
-};
-
  {
pinctrl-names = "default";
pinctrl-0 = <_hpd>;
diff --git a/arch/arm/dts/rk3288-veyron-chromebook.dtsi 
b/arch/arm/dts/rk3288-veyron-chromebook.dtsi
index bbbc2f4..f88a868 100644
--- a/arch/arm/dts/rk3288-veyron-chromebook.dtsi
+++ b/arch/arm/dts/rk3288-veyron-chromebook.dtsi
@@ -13,6 +13,8 @@
 / {
aliases {
i2c20 = _tunnel;
+   video0 = 
+   video1 = 
};
 
gpio_keys: gpio-keys {
diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index 130dace..eab5486 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -221,6 +221,11 @@ int rk_display_init(struct udevice *dev, ulong fbbase,
 
disp_uc_plat = dev_get_uclass_platdata(disp);
debug("Found device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
+   if (display_in_use(disp)) {
+   debug("   - device in use\n");
+   return -EBUSY;
+   }
+
disp_uc_plat->source_id = remote_vop_id;
disp_uc_plat->src_dev = dev;
 
@@ -311,6 +316,10 @@ static int rk_vop_probe(struct udevice *dev)
/*
 * Try all the ports until we find one that works. In practice this
 * tries EDP first if available, then HDMI.
+*
+* Note that rockchip_vop_set_clk() always uses NPLL as the source
+* clock so it is currently not possible to use more than one display
+* device simultaneously.
 */
port = fdt_subnode_offset(blob, dev->of_offset, "port");
if (port < 0)
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH v2 19/22] rockchip: clk: Support setting ACLK

[Simon Glass]

Add basic support for setting the ARM clock, since this allows us to run
at maximum speed in U-Boot. Currently only a single speed is supported
(1.8GHz).

Signed-off-by: Simon Glass 
---

Changes in v2: None

 drivers/clk/rockchip/clk_rk3288.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3288.c 
b/drivers/clk/rockchip/clk_rk3288.c
index ed97e87..d15504c 100644
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -691,6 +691,13 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong 
rate)
 
gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
switch (clk->id) {
+   case PLL_APLL:
+   /* We only support a fixed rate here */
+   if (rate != 18)
+   return -EINVAL;
+   rk3288_clk_configure_cpu(priv->cru, priv->grf);
+   new_rate = rate;
+   break;
case CLK_DDR:
new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate);
break;
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH v2 17/22] rockchip: veyron: Add a note about the SDRAM voltage

[Simon Glass]

Add a comment to indicate that we are not supporting the PWM regulator
yet.

Signed-off-by: Simon Glass 
---

Changes in v2:
- Add new patch with note about the SDRAM voltage

 board/google/veyron/veyron.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/board/google/veyron/veyron.c b/board/google/veyron/veyron.c
index 5119e95..20297e1 100644
--- a/board/google/veyron/veyron.c
+++ b/board/google/veyron/veyron.c
@@ -5,3 +5,9 @@
  */
 
 #include 
+
+/*
+ * We should increase the DDR voltage to 1.2V using the PWM regulator.
+ * There is a U-Boot driver for this but it may need to add support for the
+ * 'voltage-table' property.
+ */
-- 
2.8.0.rc3.226.g39d4020

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Re: [U-Boot] [PATCH 07/10] sunxi: Add support for TZPC on sun9i/A80

[Hans de Goede]

Hi,

On 09-11-16 11:21, Chen-Yu Tsai wrote:

The A80 also has the TrustZone Protection Controller (TZPC), called
the Secure Memory Touch Arbiter (SMTA).

Enable non-secure access to all the peripherals at boot time.

Signed-off-by: Chen-Yu Tsai 


LGTM:

Reviewed-by: Hans de Goede 

Regards,

Hans




---
 arch/arm/cpu/armv7/sunxi/Makefile   | 1 +
 arch/arm/cpu/armv7/sunxi/tzpc.c | 6 ++
 arch/arm/include/asm/arch-sunxi/cpu_sun9i.h | 1 +
 arch/arm/include/asm/arch-sunxi/tzpc.h  | 4 
 arch/arm/mach-sunxi/board.c | 3 ++-
 5 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile 
b/arch/arm/cpu/armv7/sunxi/Makefile
index b35b9df4a9d6..239c659ec032 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -11,6 +11,7 @@ obj-y += timer.o

 obj-$(CONFIG_MACH_SUN6I)   += tzpc.o
 obj-$(CONFIG_MACH_SUN8I_H3)+= tzpc.o
+obj-$(CONFIG_MACH_SUN9I)   += tzpc.o

 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_ARMV7_PSCI)   += psci.o
diff --git a/arch/arm/cpu/armv7/sunxi/tzpc.c b/arch/arm/cpu/armv7/sunxi/tzpc.c
index 6c8a0fd9a25b..2a2cf363b99c 100644
--- a/arch/arm/cpu/armv7/sunxi/tzpc.c
+++ b/arch/arm/cpu/armv7/sunxi/tzpc.c
@@ -24,4 +24,10 @@ void tzpc_init(void)
writel(SUN8I_H3_TZPC_DECPORT1_ALL, >decport1_set);
writel(SUN8I_H3_TZPC_DECPORT2_ALL, >decport2_set);
 #endif
+
+#ifdef CONFIG_MACH_SUN9I
+   writel(SUN9I_TZPC_DECPORT0_ALL, >decport0_set);
+   writel(SUN9I_TZPC_DECPORT1_ALL, >decport1_set);
+   writel(SUN9I_TZPC_DECPORT2_ALL, >decport2_set);
+#endif
 }
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h 
b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
index e9839eecaa92..25114174f395 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
@@ -90,6 +90,7 @@
 #define SUNXI_TIMER_BASE   (REGS_APB0_BASE + 0x0C00)
 #define SUNXI_PWM_BASE (REGS_APB0_BASE + 0x1400)
 #define SUNXI_LRADC_BASE   (REGS_APB0_BASE + 0x1800)
+#define SUNXI_TZPC_BASE(REGS_APB0_BASE + 0x3400)

 /* APB1 Module */
 #define SUNXI_UART0_BASE   (REGS_APB1_BASE + 0x)
diff --git a/arch/arm/include/asm/arch-sunxi/tzpc.h 
b/arch/arm/include/asm/arch-sunxi/tzpc.h
index 95c55cd4d130..3425d00edd97 100644
--- a/arch/arm/include/asm/arch-sunxi/tzpc.h
+++ b/arch/arm/include/asm/arch-sunxi/tzpc.h
@@ -29,6 +29,10 @@ struct sunxi_tzpc {
 #define SUN8I_H3_TZPC_DECPORT1_ALL  0xff
 #define SUN8I_H3_TZPC_DECPORT2_ALL  0x7f

+#define SUN9I_TZPC_DECPORT0_ALL 0xfe
+#define SUN9I_TZPC_DECPORT1_ALL 0x7f
+#define SUN9I_TZPC_DECPORT2_ALL 0x00
+
 void tzpc_init(void);

 #endif /* _SUNXI_TZPC_H */
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 0f8ead980cdc..0053f562e00d 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -190,7 +190,8 @@ void s_init(void)
"orr r0, r0, #1 << 6\n"
"mcr p15, 0, r0, c1, c0, 1\n");
 #endif
-#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
+#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3 || \
+defined CONFIG_MACH_SUN9I
/* Enable non-secure access to some peripherals */
tzpc_init();
 #endif


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Re: [U-Boot] [PATCH 04/10] sunxi: Use secure SRAM B for secure RAM for sun9i/A80

[Hans de Goede]

Hi,

On 09-11-16 11:21, Chen-Yu Tsai wrote:

The A80 has a 256 kiB secure SRAM. However the first 4 kiB are reserved
for CPU0 hotplug flags.

Signed-off-by: Chen-Yu Tsai 


LGTM:

Reviewed-by: Hans de Goede 

Regards,

Hans



---
 include/configs/sun9i.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/include/configs/sun9i.h b/include/configs/sun9i.h
index cd9e08d8b1b9..e751c5e05c14 100644
--- a/include/configs/sun9i.h
+++ b/include/configs/sun9i.h
@@ -13,6 +13,10 @@
  * A80 specific configuration
  */

+/* First 4 kiB is reserved for CPU0 hotplug flags */
+#define CONFIG_ARMV7_SECURE_BASE   (SUNXI_SRAM_B_BASE + 4 * 1024)
+#define CONFIG_ARMV7_SECURE_MAX_SIZE   (252 * 1024) /* 252 KB */
+
 /*
  * Include common sunxi configuration where most the settings are
  */


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Re: [U-Boot] [PATCH 08/10] sunxi: Add basic PSCI implementation for A80

[Hans de Goede]

Hi,

On 09-11-16 11:21, Chen-Yu Tsai wrote:

The A80 is a big.LITTLE multi-cluster SoC, with a different layout for
the PRCM and CPUCFG registers. As such it needs a different PSCI
implementation.

This patch adds a basic version that allows bringing up the four cores
in the first cluster. The structure is based on existing sunxi PSCI code.

Signed-off-by: Chen-Yu Tsai 


LGTM:

Reviewed-by: Hans de Goede 

Regards,

Hans



---
 arch/arm/cpu/armv7/sunxi/Makefile|   4 +
 arch/arm/cpu/armv7/sunxi/psci-mcpm.c | 234 +++
 2 files changed, 238 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/sunxi/psci-mcpm.c

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile 
b/arch/arm/cpu/armv7/sunxi/Makefile
index 239c659ec032..b18e5f1fa974 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -14,8 +14,12 @@ obj-$(CONFIG_MACH_SUN8I_H3)  += tzpc.o
 obj-$(CONFIG_MACH_SUN9I)   += tzpc.o

 ifndef CONFIG_SPL_BUILD
+ifdef CONFIG_MACH_SUN9I
+obj-$(CONFIG_ARMV7_PSCI)   += psci-mcpm.o
+else
 obj-$(CONFIG_ARMV7_PSCI)   += psci.o
 endif
+endif

 ifdef CONFIG_SPL_BUILD
 obj-y  += fel_utils.o
diff --git a/arch/arm/cpu/armv7/sunxi/psci-mcpm.c 
b/arch/arm/cpu/armv7/sunxi/psci-mcpm.c
new file mode 100644
index ..3ede07cace2c
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/psci-mcpm.c
@@ -0,0 +1,234 @@
+/*
+ * Copyright (C) 2016
+ * Author: Chen-Yu Tsai 
+ *
+ * Based on assembly code by Marc Zyngier ,
+ * which was based on code by Carl van Schaik .
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+/*
+ * NOTE dense CPU IDs (0~3 for first cluster of 4 cores, 4~7 for the
+ * second cluster) are used throughout the PSCI code. Any MPIDR style
+ * values must be converted.
+ */
+
+/*
+ * Provide a dense CPU ID for 2-cluster systems. This must be coded in
+ * assembly as it gets called from psci_stack_setup, when the stack isn't
+ * available yet.
+ *
+ * Only r0 and r3 is usable. r8 - r12 are available if this function is
+ * only called from psci_stack_setup, which we cannot guarantee.
+ */
+u32 __secure __naked psci_get_cpu_id(void)
+{
+   asm volatile (
+   "mrc   p15, 0, r3, c0, c0, 5   @ Get MPIDR\n"
+   "lsr   r0, r3, #6\n"
+   "and   r3, r3, #3\n"
+   "and   r0, r0, #4\n"
+   "orr   r0, r0, r3\n"
+   "bxlr\n"
+   );
+
+   /*
+* The last five lines are the compiler generated assembly code for
+*
+*  return (reg & 0x3) | (((reg >> 8) & 0x1) << 2);
+*
+* We can't guarantee that all compilers correctly use only r0 and
+* r3, so we use inline assembly here.
+*/
+}
+
+static void __secure cp15_write_cntp_tval(u32 tval)
+{
+   asm volatile ("mcr p15, 0, %0, c14, c2, 0" : : "r" (tval));
+}
+
+static void __secure cp15_write_cntp_ctl(u32 val)
+{
+   asm volatile ("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
+}
+
+static u32 __secure cp15_read_cntp_ctl(void)
+{
+   u32 val;
+
+   asm volatile ("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
+
+   return val;
+}
+
+#define ONE_US (CONFIG_TIMER_CLK_FREQ / 100)
+
+/* Use a different name to avoid clashing with the non-secure function */
+static void __secure __udelay_sec(unsigned long us)
+{
+   u32 reg = ONE_US * us;
+
+   cp15_write_cntp_tval(reg);
+   isb();
+   cp15_write_cntp_ctl(3);
+
+   do {
+   isb();
+   reg = cp15_read_cntp_ctl();
+   } while (!(reg & BIT(2)));
+
+   cp15_write_cntp_ctl(0);
+   isb();
+}
+
+static void __secure clamp_release(u32 *clamp)
+{
+   writel(0xff, clamp);
+   __udelay_sec(10);
+   writel(0xfe, clamp);
+   __udelay_sec(10);
+   writel(0xf8, clamp);
+   __udelay_sec(10);
+   writel(0xf0, clamp);
+   __udelay_sec(10);
+   writel(0x00, clamp);
+}
+
+static void __secure clamp_set(u32 *clamp)
+{
+   writel(0xff, clamp);
+}
+
+static void __secure sunxi_core_power_switch(u32 *clamp, u32 *pwroff,
+bool on, int cpu)
+{
+   if (on) {
+   /* Release power clamp */
+   clamp_release(clamp);
+
+   __udelay_sec(20);
+
+   /* Clear power gating */
+   clrbits_le32(pwroff, BIT(cpu));
+   } else {
+   /* Set power gating */
+   setbits_le32(pwroff, BIT(cpu));
+
+   __udelay_sec(20);
+
+   /* Activate power clamp */
+   clamp_set(clamp);
+   }
+}
+
+static void __secure sunxi_cpu_set_power(int cpu, bool on)
+{
+   struct sunxi_prcm_reg *prcm =
+   (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+   int cluster = 

Re: [U-Boot] [PATCH 09/10] sunxi: Enable PSCI on sun9i/A80

[Hans de Goede]

Hi,

On 09-11-16 11:21, Chen-Yu Tsai wrote:

Now that we have a basic version of PSCI firmware, enable non-secure
boot and PSCI on the A80.

Signed-off-by: Chen-Yu Tsai 


LGTM:

Reviewed-by: Hans de Goede 

Regards,

Hans



---
 board/sunxi/Kconfig | 4 
 1 file changed, 4 insertions(+)

diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index e1d4ab148f08..ae2fba1368cc 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -118,8 +118,12 @@ config MACH_SUN8I_H3
 config MACH_SUN9I
bool "sun9i (Allwinner A80)"
select CPU_V7
+   select CPU_V7_HAS_NONSEC
+   select CPU_V7_HAS_VIRT
+   select ARCH_SUPPORT_PSCI
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
+   select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT

 config MACH_SUN50I
bool "sun50i (Allwinner A64)"


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Re: [U-Boot] [PATCH] tools: fix mksunxiboot build for tools-all target

[Hans de Goede]

Hi,

On 10-11-16 13:13, Andre Przywara wrote:

Commit fed329aebe3a ("tools: add mksunxiboot to tools-all target") added
mksunxiboot to the tools-all target, but used the CONFIG_SUNXI symbol
to enable its build. Now commit aec9a0f19f64 ("sunxi: Rename CONFIG_SUNXI
to CONFIG_ARCH_SUNXI"), merged before that, renamed that symbol, so that
the first patch basically gets ineffective.
Adjust the symbol name in tools/Makefile to make it build again.

Signed-off-by: Andre Przywara 


LGTM:

Reviewed-by: Hans de Goede 

Regards,

Hans



---
 tools/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/Makefile b/tools/Makefile
index 400588c..9edb504 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -13,7 +13,7 @@ CONFIG_CMD_NET = y
 CONFIG_XWAY_SWAP_BYTES = y
 CONFIG_NETCONSOLE = y
 CONFIG_SHA1_CHECK_UB_IMG = y
-CONFIG_SUNXI = y
+CONFIG_ARCH_SUNXI = y
 endif

 subdir-$(HOST_TOOLS_ALL) += easylogo


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Re: [U-Boot] [U-Boot, PATCHv2, 1/3] igep00x0: disable CONFIG_DISPLAY_BOARDINFO

[Tom Rini]

On Fri, Nov 04, 2016 at 12:55:21PM +0100, Ladislav Michl wrote:

> As a single U-Boot binary can now run on various board modifications,
> drop CONFIG_DISPLAY_BOARDINFO as it prints flash memory information
> too early to give us chance to easily detect it. Also saves few bytes
> as a bonus.
> 
> Signed-off-by: Ladislav Michl 
> Reviewed-by: Javier Martinez Canillas 
> Tested-by: Javier Martinez Canillas 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] tools: fix mksunxiboot build for tools-all target

[Tom Rini]

On Thu, Nov 10, 2016 at 12:13:23PM +, Andre Przywara wrote:

> Commit fed329aebe3a ("tools: add mksunxiboot to tools-all target") added
> mksunxiboot to the tools-all target, but used the CONFIG_SUNXI symbol
> to enable its build. Now commit aec9a0f19f64 ("sunxi: Rename CONFIG_SUNXI
> to CONFIG_ARCH_SUNXI"), merged before that, renamed that symbol, so that
> the first patch basically gets ineffective.
> Adjust the symbol name in tools/Makefile to make it build again.
> 
> Signed-off-by: Andre Przywara 
> Reviewed-by: Hans de Goede 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] Please pull: u-boot-video/master

[Tom Rini]

On Sun, Nov 13, 2016 at 07:08:41PM +0100, Anatolij Gustschin wrote:

> Hi Tom,
> 
> The following changes since commit 38cacdab3b5a6d8efd16a4b2620f7ab72144a624:
> 
>   Merge branch 'master' of git://git.denx.de/u-boot-tegra (2016-11-08 
> 10:36:57 -0500)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-video.git master
> 
> for you to fetch changes up to 9f6ce7defeb3786739bb55eabb9bb20f5b50cd0f:
> 
>   video: bmp: Fix compilation errors with CONFIG_BMP_xxBPP enabled 
> (2016-11-12 21:03:11 +0100)
> 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] Pull request: u-boot-spi/master

[Tom Rini]

On Sat, Nov 12, 2016 at 05:43:08PM +0530, Jagan Teki wrote:

> Hi Tom,
> 
> Please take these fixes.
> 
> thanks!
> Jagan.
> 
> The following changes since commit 38cacdab3b5a6d8efd16a4b2620f7ab72144a624:
> 
>   Merge branch 'master' of git://git.denx.de/u-boot-tegra (2016-11-08 
> 10:36:57 -0500)
> 
> are available in the git repository at:
> 
> 
>   git://git.denx.de/u-boot-spi.git master
> 
> for you to fetch changes up to 7480b35fd19d18871d09fc0447d978d8d10c05b8:
> 
>   spi: ti_qspi: Fix baudrate divider calculation (2016-11-11 17:22:47 +0530)
> 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] [U-Boot, v2, 1/2] arm: print the cache config option in hex instead of decimal

[Tom Rini]

On Sat, Oct 29, 2016 at 03:19:09PM +0530, Keerthy wrote:

> Printing the option value in hex makes it more comprehensible.
> 
> Signed-off-by: Keerthy 
> Reviewed-by: Tom Rini 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [U-Boot] mx6ull_14x14_evk: Add README file

[Tom Rini]

On Thu, Nov 10, 2016 at 03:05:37PM -0200, Diego Dorta wrote:

> Add a README file to help users getting started with the board.
> 
> Signed-off-by: Diego Dorta 
> Reviewed-by: Fabio Estevam 
> Reviewed-by: Peng Fan 
> Reviewed-by: Jagan Teki 

Applied to u-boot/master, thanks!

-- 
Tom


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[U-Boot] [PATCH] cmd: move CMD_PXE to Kconfig

[Yann E. MORIN]

Currently, CMD_PXE is forcibly enabled in config_distro_defaults.h, so
that general purpose distributions can rely on it being defined. This
header is included, under conditions or not, by various archs or
famillies of archs / SoCs.

However, it is very possible that boards based on those SoCs will not
have a physical ethernet connector at all, even if the have a MAC; for
example, the Nanopi Neo AIR (sunxi H3) does not. It is also possible
that network booting is absolutely not necessary for a device.

However, it is not possible to disable the PXE command, as it is
forcibly enabled and is non-configurable.

But it turns out we already have a config option to build a distro-ready
image, in the name of DISTRO_DEFAULTS.

Move CMD_PXE out of the hard-coded config_distro_defaults.h into a
Kconfig option, that gets selected by DISTRO_DEFAULTS when it is set.

Signed-off-by: "Yann E. MORIN" 
Cc: Joe Hershberger 
---
 Kconfig  | 1 +
 cmd/Kconfig  | 5 +
 include/config_distro_defaults.h | 2 --
 3 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/Kconfig b/Kconfig
index 1263d0b..5421cd3 100644
--- a/Kconfig
+++ b/Kconfig
@@ -60,6 +60,7 @@ config DISTRO_DEFAULTS
select CMD_BOOTZ if ARM && !ARM64
select CMD_BOOTI if ARM64
select CMD_DHCP
+   select CMD_PXE
select CMD_EXT2
select CMD_EXT4
select CMD_FAT
diff --git a/cmd/Kconfig b/cmd/Kconfig
index e339d86..95f5ce6 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -496,6 +496,11 @@ config CMD_DHCP
help
  Boot image via network using DHCP/TFTP protocol
 
+config CMD_PXE
+   bool "pxe"
+   help
+ Boot image via network using PXE protocol
+
 config CMD_NFS
bool "nfs"
default y
diff --git a/include/config_distro_defaults.h b/include/config_distro_defaults.h
index b5efab5..01cd6d9 100644
--- a/include/config_distro_defaults.h
+++ b/include/config_distro_defaults.h
@@ -20,8 +20,6 @@
 #define CONFIG_BOOTP_PXE
 #define CONFIG_BOOTP_SUBNETMASK
 
-#define CONFIG_CMD_PXE
-
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_LONGHELP
-- 
2.7.4

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[U-Boot] [PATCH v2 02/22] rockchip: video: Correct VOP clock selection

[Simon Glass]

This code incorrectly uses the oscillator. It should use the clock
selected in the device tree.

Signed-off-by: Simon Glass 
Fixes: 135aa95 (clk: convert API to match reset/mailbox style)
---

Changes in v2: None

 drivers/video/rockchip/rk_vop.c | 7 +--
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index c6d88d9..130dace 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -195,7 +195,6 @@ int rk_display_init(struct udevice *dev, ulong fbbase,
struct udevice *disp;
int ret, remote, i, offset;
struct display_plat *disp_uc_plat;
-   struct udevice *dev_clk;
struct clk clk;
 
vop_id = fdtdec_get_int(blob, ep_node, "reg", -1);
@@ -238,11 +237,7 @@ int rk_display_init(struct udevice *dev, ulong fbbase,
return ret;
}
 
-   ret = rockchip_get_clk(_clk);
-   if (!ret) {
-   clk.id = DCLK_VOP0 + remote_vop_id;
-   ret = clk_request(dev_clk, );
-   }
+   ret = clk_get_by_index(dev, 1, );
if (!ret)
ret = clk_set_rate(, timing.pixelclock.typ);
if (ret) {
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH v2 05/22] stdio: Correct code style nits

[Simon Glass]

Fix a few code style nits in stdio_get_by_name().

Signed-off-by: Simon Glass 
---

Changes in v2: None

 common/stdio.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/common/stdio.c b/common/stdio.c
index 8e4a9be..a7d016b 100644
--- a/common/stdio.c
+++ b/common/stdio.c
@@ -173,12 +173,12 @@ static int stdio_probe_device(const char *name, enum 
uclass_id id,
 }
 #endif
 
-struct stdio_dev* stdio_get_by_name(const char *name)
+struct stdio_dev *stdio_get_by_name(const char *name)
 {
struct list_head *pos;
struct stdio_dev *sdev;
 
-   if(!name)
+   if (!name)
return NULL;
 
list_for_each(pos, &(devs.list)) {
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH v2 03/22] rockchip: Allow jerry to use of-platdata

[Simon Glass]

This board always boots from SPI, so update the code to support that with
of-platdata. The boot source is not currently available with of-platdata.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 arch/arm/mach-rockchip/rk3288-board-spl.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c 
b/arch/arm/mach-rockchip/rk3288-board-spl.c
index 0f40351..185b5fd 100644
--- a/arch/arm/mach-rockchip/rk3288-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
@@ -64,6 +64,8 @@ u32 spl_boot_device(void)
}
 
 fallback:
+#elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY)
+   return BOOT_DEVICE_SPI;
 #endif
return BOOT_DEVICE_MMC1;
 }
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH v2 04/22] dm: core: Handle global_data moving in SPL

[Simon Glass]

When CONFIG_SPL_STACK_R is enabled, and spl_init() is called before
board_init_r(), spl_relocate_stack_gd() will move global_data to a new
place in memory. This affects driver model since it uses a list for the
uclasses. Unless this is updated the list will become invalid. When
looking for a non-existent uclass, such as when adding a new one, the loop
in uclass_find() may continue forever, thus causing a hang.

Add a function to correct this rather obscure bug.

Signed-off-by: Simon Glass 
---

Changes in v2:
- Fix CONFIG_IS_ENABLED condition

 common/spl/spl.c|  3 +++
 drivers/core/root.c |  7 +++
 include/dm/root.h   | 10 ++
 3 files changed, 20 insertions(+)

diff --git a/common/spl/spl.c b/common/spl/spl.c
index bdb165a..d16cd18 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -511,6 +511,9 @@ ulong spl_relocate_stack_gd(void)
ptr = CONFIG_SPL_STACK_R_ADDR - roundup(sizeof(gd_t),16);
new_gd = (gd_t *)ptr;
memcpy(new_gd, (void *)gd, sizeof(gd_t));
+#if CONFIG_IS_ENABLED(DM)
+   dm_fixup_for_gd_move(new_gd);
+#endif
 #if !defined(CONFIG_ARM)
gd = new_gd;
 #endif
diff --git a/drivers/core/root.c b/drivers/core/root.c
index 33dc9c0..9edfc1e 100644
--- a/drivers/core/root.c
+++ b/drivers/core/root.c
@@ -41,6 +41,13 @@ struct udevice *dm_root(void)
return gd->dm_root;
 }
 
+void dm_fixup_for_gd_move(struct global_data *new_gd)
+{
+   /* The sentinel node has moved, so update things that point to it */
+   new_gd->uclass_root.next->prev = _gd->uclass_root;
+   new_gd->uclass_root.prev->next = _gd->uclass_root;
+}
+
 fdt_addr_t dm_get_translation_offset(void)
 {
struct udevice *root = dm_root();
diff --git a/include/dm/root.h b/include/dm/root.h
index c7f0c1d..3cf730d 100644
--- a/include/dm/root.h
+++ b/include/dm/root.h
@@ -21,6 +21,16 @@ struct udevice;
  */
 struct udevice *dm_root(void);
 
+struct global_data;
+/**
+ * dm_fixup_for_gd_move() - Handle global_data moving to a new place
+ *
+ * The uclass list is part of global_data. Due to the way lists work, moving
+ * the list will cause it to become invalid. This function fixes that up so
+ * that the uclass list will work correctly.
+ */
+void dm_fixup_for_gd_move(struct global_data *new_gd);
+
 /**
  * dm_scan_platdata() - Scan all platform data and bind drivers
  *
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH v2 01/22] rockchip: video: Correct HDMI data source selection

[Simon Glass]

This code currently always selects the second source. It only worked
because both sources are set up.

With the change to only init video devices that are present in the stdout
environment variable, this fails. Fix it.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 drivers/video/rockchip/rk_hdmi.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c
index 7976c5e..72142dc 100644
--- a/drivers/video/rockchip/rk_hdmi.c
+++ b/drivers/video/rockchip/rk_hdmi.c
@@ -899,7 +899,8 @@ static int rk_hdmi_probe(struct udevice *dev)
rk_setreg(>grf->soc_con6, 1 << 15);
 
/* hdmi data from vop id */
-   rk_setreg(>grf->soc_con6, (vop_id == 1) ? (1 << 4) : (1 << 4));
+   rk_clrsetreg(>grf->soc_con6, 1 << 4,
+(vop_id == 1) ? (1 << 4) : 0);
 
ret = hdmi_wait_for_hpd(priv->regs);
if (ret < 0) {
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH v2 00/22] rockchip: Add support for Asus Chromebit

[Simon Glass]

This series adds support for 'mickey', the Asus Chromebit based on Rockchip
RK3288.

Some refactoring is included to jerry also. The intent is that all
RK3288-based Chromebooks will use the 'veyron' board, with everything
common except the device tree. SPI is used to boot, and we move jerry to
use of-platdata to save space.

At present there are few boards in U-Boot with two displays. Jerry supports
both its internal EDP display and HDMI. The current driver can get confused
if both HDMI and EDP try to use the same video-out device (VOP). Some
adjustments are made to fix this.

Currently there is an option to increase the CPU speed in SPL. This does
not seem necessary with mickey, so instead, this is done in U-Boot proper.

Additionally some bugs have crept in as part of the clock API conversion
and other work, so this series fixes those.

Changes in v2:
- Fix CONFIG_IS_ENABLED condition
- Add new patch with note about the SDRAM voltage
- Add new patch to avoid using u8 in the HDMI driver
- Enable only the active eMMC port

Simon Glass (22):
  rockchip: video: Correct HDMI data source selection
  rockchip: video: Correct VOP clock selection
  rockchip: Allow jerry to use of-platdata
  dm: core: Handle global_data moving in SPL
  stdio: Correct code style nits
  stdio: Correct numbering logic in stdio_probe_device()
  spi: Add of-platdata support to SPI and SPI flash
  rockchip: spi: Add support for of-platdata
  rockchip: spi: Honour the deactivation delay
  spi: Add error checking for invalid bus widths
  spi: Add a debug() on bind failure
  video: Use cache-alignment in video_sync()
  video: Track whether a display is in use
  rockchip: video: Check for device in use
  rockchip: Move jerry to use of-platdata
  rockchip: Rename jerry files to veyron
  rockchip: veyron: Add a note about the SDRAM voltage
  rockchip: Move jerry SDRAM settings into its own .dts file
  rockchip: clk: Support setting ACLK
  rockchip: veyron: Adjust ARM clock after relocation
  rockchip: video: Avoid using u8 in the HDMI driver
  rockchip: Add support for veyron-mickey (Chromebit)

 arch/arm/dts/Makefile  |   3 +-
 arch/arm/dts/rk3288-veyron-chromebook.dtsi |   2 +
 .../{rk3288-jerry.dts => rk3288-veyron-jerry.dts}  |  16 +-
 arch/arm/dts/rk3288-veyron-mickey.dts  | 277 +
 arch/arm/dts/rk3288-veyron.dtsi|   8 -
 arch/arm/mach-rockchip/rk3288-board-spl.c  |   3 +
 arch/arm/mach-rockchip/rk3288-board.c  |  44 
 arch/arm/mach-rockchip/rk3288/Kconfig  |  11 +-
 board/google/chromebook_jerry/Kconfig  |  15 --
 board/google/chromebook_jerry/MAINTAINERS  |   6 -
 board/google/chromebook_jerry/jerry.c  |   7 -
 board/google/veyron/Kconfig|  31 +++
 board/google/veyron/MAINTAINERS|  13 +
 board/google/{chromebook_jerry => veyron}/Makefile |   2 +-
 board/google/veyron/veyron.c   |  13 +
 common/spl/spl.c   |   3 +
 common/stdio.c |   9 +-
 configs/chromebit_mickey_defconfig |  84 +++
 configs/chromebook_jerry_defconfig |  10 +-
 drivers/clk/rockchip/clk_rk3288.c  |   7 +
 drivers/core/root.c|   7 +
 drivers/mtd/spi/spi_flash.c|   2 +-
 drivers/spi/rk_spi.c   |  44 +++-
 drivers/spi/spi-uclass.c   |  26 +-
 drivers/video/display-uclass.c |  18 +-
 drivers/video/rockchip/rk_hdmi.c   |  33 +--
 drivers/video/rockchip/rk_vop.c|  16 +-
 drivers/video/video-uclass.c   |   3 +-
 include/configs/{chromebook_jerry.h => veyron.h}   |   0
 include/display.h  |  10 +
 include/dm/root.h  |  10 +
 31 files changed, 648 insertions(+), 85 deletions(-)
 rename arch/arm/dts/{rk3288-jerry.dts => rk3288-veyron-jerry.dts} (92%)
 create mode 100644 arch/arm/dts/rk3288-veyron-mickey.dts
 delete mode 100644 board/google/chromebook_jerry/Kconfig
 delete mode 100644 board/google/chromebook_jerry/MAINTAINERS
 delete mode 100644 board/google/chromebook_jerry/jerry.c
 create mode 100644 board/google/veyron/Kconfig
 create mode 100644 board/google/veyron/MAINTAINERS
 rename board/google/{chromebook_jerry => veyron}/Makefile (81%)
 create mode 100644 board/google/veyron/veyron.c
 create mode 100644 configs/chromebit_mickey_defconfig
 rename include/configs/{chromebook_jerry.h => veyron.h} (100%)

-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH v2 08/22] rockchip: spi: Add support for of-platdata

[Simon Glass]

Allow this driver to be used with of-platdata on rk3288.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 drivers/spi/rk_spi.c | 36 +++-
 1 file changed, 35 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index 105ee4a..8d64249 100644
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -27,6 +28,9 @@ DECLARE_GLOBAL_DATA_PTR;
 #define DEBUG_RK_SPI   0
 
 struct rockchip_spi_platdata {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+   struct dtd_rockchip_rk3288_spi of_plat;
+#endif
s32 frequency;  /* Default clock frequency, -1 for none */
fdt_addr_t base;
uint deactivate_delay_us;   /* Delay to wait after deactivate */
@@ -127,9 +131,29 @@ static void spi_cs_deactivate(struct udevice *dev, uint cs)
priv->last_transaction_us = timer_get_us();
 }
 
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+static int conv_of_platdata(struct udevice *dev)
+{
+   struct rockchip_spi_platdata *plat = dev->platdata;
+   struct dtd_rockchip_rk3288_spi *dtplat = >of_plat;
+   struct rockchip_spi_priv *priv = dev_get_priv(dev);
+   int ret;
+
+   plat->base = dtplat->reg[0];
+   plat->frequency = 2000;
+   ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, >clk);
+   if (ret < 0)
+   return ret;
+   dev->req_seq = 0;
+
+   return 0;
+}
+#endif
+
 static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
 {
-   struct rockchip_spi_platdata *plat = bus->platdata;
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+   struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
struct rockchip_spi_priv *priv = dev_get_priv(bus);
const void *blob = gd->fdt_blob;
int node = bus->of_offset;
@@ -153,6 +177,7 @@ static int rockchip_spi_ofdata_to_platdata(struct udevice 
*bus)
debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
  __func__, (uint)plat->base, plat->frequency,
  plat->deactivate_delay_us);
+#endif
 
return 0;
 }
@@ -164,6 +189,11 @@ static int rockchip_spi_probe(struct udevice *bus)
int ret;
 
debug("%s: probe\n", __func__);
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+   ret = conv_of_platdata(bus);
+   if (ret)
+   return ret;
+#endif
priv->regs = (struct rockchip_spi *)plat->base;
 
priv->last_transaction_us = timer_get_us();
@@ -369,7 +399,11 @@ static const struct udevice_id rockchip_spi_ids[] = {
 };
 
 U_BOOT_DRIVER(rockchip_spi) = {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+   .name   = "rockchip_rk3288_spi",
+#else
.name   = "rockchip_spi",
+#endif
.id = UCLASS_SPI,
.of_match = rockchip_spi_ids,
.ops= _spi_ops,
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH v2 10/22] spi: Add error checking for invalid bus widths

[Simon Glass]

At present an invalid bus width prints a message but does not return an
error. This is the opposite of the correct behaviour. Adjust it to avoid
code bloat in the common case, and avoid hard-to-debug failure in the
uncommon case.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 drivers/spi/spi-uclass.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index 26eada2..358e229 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c
@@ -415,8 +415,8 @@ int spi_slave_ofdata_to_platdata(const void *blob, int node,
mode |= SPI_TX_QUAD;
break;
default:
-   error("spi-tx-bus-width %d not supported\n", value);
-   break;
+   debug("spi-tx-bus-width %d not supported\n", value);
+   return -EPROTONOSUPPORT;
}
 
value = fdtdec_get_uint(blob, node, "spi-rx-bus-width", 1);
@@ -430,8 +430,8 @@ int spi_slave_ofdata_to_platdata(const void *blob, int node,
mode |= SPI_RX_QUAD;
break;
default:
-   error("spi-rx-bus-width %d not supported\n", value);
-   break;
+   debug("spi-rx-bus-width %d not supported\n", value);
+   return -EPROTONOSUPPORT;
}
 
plat->mode = mode;
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH v2 11/22] spi: Add a debug() on bind failure

[Simon Glass]

This is an uncommon error but we may as well have a debug() message when
it happens.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 drivers/spi/spi-uclass.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index 358e229..b251442 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c
@@ -297,8 +297,11 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int 
mode,
debug("%s: Binding new device '%s', busnum=%d, cs=%d, 
driver=%s\n",
  __func__, dev_name, busnum, cs, drv_name);
ret = device_bind_driver(bus, drv_name, dev_name, );
-   if (ret)
+   if (ret) {
+   debug("%s: Unable to bind driver (ret=%d)\n", __func__,
+ ret);
return ret;
+   }
plat = dev_get_parent_platdata(dev);
plat->cs = cs;
plat->max_hz = speed;
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH v2 07/22] spi: Add of-platdata support to SPI and SPI flash

[Simon Glass]

Some boards may want to use these subsystems with of-platdata in SPL. Add
support for this by avoiding any device tree access in this case.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 drivers/mtd/spi/spi_flash.c |  2 +-
 drivers/spi/spi-uclass.c| 13 -
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 7f6e9ae..6571f86 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -1228,7 +1228,7 @@ int spi_flash_scan(struct spi_flash *flash)
return ret;
 #endif
 
-#if CONFIG_IS_ENABLED(OF_CONTROL)
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
ret = spi_flash_decode_fdt(gd->fdt_blob, flash);
if (ret) {
debug("SF: FDT decode error\n");
diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index d9c49e4..26eada2 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c
@@ -108,6 +108,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
return dm_spi_xfer(slave->dev, bitlen, dout, din, flags);
 }
 
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
 static int spi_child_post_bind(struct udevice *dev)
 {
struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
@@ -117,14 +118,16 @@ static int spi_child_post_bind(struct udevice *dev)
 
return spi_slave_ofdata_to_platdata(gd->fdt_blob, dev->of_offset, plat);
 }
+#endif
 
 static int spi_post_probe(struct udevice *bus)
 {
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct dm_spi_bus *spi = dev_get_uclass_priv(bus);
 
spi->max_hz = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
 "spi-max-frequency", 0);
-
+#endif
 #if defined(CONFIG_NEEDS_MANUAL_RELOC)
struct dm_spi_ops *ops = spi_get_ops(bus);
 
@@ -274,7 +277,11 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int 
mode,
bool created = false;
int ret;
 
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+   ret = uclass_first_device_err(UCLASS_SPI, );
+#else
ret = uclass_get_device_by_seq(UCLASS_SPI, busnum, );
+#endif
if (ret) {
printf("Invalid bus %d (err=%d)\n", busnum, ret);
return ret;
@@ -436,14 +443,18 @@ UCLASS_DRIVER(spi) = {
.id = UCLASS_SPI,
.name   = "spi",
.flags  = DM_UC_FLAG_SEQ_ALIAS,
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
.post_bind  = dm_scan_fdt_dev,
+#endif
.post_probe = spi_post_probe,
.child_pre_probe = spi_child_pre_probe,
.per_device_auto_alloc_size = sizeof(struct dm_spi_bus),
.per_child_auto_alloc_size = sizeof(struct spi_slave),
.per_child_platdata_auto_alloc_size =
sizeof(struct dm_spi_slave_platdata),
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
.child_post_bind = spi_child_post_bind,
+#endif
 };
 
 UCLASS_DRIVER(spi_generic) = {
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH v2 09/22] rockchip: spi: Honour the deactivation delay

[Simon Glass]

This is not currently implemented. Add support for this so that the Chrome
OS EC can be used on jerry.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 drivers/spi/rk_spi.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index 8d64249..15cf0bd 100644
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -110,6 +110,14 @@ static void spi_cs_activate(struct udevice *dev, uint cs)
struct rockchip_spi_priv *priv = dev_get_priv(bus);
struct rockchip_spi *regs = priv->regs;
 
+   /* If it's too soon to do another transaction, wait */
+   if (plat->deactivate_delay_us && priv->last_transaction_us) {
+   ulong delay_us; /* The delay completed so far */
+   delay_us = timer_get_us() - priv->last_transaction_us;
+   if (delay_us < plat->deactivate_delay_us)
+   udelay(plat->deactivate_delay_us - delay_us);
+   }
+
debug("activate cs%u\n", cs);
writel(1 << cs, >ser);
if (plat->activate_delay_us)
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH v2 06/22] stdio: Correct numbering logic in stdio_probe_device()

[Simon Glass]

The current code assumes that the devices are ordered corresponding to
their alias value. But (for example) video1 can come before video0 in the
device tree.

Correct this, by always looking for device 0 first. After that we can fall
back to finding the first available device.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 common/stdio.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/common/stdio.c b/common/stdio.c
index a7d016b..4d30017 100644
--- a/common/stdio.c
+++ b/common/stdio.c
@@ -151,9 +151,10 @@ static int stdio_probe_device(const char *name, enum 
uclass_id id,
*sdevp = NULL;
seq = trailing_strtoln(name, NULL);
if (seq == -1)
+   seq = 0;
+   ret = uclass_get_device_by_seq(id, seq, );
+   if (ret == -ENODEV)
ret = uclass_first_device_err(id, );
-   else
-   ret = uclass_get_device_by_seq(id, seq, );
if (ret) {
debug("No %s device for seq %d (%s)\n", uclass_get_name(id),
  seq, name);
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH] spl: mmc: fix build without CONFIG_SPL_LIBCOMMON_SUPPORT

[Yann E. MORIN]

When CONFIG_SPL_LIBCOMMON_SUPPORT is disabled, the last case statement
is missing a proper statement, which makes the compiler whine.

Signed-off-by: "Yann E. MORIN" 
Cc: Pantelis Antoniou 
---
 common/spl/spl_mmc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index c674e61..cc81d19 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -343,6 +343,7 @@ static int spl_mmc_load_image(struct spl_image_info 
*spl_image,
 
break;
case MMCSD_MODE_UNDEFINED:
+   ;
 #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
default:
puts("spl: mmc: wrong boot mode\n");
-- 
2.7.4

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Re: [U-Boot] [U-Boot, v2, 2/2] arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode

[Tom Rini]

On Sat, Oct 29, 2016 at 03:19:10PM +0530, Keerthy wrote:

> While we setup the mmu initially we mark set_section_dcache with
> DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro
> is rightly defined with TTB_SECT_XN_MASK set so as to mark all the
> 4GB XN. In case of LPAE mode  XN(Execute-never) bit is not set with
> DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which
> keeps all the regions execute okay and this leads to random speculative
> fetches in random memory regions which was eventually caught by kernel
> omap-l3-noc driver.
> 
> Fix this to mark the regions as XN by default.
> 
> Signed-off-by: Keerthy 
> Reviewed-by: Alexander Graf 
> Reviewed-by: Tom Rini 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] [U-Boot,PATCHv2,2/3] igep00x0: consolidate defconfigs

[Tom Rini]

On Fri, Nov 04, 2016 at 12:57:27PM +0100, Ladislav Michl wrote:

> Defconfigs should remain the same except CONFIG_SYS_EXTRA_OPTIONS.
> Drop NAND specific defconfig as flash type is runtime detected.
> 
> Signed-off-by: Ladislav Michl 
> Reviewed-by: Javier Martinez Canillas 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] ARM: k2g: Update PLL Multiplier and divider values

[Tom Rini]

On Thu, Nov 03, 2016 at 03:35:02PM +0530, Lokesh Vutla wrote:

> Only a certain set of PLLM/D values are recommended to configure the DDR
> at the required speeds for a given clock input frequency. Updating these
> values as specified in Data Sheet[1] Table 5-18
> 
> [1] http://www.ti.com/lit/ds/symlink/66ak2g02.pdf
> 
> Signed-off-by: Lokesh Vutla 
> Reviewed-by: Tom Rini 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot,PATCHv2,3/3] igep00x0: add Hynix timings

[Tom Rini]

On Fri, Nov 04, 2016 at 12:59:46PM +0100, Ladislav Michl wrote:

> Tested on IGEPv2 with Micron MT29F4G16ABBDA3W and
> Hynix H27S4G6F2DKA-BM
> 
> Signed-off-by: Ladislav Michl 
> Reviewed-by: Javier Martinez Canillas 
> Tested-by: Javier Martinez Canillas 

Applied to u-boot/master, thanks!

-- 
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[U-Boot] [PATCH v2 22/22] rockchip: Add support for veyron-mickey (Chromebit)

[Simon Glass]

This adds support for the Asus Chromebit, and RK3288-based device designed
to plug directly into an HDMI monitor. The device tree file comes from
Linux v4.8.

Signed-off-by: Simon Glass 
---

Changes in v2:
- Enable only the active eMMC port

 arch/arm/dts/Makefile |   1 +
 arch/arm/dts/rk3288-veyron-mickey.dts | 277 ++
 arch/arm/mach-rockchip/rk3288-board-spl.c |   3 +-
 arch/arm/mach-rockchip/rk3288/Kconfig |   9 +
 board/google/veyron/Kconfig   |  16 ++
 board/google/veyron/MAINTAINERS   |   7 +
 configs/chromebit_mickey_defconfig|  84 +
 7 files changed, 396 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/rk3288-veyron-mickey.dts
 create mode 100644 configs/chromebit_mickey_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index af8b0de..5723c1b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -30,6 +30,7 @@ dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-firefly.dtb \
rk3288-veyron-jerry.dtb \
+   rk3288-veyron-mickey.dtb \
rk3288-rock2-square.dtb \
rk3288-evb.dtb \
rk3288-fennec.dtb \
diff --git a/arch/arm/dts/rk3288-veyron-mickey.dts 
b/arch/arm/dts/rk3288-veyron-mickey.dts
new file mode 100644
index 000..e0dc362
--- /dev/null
+++ b/arch/arm/dts/rk3288-veyron-mickey.dts
@@ -0,0 +1,277 @@
+/*
+ * Google Veyron Mickey Rev 0 board device tree source
+ *
+ * Copyright 2015 Google, Inc
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *  Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "rk3288-veyron-chromebook.dtsi"
+
+/ {
+   model = "Google Mickey";
+   compatible = "google,veyron-mickey-rev8", "google,veyron-mickey-rev7",
+"google,veyron-mickey-rev6", "google,veyron-mickey-rev5",
+"google,veyron-mickey-rev4", "google,veyron-mickey-rev3",
+"google,veyron-mickey-rev2", "google,veyron-mickey-rev1",
+"google,veyron-mickey-rev0", "google,veyron-mickey",
+"google,veyron", "rockchip,rk3288";
+
+   vcc_5v: vcc-5v {
+   vin-supply = <_sys>;
+   };
+
+   vcc33_io: vcc33_io {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc33_io";
+   regulator-always-on;
+   regulator-boot-on;
+   vin-supply = <_sys>;
+   };
+};
+
+_thermal {
+   /delete-node/ trips;
+   /delete-node/ cooling-maps;
+
+   trips {
+   cpu_alert_almost_warm: cpu_alert_almost_warm {
+   temperature = <63000>; /* millicelsius */
+   hysteresis = <2000>; /* millicelsius */
+   type = "passive";
+   };
+   cpu_alert_warm: cpu_alert_warm {
+   temperature = <65000>; /* millicelsius */
+   hysteresis = <2000>; /* millicelsius */
+   type = "passive";
+   };
+ 

[U-Boot] [PATCH v2 0/4] buildman: Threading and output improvements

[Simon Glass]

This series includes a few minor improvements to buildman:

- Cleaner output and updates on what buildman is doing at the start
- a way to generate only the CONFIG options in a build, for speed (-D)
- a fix for pressing Ctrl-C during a build (so that it exits cleanly).

(all but the second is now applied)


Changes in v2:
- Rebase to mainline with Masahiro's changes
- Fix failure to reconfigure when needed
- Drop patches previously applied

Simon Glass (4):
  Makefile: Add a target to create the .cfg files
  buildman: Add an option to just create the config
  buildman: Add documentation for CONFIG checking
  buildman: Squash useless output from -K

 Makefile|  3 +++
 tools/buildman/README   | 49 +
 tools/buildman/builder.py   | 37 +--
 tools/buildman/builderthread.py | 14 +++-
 tools/buildman/cmdline.py   |  4 
 tools/buildman/control.py   |  4 +++-
 6 files changed, 93 insertions(+), 18 deletions(-)

-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH] rockchip: Add support for veyron-minnie (ASUS Chromebook Flip)

[Simon Glass]

This adds support for the Asus Chromebook Flip, an RK3288-based clamshell
device which can flip into 'tablet' mode. The device tree file comes from
Linux v4.8. The SDRAM parameters are for 4GB Samsung LPDDR3.

Signed-off-by: Simon Glass 
---

 arch/arm/dts/Makefile |   1 +
 arch/arm/dts/rk3288-veyron-minnie.dts | 301 ++
 arch/arm/mach-rockchip/rk3288-board-spl.c |   3 +-
 arch/arm/mach-rockchip/rk3288/Kconfig |  10 +
 board/google/veyron/Kconfig   |  16 ++
 board/google/veyron/MAINTAINERS   |   7 +
 configs/chromebook_minnie_defconfig   |  82 
 7 files changed, 419 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/rk3288-veyron-minnie.dts
 create mode 100644 configs/chromebook_minnie_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 5723c1b..46329d9 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -31,6 +31,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-firefly.dtb \
rk3288-veyron-jerry.dtb \
rk3288-veyron-mickey.dtb \
+   rk3288-veyron-minnie.dtb \
rk3288-rock2-square.dtb \
rk3288-evb.dtb \
rk3288-fennec.dtb \
diff --git a/arch/arm/dts/rk3288-veyron-minnie.dts 
b/arch/arm/dts/rk3288-veyron-minnie.dts
new file mode 100644
index 000..0a2915f
--- /dev/null
+++ b/arch/arm/dts/rk3288-veyron-minnie.dts
@@ -0,0 +1,301 @@
+/*
+ * Google Veyron Minnie Rev 0+ board device tree source
+ *
+ * Copyright 2015 Google, Inc
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *  Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "rk3288-veyron-chromebook.dtsi"
+
+/ {
+   model = "Google Minnie";
+   compatible = "google,veyron-minnie-rev4", "google,veyron-minnie-rev3",
+"google,veyron-minnie-rev2", "google,veyron-minnie-rev1",
+"google,veyron-minnie-rev0", "google,veyron-minnie",
+"google,veyron", "rockchip,rk3288";
+
+   backlight_regulator: backlight-regulator {
+   compatible = "regulator-fixed";
+   enable-active-high;
+   gpio = < 12 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_pwr_en>;
+   regulator-name = "backlight_regulator";
+   vin-supply = <_sys>;
+   startup-delay-us = <15000>;
+   };
+
+   panel_regulator: panel-regulator {
+   compatible = "regulator-fixed";
+   enable-active-high;
+   gpio = < 14 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_enable_h>;
+   regulator-name = "panel_regulator";
+   startup-delay-us = <10>;
+   vin-supply = <_sys>;
+   };
+
+   vcc18_lcd: vcc18-lcd {
+   compatible = "regulator-fixed";
+   enable-active-high;
+   gpio = < 13 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_1v8_disp_en>;
+   

[U-Boot] [PATCH v2 18/22] rockchip: Move jerry SDRAM settings into its own .dts file

[Simon Glass]

The SDRAM settings are not common across all veyron models. Move the
current settings into Jerry's file.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 arch/arm/dts/rk3288-veyron-jerry.dts | 11 +++
 arch/arm/dts/rk3288-veyron.dtsi  |  8 
 2 files changed, 11 insertions(+), 8 deletions(-)

diff --git a/arch/arm/dts/rk3288-veyron-jerry.dts 
b/arch/arm/dts/rk3288-veyron-jerry.dts
index da37ea8..8aab607 100644
--- a/arch/arm/dts/rk3288-veyron-jerry.dts
+++ b/arch/arm/dts/rk3288-veyron-jerry.dts
@@ -55,6 +55,17 @@
};
 };
 
+ {
+   rockchip,pctl-timing = <0x29a 0xc8 0x1f4 0x42 0x4e 0x4 0xea 0xa
+   0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
+   0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
+   0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
+   0x5 0x0>;
+   rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
+   0xa60 0x40 0x10 0x0>;
+   rockchip,sdram-params = <0x30B25564 0x627 3 66600 3 9 1>;
+};
+
 _keys {
power {
gpios = < 5 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi
index 2ffe39c..a314058 100644
--- a/arch/arm/dts/rk3288-veyron.dtsi
+++ b/arch/arm/dts/rk3288-veyron.dtsi
@@ -245,14 +245,6 @@
533000 115
666000 120
>;
-   rockchip,pctl-timing = <0x29a 0xc8 0x1f4 0x42 0x4e 0x4 0xea 0xa
-   0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
-   0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
-   0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
-   0x5 0x0>;
-   rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
-   0xa60 0x40 0x10 0x0>;
-   rockchip,sdram-params = <0x30B25564 0x627 3 66600 3 9 1>;
 };
 
  {
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH v2 20/22] rockchip: veyron: Adjust ARM clock after relocation

[Simon Glass]

Update board_init() to increase the ARM clock to the maximum speed on
veyron boards. This makes quite a large difference in performance. With
this change, speed goes from about 750 DMIPS to 2720 DMIPs.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 arch/arm/mach-rockchip/rk3288-board.c | 44 +++
 1 file changed, 44 insertions(+)

diff --git a/arch/arm/mach-rockchip/rk3288-board.c 
b/arch/arm/mach-rockchip/rk3288-board.c
index baf9522..bca6075 100644
--- a/arch/arm/mach-rockchip/rk3288-board.c
+++ b/arch/arm/mach-rockchip/rk3288-board.c
@@ -16,6 +16,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -56,6 +58,39 @@ int board_late_init(void)
return rk_board_late_init();
 }
 
+#ifndef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+static int veyron_init(void)
+{
+   struct udevice *dev;
+   struct clk clk;
+   int ret;
+
+   ret = regulator_get_by_platname("vdd_arm", );
+   if (ret)
+   return ret;
+
+   /* Slowly raise to max CPU voltage to prevent overshoot */
+   ret = regulator_set_value(dev, 120);
+   if (ret)
+   return ret;
+   udelay(175); /* Must wait for voltage to stabilize, 2mV/us */
+   ret = regulator_set_value(dev, 140);
+   if (ret)
+   return ret;
+   udelay(100); /* Must wait for voltage to stabilize, 2mV/us */
+
+   ret = rockchip_get_clk();
+   if (ret)
+   return ret;
+   clk.id = PLL_APLL;
+   ret = clk_set_rate(, 18);
+   if (IS_ERR_VALUE(ret))
+   return ret;
+
+   return 0;
+}
+#endif
+
 int board_init(void)
 {
 #ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
@@ -87,6 +122,15 @@ err:
 
return -1;
 #else
+   int ret;
+
+   /* We do some SoC one time setting here */
+   if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) {
+   ret = veyron_init();
+   if (ret)
+   return ret;
+   }
+
return 0;
 #endif
 }
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH v2 1/4] Makefile: Add a target to create the .cfg files

[Simon Glass]

A common requirement when converting CONFIG options to Kconfig is to check
that the effective configuration has not changed due to the conversion. Add
a target which creates this configuration (in the form of u-boot.cfg) but
does not build U-Boot. This speeds up the checking.

Signed-off-by: Simon Glass 
---

Changes in v2:
- Rebase to mainline with Masahiro's changes

 Makefile | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Makefile b/Makefile
index 37cbcb2..6729c1b 100644
--- a/Makefile
+++ b/Makefile
@@ -812,6 +812,8 @@ append = cat $(filter-out $< $(PHONY), $^) >> $@
 quiet_cmd_pad_cat = CAT $@
 cmd_pad_cat = $(cmd_objcopy) && $(append) || rm -f $@
 
+cfg: u-boot.cfg
+
 all:   $(ALL-y)
 ifeq ($(CONFIG_DM_I2C_COMPAT)$(CONFIG_SANDBOX),y)
@echo "= WARNING =="
@@ -1518,6 +1520,7 @@ help:
@echo  '  cscope  - Generate cscope index'
@echo  '  ubootrelease- Output the release version string (use with 
make -s)'
@echo  '  ubootversion- Output the version stored in Makefile (use 
with make -s)'
+   @echo  "  cfg - Don't build, just create the .cfg files"
@echo  ''
@echo  'Static analysers'
@echo  '  checkstack  - Generate a list of stack hogs'
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH v2 21/22] rockchip: video: Avoid using u8 in the HDMI driver

[Simon Glass]

It makes not sense using u8 to hold a value on a 32-bit or 64-bit machine.
It can only bloat the code by forcing the compiler to mask the value.
Change it to uint.

Signed-off-by: Simon Glass 
---

Changes in v2:
- Add new patch to avoid using u8 in the HDMI driver

 drivers/video/rockchip/rk_hdmi.c | 30 +++---
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c
index 72142dc..032b1de 100644
--- a/drivers/video/rockchip/rk_hdmi.c
+++ b/drivers/video/rockchip/rk_hdmi.c
@@ -132,8 +132,8 @@ static const u32 csc_coeff_default[3][4] = {
 
 static void hdmi_set_clock_regenerator(struct rk3288_hdmi *regs, u32 n, u32 
cts)
 {
-   u8 cts3;
-   u8 n3;
+   uint cts3;
+   uint n3;
 
/* first set ncts_atomic_write (if present) */
n3 = HDMI_AUD_N3_NCTS_ATOMIC_WRITE;
@@ -199,7 +199,7 @@ static void hdmi_audio_set_samplerate(struct rk3288_hdmi 
*regs, u32 pixel_clk)
 static void hdmi_video_sample(struct rk3288_hdmi *regs)
 {
u32 color_format = 0x01;
-   u8 val;
+   uint val;
 
val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
  ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
@@ -256,7 +256,7 @@ static void hdmi_video_packetize(struct rk3288_hdmi *regs)
u32 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
u32 remap_size = HDMI_VP_REMAP_YCC422_16BIT;
u32 color_depth = 0;
-   u8 val, vp_conf;
+   uint val, vp_conf;
 
/* set the packetizer registers */
val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
@@ -297,7 +297,7 @@ static void hdmi_video_packetize(struct rk3288_hdmi *regs)
output_select);
 }
 
-static inline void hdmi_phy_test_clear(struct rk3288_hdmi *regs, u8 bit)
+static inline void hdmi_phy_test_clear(struct rk3288_hdmi *regs, uint bit)
 {
clrsetbits_le32(>phy_tst0, HDMI_PHY_TST0_TSTCLR_MASK,
bit << HDMI_PHY_TST0_TSTCLR_OFFSET);
@@ -382,7 +382,7 @@ static void hdmi_phy_sel_interface_control(struct 
rk3288_hdmi *regs,
 static int hdmi_phy_configure(struct rk3288_hdmi *regs, u32 mpixelclock)
 {
ulong start;
-   u8 i, val;
+   uint i, val;
 
writel(HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
   >mc_flowctrl);
@@ -481,8 +481,8 @@ static int hdmi_phy_init(struct rk3288_hdmi *regs, uint 
mpixelclock)
 static void hdmi_av_composer(struct rk3288_hdmi *regs,
 const struct display_timing *edid)
 {
-   u8 mdataenablepolarity = 1;
-   u8 inv_val;
+   bool mdataenablepolarity = true;
+   uint inv_val;
uint hbl;
uint vbl;
 
@@ -553,7 +553,7 @@ static void hdmi_av_composer(struct rk3288_hdmi *regs,
 /* hdmi initialization step b.4 */
 static void hdmi_enable_video_path(struct rk3288_hdmi *regs)
 {
-   u8 clkdis;
+   uint clkdis;
 
/* control period minimum duration */
writel(12, >fc_ctrldur);
@@ -580,7 +580,7 @@ static void hdmi_enable_video_path(struct rk3288_hdmi *regs)
 /* workaround to clear the overflow condition */
 static void hdmi_clear_overflow(struct rk3288_hdmi *regs)
 {
-   u8 val, count;
+   uint val, count;
 
/* tmds software reset */
writel((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, >mc_swrstz);
@@ -614,7 +614,7 @@ static void hdmi_audio_fifo_reset(struct rk3288_hdmi *regs)
 
 static void hdmi_init_interrupt(struct rk3288_hdmi *regs)
 {
-   u8 ih_mute;
+   uint ih_mute;
 
/*
 * boot up defaults are:
@@ -650,11 +650,11 @@ static void hdmi_init_interrupt(struct rk3288_hdmi *regs)
writel(HDMI_IH_PHY_STAT0_HPD, >ih_phy_stat0);
 }
 
-static u8 hdmi_get_plug_in_status(struct rk3288_hdmi *regs)
+static int hdmi_get_plug_in_status(struct rk3288_hdmi *regs)
 {
-   u8 val = readl(>phy_stat0) & HDMI_PHY_HPD;
+   uint val = readl(>phy_stat0) & HDMI_PHY_HPD;
 
-   return !!(val);
+   return !!val;
 }
 
 static int hdmi_wait_for_hpd(struct rk3288_hdmi *regs)
@@ -753,7 +753,7 @@ static int hdmi_read_edid(struct rk3288_hdmi *regs, int 
block, u8 *buff)
return edid_read_err;
 }
 
-static u8 pre_buf[] = {
+static const u8 pre_buf[] = {
0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
0x04, 0x69, 0xfa, 0x23, 0xc8, 0x28, 0x01, 0x00,
0x10, 0x17, 0x01, 0x03, 0x80, 0x33, 0x1d, 0x78,
-- 
2.8.0.rc3.226.g39d4020

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Re: [U-Boot] [PATCH v3 3/5] ARMv8: Add basic PSCI framework

[Hongbo Zhang]

On Sat, Nov 12, 2016 at 12:06 AM, Tom Rini  wrote:
> On Mon, Nov 07, 2016 at 12:13:52PM +0800, macro.wav...@gmail.com wrote:
>
>> From: Hongbo Zhang 
>>
>> This patch introduces a generic ARMv8 PSCI framework, with all functions
>> returning a dummy ARM_PSCI_RET_NI (Not Implemented), then it is up to each
>> platform to implement their own functions based on this framework.
>>
>> Signed-off-by: Hongbo Zhang 
>
> Reviewed-by: Tom Rini 
>

Thanks Tom.

> --
> Tom
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