[U-Boot] [PATCH 2/8] ARM: rmobile: Represent SF partitioning with mtdparts on Alt
Add mtdparts description for the board. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- configs/alt_defconfig | 5 + 1 file changed, 5 insertions(+) diff --git a/configs/alt_defconfig b/configs/alt_defconfig index b0b864c1a1..49f344babd 100644 --- a/configs/alt_defconfig +++ b/configs/alt_defconfig @@ -46,6 +46,9 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nor0=spi0.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k(u-boot-env2),768k(u-boot),-(user)" CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_SPI_FLASH=y @@ -58,9 +61,11 @@ CONFIG_SYS_I2C_RCAR_IIC=y CONFIG_DM_MMC=y CONFIG_SH_MMCIF=y CONFIG_RENESAS_SDHI=y +CONFIG_MTD=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_MICREL=y CONFIG_DM_ETH=y CONFIG_SH_ETHER=y -- 2.16.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/8] ARM: rmobile: Enable MTD partitioning on Gen2 with SF
Enable MTD partitioning support on Gen2 boards with SPI NORs. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- include/configs/rcar-gen2-common.h | 8 1 file changed, 8 insertions(+) diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h index eadf5594c8..231c4ecea4 100644 --- a/include/configs/rcar-gen2-common.h +++ b/include/configs/rcar-gen2-common.h @@ -51,4 +51,12 @@ #define CONFIG_ENV_SIZE(CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN) +/* SF MTD */ +#if defined(CONFIG_SPI_FLASH_MTD) && !defined(CONFIG_SPL_BUILD) +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#else +#undef CONFIG_SPI_FLASH_MTD +#endif + #endif /* __RCAR_GEN2_COMMON_H */ -- 2.16.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 08/15] gpio: rmobile: Add R8A77990 E3 compatible
Add new compatible to the GPIO driver for R8A77990 E3 SoC.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
drivers/gpio/gpio-rcar.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
index b46621f76b..6fd1270640 100644
--- a/drivers/gpio/gpio-rcar.c
+++ b/drivers/gpio/gpio-rcar.c
@@ -175,6 +175,7 @@ static const struct udevice_id rcar_gpio_ids[] = {
{ .compatible = "renesas,gpio-r8a7796" },
{ .compatible = "renesas,gpio-r8a77965" },
{ .compatible = "renesas,gpio-r8a77970" },
+ { .compatible = "renesas,gpio-r8a77990" },
{ .compatible = "renesas,gpio-r8a77995" },
{ .compatible = "renesas,rcar-gen2-gpio" },
{ .compatible = "renesas,rcar-gen3-gpio" },
--
2.16.2
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[U-Boot] [PATCH 06/15] pinctrl: renesas: Add PORT_GP_11 helper macro
From: Takeshi Kihara This follows the style of existion PORT_GP_X macros and will be used by a follow-up patch for the r8a77990 SoC. Signed-off-by: Takeshi Kihara Cc: Nobuhiro Iwamatsu --- drivers/pinctrl/renesas/sh_pfc.h | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h index 22b8c95009..9755826201 100644 --- a/drivers/pinctrl/renesas/sh_pfc.h +++ b/drivers/pinctrl/renesas/sh_pfc.h @@ -368,9 +368,13 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info; PORT_GP_CFG_1(bank, 9, fn, sfx, cfg) #define PORT_GP_10(bank, fn, sfx) PORT_GP_CFG_10(bank, fn, sfx, 0) -#define PORT_GP_CFG_12(bank, fn, sfx, cfg) \ +#define PORT_GP_CFG_11(bank, fn, sfx, cfg) \ PORT_GP_CFG_10(bank, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 10, fn, sfx, cfg) +#define PORT_GP_11(bank, fn, sfx) PORT_GP_CFG_11(bank, fn, sfx, 0) + +#define PORT_GP_CFG_12(bank, fn, sfx, cfg) \ + PORT_GP_CFG_11(bank, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 11, fn, sfx, cfg) #define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0) -- 2.16.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 01/15] clk: renesas: Fix swapped arguments in debug message
The mul and div arguments were reported in reverse order in the debug
message, swap them to fix this.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
drivers/clk/renesas/clk-rcar-gen3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c
b/drivers/clk/renesas/clk-rcar-gen3.c
index 3a95647abe..4f10fd6352 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -230,7 +230,7 @@ static ulong gen3_clk_get_rate(struct clk *clk)
case CLK_TYPE_FF:
case CLK_TYPE_GEN3_PE: /* FIXME */
rate = (gen3_clk_get_rate() * core->mult) / core->div;
- debug("%s[%i] FIXED clk: parent=%i div=%i mul=%i => rate=%u\n",
+ debug("%s[%i] FIXED clk: parent=%i mul=%i div=%i => rate=%u\n",
__func__, __LINE__,
core->parent, core->mult, core->div, rate);
return rate;
--
2.16.2
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[U-Boot] [PATCH 13/15] ARM: dts: rmobile: Add Renesas Ebisu board support
From: Takeshi Kihara
Basic support for the Renesas Ebisu board based on R-Car E3:
- Memory,
- Main crystal,
- Serial console,
Signed-off-by: Takeshi Kihara
[shimoda: rebase and add SPDX-License-Identifier]
Signed-off-by: Yoshihiro Shimoda
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/r8a77990-ebisu.dts | 37 +
2 files changed, 38 insertions(+)
create mode 100644 arch/arm/dts/r8a77990-ebisu.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a0349a8975..6df8bc2fd6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -439,6 +439,7 @@ dtb-$(CONFIG_RCAR_GEN3) += \
r8a7796-salvator-x.dtb \
r8a77965-salvator-x.dtb \
r8a77970-eagle.dtb \
+ r8a77990-ebisu.dtb \
r8a77995-draak.dtb
dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \
diff --git a/arch/arm/dts/r8a77990-ebisu.dts b/arch/arm/dts/r8a77990-ebisu.dts
new file mode 100644
index 00..63ee1347bb
--- /dev/null
+++ b/arch/arm/dts/r8a77990-ebisu.dts
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Device Tree Source for the ebisu board
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a77990.dtsi"
+
+/ {
+ model = "Renesas Ebisu board based on r8a77990";
+ compatible = "renesas,ebisu", "renesas,r8a77990";
+
+ aliases {
+ serial0 =
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@4800 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x4800 0x0 0x3800>;
+ };
+};
+
+_clk {
+ clock-frequency = <4800>;
+};
+
+ {
+ status = "okay";
+};
--
2.16.2
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[U-Boot] [PATCH 09/15] mmc: renesas-sdhi: Add R8A77990 E3 compatible
Add new compatible to the Uniphier SD driver for R8A77990 E3 SoC.
Signed-off-by: Marek Vasut
Cc: Masahiro Yamada
Cc: Nobuhiro Iwamatsu
---
drivers/mmc/renesas-sdhi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index 62577895ee..ecdb088ac4 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -323,6 +323,7 @@ static const struct udevice_id renesas_sdhi_match[] = {
{ .compatible = "renesas,sdhi-r8a7796", .data = RENESAS_GEN3_QUIRKS },
{ .compatible = "renesas,sdhi-r8a77965", .data = RENESAS_GEN3_QUIRKS },
{ .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS },
+ { .compatible = "renesas,sdhi-r8a77990", .data = RENESAS_GEN3_QUIRKS },
{ .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS },
{ /* sentinel */ }
};
--
2.16.2
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Re: [U-Boot] [PATCH] spi: cadence_qspi: Fix compilation warning
On 05/07/2018 11:42 AM, Ley Foon Tan wrote:
> Cast data_bytes to integer.
>
> Compilation warning as below:
>
> In file included from include/linux/bug.h:7:0,
> from include/common.h:26,
> from drivers/spi/cadence_qspi.c:8:
> drivers/spi/cadence_qspi.c: In function ‘cadence_spi_xfer’:
> drivers/spi/cadence_qspi.c:211:8: warning: format ‘%d’ expects argument of
> type ‘int’, but argument 3 has type ‘size_t {aka long unsigned int}’
> [-Wformat=]
> debug("%s: len=%d [bytes]\n", __func__, data_bytes);
> ^
> include/linux/printk.h:37:21: note: in definition of macro ‘pr_fmt’
> #define pr_fmt(fmt) fmt
> ^~~
> include/log.h:142:2: note: in expansion of macro ‘debug_cond’
> debug_cond(_DEBUG, fmt, ##args)
> ^~
> drivers/spi/cadence_qspi.c:211:2: note: in expansion of macro ‘debug’
> debug("%s: len=%d [bytes]\n", __func__, data_bytes);
>
> Signed-off-by: Ley Foon Tan
> ---
> drivers/spi/cadence_qspi.c |2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
> index f80d073..dc4b5a4 100644
> --- a/drivers/spi/cadence_qspi.c
> +++ b/drivers/spi/cadence_qspi.c
> @@ -208,7 +208,7 @@ static int cadence_spi_xfer(struct udevice *dev, unsigned
> int bitlen,
> } else {
> data_bytes = bitlen / 8;
> }
> - debug("%s: len=%d [bytes]\n", __func__, data_bytes);
> + debug("%s: len=%d [bytes]\n", __func__, (int)data_bytes);
This should probably be %lu instead of the cast.
> /* Set Chip select */
> cadence_qspi_apb_chipselect(base, spi_chip_select(dev),
>
--
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] spi: cadence_qspi: Fix compilation warning
On Fri, Jun 1, 2018 at 4:07 PM, Marek Vasut wrote:
> On 05/07/2018 11:42 AM, Ley Foon Tan wrote:
>> Cast data_bytes to integer.
>>
>> Compilation warning as below:
>>
>> In file included from include/linux/bug.h:7:0,
>> from include/common.h:26,
>> from drivers/spi/cadence_qspi.c:8:
>> drivers/spi/cadence_qspi.c: In function ‘cadence_spi_xfer’:
>> drivers/spi/cadence_qspi.c:211:8: warning: format ‘%d’ expects argument of
>> type ‘int’, but argument 3 has type ‘size_t {aka long unsigned int}’
>> [-Wformat=]
>> debug("%s: len=%d [bytes]\n", __func__, data_bytes);
>> ^
>> include/linux/printk.h:37:21: note: in definition of macro ‘pr_fmt’
>> #define pr_fmt(fmt) fmt
>> ^~~
>> include/log.h:142:2: note: in expansion of macro ‘debug_cond’
>> debug_cond(_DEBUG, fmt, ##args)
>> ^~
>> drivers/spi/cadence_qspi.c:211:2: note: in expansion of macro ‘debug’
>> debug("%s: len=%d [bytes]\n", __func__, data_bytes);
>>
>> Signed-off-by: Ley Foon Tan
>> ---
>> drivers/spi/cadence_qspi.c |2 +-
>> 1 files changed, 1 insertions(+), 1 deletions(-)
>>
>> diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
>> index f80d073..dc4b5a4 100644
>> --- a/drivers/spi/cadence_qspi.c
>> +++ b/drivers/spi/cadence_qspi.c
>> @@ -208,7 +208,7 @@ static int cadence_spi_xfer(struct udevice *dev,
>> unsigned int bitlen,
>> } else {
>> data_bytes = bitlen / 8;
>> }
>> - debug("%s: len=%d [bytes]\n", __func__, data_bytes);
>> + debug("%s: len=%d [bytes]\n", __func__, (int)data_bytes);
>
> This should probably be %lu instead of the cast.
Okay.
>
>> /* Set Chip select */
>> cadence_qspi_apb_chipselect(base, spi_chip_select(dev),
>>
>
Regards
Ley Foon
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Re: [U-Boot] [PATCH] spi: cadence_qspi: Fix warning cast from pointer to integer of different size
On Fri, Jun 1, 2018 at 4:07 PM, Marek Vasut wrote:
> On 05/07/2018 11:42 AM, Ley Foon Tan wrote:
>> Cast to ulong data type.
>>
>> Compilation warning as below:
>>
>> CC spl/drivers/spi/cadence_qspi_apb.o
>> LD spl/lib/built-in.o
>> drivers/spi/cadence_qspi_apb.c: In function
>> ‘cadence_qspi_apb_indirect_write_setup’:
>> drivers/spi/cadence_qspi_apb.c:696:18: warning: cast from pointer to integer
>> of different size [-Wpointer-to-int-cast]
>> cmdlen, (unsigned int)cmdbuf);
>>
>> Signed-off-by: Ley Foon Tan
>> ---
>> drivers/spi/cadence_qspi_apb.c |4 ++--
>> 1 files changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
>> index aa3a9ff..5bef0ae 100644
>> --- a/drivers/spi/cadence_qspi_apb.c
>> +++ b/drivers/spi/cadence_qspi_apb.c
>> @@ -692,8 +692,8 @@ int cadence_qspi_apb_indirect_write_setup(struct
>> cadence_spi_platdata *plat,
>> unsigned int addr_bytes = cmdlen > 4 ? 4 : 3;
>>
>> if (cmdlen < 4 || cmdbuf == NULL) {
>> - printf("QSPI: iInvalid input argument, len %d cmdbuf 0x%08x\n",
>> -cmdlen, (unsigned int)cmdbuf);
>> + printf("QSPI: Invalid input argument, len %d cmdbuf 0x%08lx\n",
>> +cmdlen, (unsigned long)cmdbuf);
>
> %p ?
Yes, can use %p.
>
>> return -EINVAL;
>> }
>> /* Setup the indirect trigger address */
>>
>
>
Regards
Ley Foon
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[U-Boot] build fail due to dependence error
Hi Guys, I met below error from time to time when build U-Boot project. fixdep: error opening config file: arch/arm/include/asm/arch/hardware.h: No such file or directory The folder 'arch/arm/include/asm/arch' is a link for 'arch/arm/include/asm/arch-rockchip', which is dynamic generate by build system, I thinks there should be some dependency issue? How to fix this kind of issue? Thanks, - Kever ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] spi: cadence_qspi: Fix compilation warning
On 06/01/2018 10:52 AM, Ley Foon Tan wrote:
> Use "%lu" for size_t data type.
>
> Compilation warning as below:
>
> In file included from include/linux/bug.h:7:0,
> from include/common.h:26,
> from drivers/spi/cadence_qspi.c:8:
> drivers/spi/cadence_qspi.c: In function ‘cadence_spi_xfer’:
> drivers/spi/cadence_qspi.c:211:8: warning: format ‘%d’ expects argument of
> type ‘int’, but argument 3 has type ‘size_t {aka long unsigned int}’
> [-Wformat=]
> debug("%s: len=%d [bytes]\n", __func__, data_bytes);
> ^
> include/linux/printk.h:37:21: note: in definition of macro ‘pr_fmt’
> #define pr_fmt(fmt) fmt
> ^~~
> include/log.h:142:2: note: in expansion of macro ‘debug_cond’
> debug_cond(_DEBUG, fmt, ##args)
> ^~
> drivers/spi/cadence_qspi.c:211:2: note: in expansion of macro ‘debug’
> debug("%s: len=%d [bytes]\n", __func__, data_bytes);
>
> Signed-off-by: Ley Foon Tan
Acked-by: Marek Vasut
btw missing [PATCH v2 2/2] in the SUBJECT ...
> ---
> v2: use "%lu" instead of cast data type to ulong.
> ---
> drivers/spi/cadence_qspi.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
> index 91742ba..63249c5 100644
> --- a/drivers/spi/cadence_qspi.c
> +++ b/drivers/spi/cadence_qspi.c
> @@ -207,7 +207,7 @@ static int cadence_spi_xfer(struct udevice *dev, unsigned
> int bitlen,
> } else {
> data_bytes = bitlen / 8;
> }
> - debug("%s: len=%d [bytes]\n", __func__, data_bytes);
> + debug("%s: len=%lu [bytes]\n", __func__, data_bytes);
>
> /* Set Chip select */
> cadence_qspi_apb_chipselect(base, spi_chip_select(dev),
>
--
Best regards,
Marek Vasut
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Re: [U-Boot] [PULL] u-boot-socfpga/master
On 06/01/2018 02:23 AM, Tom Rini wrote: > On Thu, May 31, 2018 at 08:06:50PM +0200, Marek Vasut wrote: > >> The following changes since commit c3c863880479edeb5b08226e622d13c91326e4a7: >> >> add FIT data-position & data-offset property support (2018-05-26 >> 18:19:19 -0400) >> >> are available in the Git repository at: >> >> git://git.denx.de/u-boot-socfpga.git master >> >> for you to fetch changes up to a0029aea787286c72ca2411475f95519bf9a7f34: >> >> arm: socfpga: stratix10: Enable Stratix10 SoC build (2018-05-29 >> 18:34:39 +0200) >> > > NAK. This adds warnings (which are errors in travis): > https://travis-ci.org/trini/u-boot/jobs/386306955#L866 Ley, can you send me a fix ? -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 6/8] ARM: rmobile: Represent SF partitioning with mtdparts on Porter
Add mtdparts description for the board. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- configs/porter_defconfig | 5 + 1 file changed, 5 insertions(+) diff --git a/configs/porter_defconfig b/configs/porter_defconfig index b04627efa3..0588387cbd 100644 --- a/configs/porter_defconfig +++ b/configs/porter_defconfig @@ -46,6 +46,9 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nor0=spi0.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k(u-boot-env2),768k(u-boot),-(user)" CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_SPI_FLASH=y @@ -57,9 +60,11 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_RCAR_IIC=y CONFIG_DM_MMC=y CONFIG_RENESAS_SDHI=y +CONFIG_MTD=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_MICREL=y CONFIG_DM_ETH=y CONFIG_SH_ETHER=y -- 2.16.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 14/15] ARM: renesas: Add R8A77990 E3 Ebisu board
Add support for the R8A77990 Ebisu board.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
arch/arm/dts/r8a77990-ebisu-u-boot.dts | 10
arch/arm/dts/r8a77990-u-boot.dtsi | 9
arch/arm/mach-rmobile/Kconfig.64 | 6 +++
board/renesas/ebisu/Kconfig| 15 ++
board/renesas/ebisu/MAINTAINERS| 6 +++
board/renesas/ebisu/Makefile | 9
board/renesas/ebisu/ebisu.c| 87 ++
configs/r8a77990_ebisu_defconfig | 64 +
include/configs/ebisu.h| 34 +
9 files changed, 240 insertions(+)
create mode 100644 arch/arm/dts/r8a77990-ebisu-u-boot.dts
create mode 100644 arch/arm/dts/r8a77990-u-boot.dtsi
create mode 100644 board/renesas/ebisu/Kconfig
create mode 100644 board/renesas/ebisu/MAINTAINERS
create mode 100644 board/renesas/ebisu/Makefile
create mode 100644 board/renesas/ebisu/ebisu.c
create mode 100644 configs/r8a77990_ebisu_defconfig
create mode 100644 include/configs/ebisu.h
diff --git a/arch/arm/dts/r8a77990-ebisu-u-boot.dts
b/arch/arm/dts/r8a77990-ebisu-u-boot.dts
new file mode 100644
index 00..28bc497046
--- /dev/null
+++ b/arch/arm/dts/r8a77990-ebisu-u-boot.dts
@@ -0,0 +1,10 @@
+/*
+ * Device Tree Source extras for U-Boot for the Ebisu board
+ *
+ * Copyright (C) 2018 Marek Vasut
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include "r8a77990-ebisu.dts"
+#include "r8a77990-u-boot.dtsi"
diff --git a/arch/arm/dts/r8a77990-u-boot.dtsi
b/arch/arm/dts/r8a77990-u-boot.dtsi
new file mode 100644
index 00..30a9f0b8ea
--- /dev/null
+++ b/arch/arm/dts/r8a77990-u-boot.dtsi
@@ -0,0 +1,9 @@
+/*
+ * Device Tree Source extras for U-Boot on RCar R8A77990 SoC
+ *
+ * Copyright (C) 2018 Marek Vasut
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include "r8a779x-u-boot.dtsi"
diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64
index 6b93d25358..cb9f569e5f 100644
--- a/arch/arm/mach-rmobile/Kconfig.64
+++ b/arch/arm/mach-rmobile/Kconfig.64
@@ -34,6 +34,11 @@ config TARGET_EAGLE
help
Support for Renesas R-Car Gen3 Eagle platform
+config TARGET_EBISU
+ bool "Ebisu board"
+ help
+ Support for Renesas R-Car Gen3 Ebisu platform
+
config TARGET_SALVATOR_X
bool "Salvator-X board"
help
@@ -51,6 +56,7 @@ config SYS_SOC
source "board/renesas/draak/Kconfig"
source "board/renesas/eagle/Kconfig"
+source "board/renesas/ebisu/Kconfig"
source "board/renesas/salvator-x/Kconfig"
source "board/renesas/ulcb/Kconfig"
diff --git a/board/renesas/ebisu/Kconfig b/board/renesas/ebisu/Kconfig
new file mode 100644
index 00..f500a94c9a
--- /dev/null
+++ b/board/renesas/ebisu/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EBISU
+
+config SYS_SOC
+ default "rmobile"
+
+config SYS_BOARD
+ default "ebisu"
+
+config SYS_VENDOR
+ default "renesas"
+
+config SYS_CONFIG_NAME
+ default "ebisu"
+
+endif
diff --git a/board/renesas/ebisu/MAINTAINERS b/board/renesas/ebisu/MAINTAINERS
new file mode 100644
index 00..facad520ca
--- /dev/null
+++ b/board/renesas/ebisu/MAINTAINERS
@@ -0,0 +1,6 @@
+EBISU BOARD
+M: Marek Vasut
+S: Maintained
+F: board/renesas/ebisu/
+F: include/configs/ebisu.h
+F: configs/r8a77990_ebisu_defconfig
diff --git a/board/renesas/ebisu/Makefile b/board/renesas/ebisu/Makefile
new file mode 100644
index 00..2741035c57
--- /dev/null
+++ b/board/renesas/ebisu/Makefile
@@ -0,0 +1,9 @@
+#
+# board/renesas/ebisu/Makefile
+#
+# Copyright (C) 2018 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := ebisu.o
diff --git a/board/renesas/ebisu/ebisu.c b/board/renesas/ebisu/ebisu.c
new file mode 100644
index 00..92062141a2
--- /dev/null
+++ b/board/renesas/ebisu/ebisu.c
@@ -0,0 +1,87 @@
+/*
+ * board/renesas/ebisu/ebisu.c
+ * This file is Ebisu board support.
+ *
+ * Copyright (C) 2018 Marek Vasut
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void s_init(void)
+{
+}
+
+#define TMU0_MSTP125 BIT(25) /* secure */
+
+int board_early_init_f(void)
+{
+ /* TMU0 */
+ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x5;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ if (fdtdec_setup_memory_size() != 0)
+ return -EINVAL;
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ fdtdec_setup_memory_banksize();
+
+ return 0;
+}
+
+#define RST_BASE 0xE616
+#define RST_CA57RESCNT (RST_BASE + 0x40)
+#define RST_CA53RESCNT (RST_BASE + 0x44)
Re: [U-Boot] [PATCH] arm: socfpga: Add do_bridge_reset for Arria 10
On 06/01/2018 10:13 AM, Ley Foon Tan wrote:
> Add do_bridge_reset() function for Arria 10, it is required by misc.c.
>
> arch/arm/mach-socfpga/built-in.o: In function `do_bridge':
> arch/arm/mach-socfpga/misc.c:221: undefined reference to `do_bridge_reset'
> make[1]: *** [u-boot] Error 1
>
> Signed-off-by: Ley Foon Tan
> ---
> arch/arm/mach-socfpga/misc_arria10.c | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm/mach-socfpga/misc_arria10.c
> b/arch/arm/mach-socfpga/misc_arria10.c
> index 47a9d50..a75cbc4 100644
> --- a/arch/arm/mach-socfpga/misc_arria10.c
> +++ b/arch/arm/mach-socfpga/misc_arria10.c
> @@ -14,6 +14,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -262,3 +263,11 @@ int arch_misc_init(void)
> return socfpga_eth_reset();
> }
> #endif
> +
> +void do_bridge_reset(int enable)
> +{
> + if (enable)
> + socfpga_reset_deassert_bridges_handoff();
> + else
> + socfpga_bridges_reset();
> +}
>
Ignore my previous comment, applied.
--
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v3 1/2] sunxi-mmc: use new mode on A64
On Thu, May 31, 2018 at 09:43:20AM -0700, Vasily Khoruzhick wrote:
> On Thu, May 31, 2018 at 5:00 AM, Maxime Ripard
> wrote:
> > On Wed, May 30, 2018 at 09:02:18PM -0700, Vasily Khoruzhick wrote:
> >> That is necessary for using automatic calibration on A64 eMMC.
> >>
> >> Signed-off-by: Vasily khoruzhick
> >> ---
> >> arch/arm/mach-sunxi/Kconfig | 1 +
> >> drivers/mmc/sunxi_mmc.c | 4 ++--
> >> 2 files changed, 3 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> >> index 66fb094ac5..8a35033d1f 100644
> >> --- a/arch/arm/mach-sunxi/Kconfig
> >> +++ b/arch/arm/mach-sunxi/Kconfig
> >> @@ -257,6 +257,7 @@ config MACH_SUN50I
> >> select SUNXI_GEN_SUN6I
> >> select SUN6I_PRCM
> >> select SUNXI_HIGH_SRAM
> >> + select MMC_SUNXI_HAS_NEW_MODE
> >> select SUPPORT_SPL
> >> select SUNXI_DRAM_DW
> >> select SUNXI_DRAM_DW_32BIT
> >> diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
> >> index fe6d82c7b4..3bffb1b02e 100644
> >> --- a/drivers/mmc/sunxi_mmc.c
> >> +++ b/drivers/mmc/sunxi_mmc.c
> >> @@ -165,10 +165,10 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv
> >> *priv, unsigned int hz)
> >> }
> >>
> >> if (new_mode) {
> >> -#ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE
> >> +#if defined(CONFIG_MMC_SUNXI_HAS_NEW_MODE) && !defined(CONFIG_MACH_SUN50I)
> >> val = CCM_MMC_CTRL_MODE_SEL_NEW;
> >> - setbits_le32(>reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);
> >> #endif
> >> + setbits_le32(>reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);
> >
> > This is slightly more complicated than that, we have three cases we
> > need to support:
> > - Devices without the new mode (A31 and before)
> > - Devices with support for the new mode that can be toggled (A23/A33 to
> > H3/H5 iirc)
> > - Devices with support for the new mode only
>
> Right.
>
> > The latter was introduced by the A64, but is also found on other SoCs
> > now (such as the H6).
> >
> > So I guess here we need an extra config option to handle it, or even
> > better, base the decision on the compatible like we're doing in Linux.
>
> OK, sounds reasonable. However using compatibles (and thus switching
> to DM_MMC) would be more invasive chance and I won't be able to test
> it on all platforms that use sunxi_mmc driver.
We already have DM_MMC support in the driver. The only thing that
seems to be missing are the A64 compatibles, and to test. But most of
the driver is shared, so I don't expect a lot of trouble there.
Maxime
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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[U-Boot] [PATCH] spi: cadence_qspi: Fix warning cast from pointer to integer of different size
Use "%p" to print cmdbuf.
Compilation warning as below:
CC spl/drivers/spi/cadence_qspi_apb.o
LD spl/lib/built-in.o
drivers/spi/cadence_qspi_apb.c: In function
‘cadence_qspi_apb_indirect_write_setup’:
drivers/spi/cadence_qspi_apb.c:696:18: warning: cast from pointer to integer of
different size [-Wpointer-to-int-cast]
cmdlen, (unsigned int)cmdbuf);
Signed-off-by: Ley Foon Tan
---
v2: Use "%p" instead of cast to ulong data type.
---
drivers/spi/cadence_qspi_apb.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index aa3a9ff..a8af352 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -692,8 +692,8 @@ int cadence_qspi_apb_indirect_write_setup(struct
cadence_spi_platdata *plat,
unsigned int addr_bytes = cmdlen > 4 ? 4 : 3;
if (cmdlen < 4 || cmdbuf == NULL) {
- printf("QSPI: iInvalid input argument, len %d cmdbuf 0x%08x\n",
- cmdlen, (unsigned int)cmdbuf);
+ printf("QSPI: Invalid input argument, len %d cmdbuf %p\n",
+ cmdlen, cmdbuf);
return -EINVAL;
}
/* Setup the indirect trigger address */
--
2.2.2
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Re: [U-Boot] [U-Boot,1/1] Remove snapshot.commit
On 05/31/2018 08:17 PM, Tom Rini wrote: > On Sun, May 27, 2018 at 07:54:16PM +0200, Heinrich Schuchardt > wrote: > >> The file is not referenced anywhere. To display a change log we >> have the 'git log' command. >> >> Signed-off-by: Heinrich Schuchardt > > Applied to u-boot/master, thanks! > Hello Tom, could you, please, push to git.denx.de. Best regards Heinrich ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] spi: cadence_qspi: Fix compilation warning
Use "%lu" for size_t data type.
Compilation warning as below:
In file included from include/linux/bug.h:7:0,
from include/common.h:26,
from drivers/spi/cadence_qspi.c:8:
drivers/spi/cadence_qspi.c: In function ‘cadence_spi_xfer’:
drivers/spi/cadence_qspi.c:211:8: warning: format ‘%d’ expects argument of type
‘int’, but argument 3 has type ‘size_t {aka long unsigned int}’ [-Wformat=]
debug("%s: len=%d [bytes]\n", __func__, data_bytes);
^
include/linux/printk.h:37:21: note: in definition of macro ‘pr_fmt’
#define pr_fmt(fmt) fmt
^~~
include/log.h:142:2: note: in expansion of macro ‘debug_cond’
debug_cond(_DEBUG, fmt, ##args)
^~
drivers/spi/cadence_qspi.c:211:2: note: in expansion of macro ‘debug’
debug("%s: len=%d [bytes]\n", __func__, data_bytes);
Signed-off-by: Ley Foon Tan
---
v2: use "%lu" instead of cast data type to ulong.
---
drivers/spi/cadence_qspi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 91742ba..63249c5 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -207,7 +207,7 @@ static int cadence_spi_xfer(struct udevice *dev, unsigned
int bitlen,
} else {
data_bytes = bitlen / 8;
}
- debug("%s: len=%d [bytes]\n", __func__, data_bytes);
+ debug("%s: len=%lu [bytes]\n", __func__, data_bytes);
/* Set Chip select */
cadence_qspi_apb_chipselect(base, spi_chip_select(dev),
--
2.2.2
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[U-Boot] [PATCH 03/15] clk: renesas: Add PLL1 and PLL3 dividers
Add and use the PLL1 and PLL3 dividers.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
drivers/clk/renesas/clk-rcar-gen3.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c
b/drivers/clk/renesas/clk-rcar-gen3.c
index 834cd5ac58..f2550598a4 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -200,9 +200,11 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
case CLK_TYPE_GEN3_PLL1:
rate = gen3_clk_get_rate64() * pll_config->pll1_mult;
- debug("%s[%i] PLL1 clk: parent=%i mul=%i => rate=%llu\n",
+ rate /= pll_config->pll1_div;
+ debug("%s[%i] PLL1 clk: parent=%i mul=%i div=%i => rate=%llu\n",
__func__, __LINE__,
- core->parent, pll_config->pll1_mult, rate);
+ core->parent, pll_config->pll1_mult,
+ pll_config->pll1_div, rate);
return rate;
case CLK_TYPE_GEN3_PLL2:
@@ -215,9 +217,11 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
case CLK_TYPE_GEN3_PLL3:
rate = gen3_clk_get_rate64() * pll_config->pll3_mult;
- debug("%s[%i] PLL3 clk: parent=%i mul=%i => rate=%llu\n",
+ rate /= pll_config->pll3_div;
+ debug("%s[%i] PLL3 clk: parent=%i mul=%i div=%i => rate=%llu\n",
__func__, __LINE__,
- core->parent, pll_config->pll3_mult, rate);
+ core->parent, pll_config->pll3_mult,
+ pll_config->pll3_div, rate);
return rate;
case CLK_TYPE_GEN3_PLL4:
--
2.16.2
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[U-Boot] [PATCH 04/15] clk: renesas: Add PE clock handling
The PE clock have two parents, add support for picking the correct
one and deriving the clock from it.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
drivers/clk/renesas/clk-rcar-gen3.c | 40 +
drivers/clk/renesas/rcar-gen3-cpg.h | 6 --
2 files changed, 40 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c
b/drivers/clk/renesas/clk-rcar-gen3.c
index f2550598a4..99698b1f46 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -85,6 +85,28 @@ static const struct sd_div_table cpg_sd_div_table[] = {
CPG_SD_DIV_TABLE_DATA(1,0,4, 0, 32),
};
+static int gen3_clk_get_parent(struct gen3_clk_priv *priv, struct clk *clk,
+ struct cpg_mssr_info *info, struct clk *parent)
+{
+ const struct cpg_core_clk *core;
+ int ret;
+
+ if (!renesas_clk_is_mod(clk)) {
+ ret = renesas_clk_get_core(clk, info, );
+ if (ret)
+ return ret;
+
+ if (core->type == CLK_TYPE_GEN3_PE) {
+ parent->dev = clk->dev;
+ parent->id = core->parent >> (priv->sscg ? 16 : 0);
+ parent->id &= 0x;
+ return 0;
+ }
+ }
+
+ return renesas_clk_get_parent(clk, info, parent);
+}
+
static int gen3_clk_setup_sdif_div(struct clk *clk)
{
struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
@@ -93,7 +115,7 @@ static int gen3_clk_setup_sdif_div(struct clk *clk)
struct clk parent;
int ret;
- ret = renesas_clk_get_parent(clk, info, );
+ ret = gen3_clk_get_parent(priv, clk, info, );
if (ret) {
printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
return ret;
@@ -142,13 +164,13 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
const struct cpg_core_clk *core;
const struct rcar_gen3_cpg_pll_config *pll_config =
priv->cpg_pll_config;
- u32 value, mult, prediv, postdiv;
+ u32 value, mult, div, prediv, postdiv;
u64 rate = 0;
int i, ret;
debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id);
- ret = renesas_clk_get_parent(clk, info, );
+ ret = gen3_clk_get_parent(priv, clk, info, );
if (ret) {
printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
return ret;
@@ -233,13 +255,21 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
return rate;
case CLK_TYPE_FF:
- case CLK_TYPE_GEN3_PE: /* FIXME */
rate = (gen3_clk_get_rate64() * core->mult) / core->div;
debug("%s[%i] FIXED clk: parent=%i mul=%i div=%i =>
rate=%llu\n",
__func__, __LINE__,
core->parent, core->mult, core->div, rate);
return rate;
+ case CLK_TYPE_GEN3_PE:
+ div = (core->div >> (priv->sscg ? 16 : 0)) & 0x;
+ rate = gen3_clk_get_rate64() / div;
+ debug("%s[%i] PE clk: parent=%i div=%u => rate=%llu\n",
+ __func__, __LINE__,
+ (core->parent >> (priv->sscg ? 16 : 0)) & 0x,
+ div, rate);
+ return rate;
+
case CLK_TYPE_GEN3_SD: /* FIXME */
value = readl(priv->base + core->offset);
value &= CPG_SD_STP_MASK | CPG_SD_FC_MASK;
@@ -351,6 +381,8 @@ int gen3_clk_probe(struct udevice *dev)
if (!priv->cpg_pll_config->extal_div)
return -EINVAL;
+ priv->sscg = !(cpg_mode & BIT(12));
+
ret = clk_get_by_name(dev, "extal", >clk_extal);
if (ret < 0)
return ret;
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h
b/drivers/clk/renesas/rcar-gen3-cpg.h
index 2f410df42a..58e71f363c 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -31,8 +31,9 @@ enum rcar_gen3_clk_types {
DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPC, _parent, .offset = _offset)
#define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
_div_clean) \
- DEF_BASE(_name, _id, CLK_TYPE_FF, \
-(_parent_clean), .div = (_div_clean), 1)
+ DEF_BASE(_name, _id, CLK_TYPE_GEN3_PE, \
+(_parent_sscg) << 16 | (_parent_clean),\
+.div = (_div_sscg) << 16 | (_div_clean))
struct rcar_gen3_cpg_pll_config {
u8 extal_div;
@@ -49,6 +50,7 @@ struct gen3_clk_priv {
struct cpg_mssr_info*info;
struct clk clk_extal;
struct clk clk_extalr;
+ boolsscg;
const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
};
--
[U-Boot] [PATCH 07/15] pinctrl: renesas: Initial R8A77990 PFC support
This patch adds initial pinctrl driver to support for the R8A77990 SoC. Signed-off-by: Takeshi Kihara Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- drivers/pinctrl/renesas/Kconfig| 11 + drivers/pinctrl/renesas/Makefile |1 + drivers/pinctrl/renesas/pfc-r8a77990.c | 1732 drivers/pinctrl/renesas/pfc.c | 11 + drivers/pinctrl/renesas/sh_pfc.h |1 + 5 files changed, 1756 insertions(+) create mode 100644 drivers/pinctrl/renesas/pfc-r8a77990.c diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index 5e6d854065..1baab9088a 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -94,6 +94,17 @@ config PINCTRL_PFC_R8A77970 the GPIO definitions and pin control functions for each available multiplex function. +config PINCTRL_PFC_R8A77990 + bool "Renesas RCar Gen3 R8A77990 pin control driver" + def_bool y if R8A77990 + depends on PINCTRL_PFC + help + Support pin multiplexing control on Renesas RCar Gen3 R8A77990 SoCs. + + The driver is controlled by a device tree node which contains both + the GPIO definitions and pin control functions for each available + multiplex function. + config PINCTRL_PFC_R8A77995 bool "Renesas RCar Gen3 R8A77995 pin control driver" def_bool y if R8A77995 diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile index 29b9912f83..62bc40b8c1 100644 --- a/drivers/pinctrl/renesas/Makefile +++ b/drivers/pinctrl/renesas/Makefile @@ -7,4 +7,5 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o +obj-$(CONFIG_PINCTRL_PFC_R8A77990) += pfc-r8a77990.o obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c new file mode 100644 index 00..f32e528f93 --- /dev/null +++ b/drivers/pinctrl/renesas/pfc-r8a77990.c @@ -0,0 +1,1732 @@ +/* + * R8A77990 processor support - PFC hardware block. + * + * Copyright (C) 2018 Renesas Electronics Corp. + * + * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c + * + * R-Car Gen3 processor support - PFC hardware block. + * + * Copyright (C) 2015 Renesas Electronics Corporation + * + * SPDX-License-Identifier:GPL-2.0 + */ + +#include +#include +#include +#include +#include + +#include "sh_pfc.h" + +#define CPU_ALL_PORT(fn, sfx) \ + PORT_GP_18(0, fn, sfx), \ + PORT_GP_23(1, fn, sfx), \ + PORT_GP_26(2, fn, sfx), \ + PORT_GP_16(3, fn, sfx), \ + PORT_GP_11(4, fn, sfx), \ + PORT_GP_20(5, fn, sfx), \ + PORT_GP_18(6, fn, sfx) + +/* + * F_() : just information + * FM() : macro for FN_xxx / xxx_MARK + */ + +/* GPSR0 */ +#define GPSR0_17 F_(SDA4,IP7_27_24) +#define GPSR0_16 F_(SCL4,IP7_23_20) +#define GPSR0_15 F_(D15, IP7_19_16) +#define GPSR0_14 F_(D14, IP7_15_12) +#define GPSR0_13 F_(D13, IP7_11_8) +#define GPSR0_12 F_(D12, IP7_7_4) +#define GPSR0_11 F_(D11, IP7_3_0) +#define GPSR0_10 F_(D10, IP6_31_28) +#define GPSR0_9F_(D9, IP6_27_24) +#define GPSR0_8F_(D8, IP6_23_20) +#define GPSR0_7F_(D7, IP6_19_16) +#define GPSR0_6F_(D6, IP6_15_12) +#define GPSR0_5F_(D5, IP6_11_8) +#define GPSR0_4F_(D4, IP6_7_4) +#define GPSR0_3F_(D3, IP6_3_0) +#define GPSR0_2F_(D2, IP5_31_28) +#define GPSR0_1F_(D1, IP5_27_24) +#define GPSR0_0F_(D0, IP5_23_20) + +/* GPSR1 */ +#define GPSR1_22 F_(WE0_N, IP5_19_16) +#define GPSR1_21 F_(CS0_N, IP5_15_12) +#define GPSR1_20 FM(CLKOUT) +#define GPSR1_19 F_(A19, IP5_11_8) +#define GPSR1_18 F_(A18, IP5_7_4) +#define GPSR1_17 F_(A17, IP5_3_0) +#define GPSR1_16 F_(A16, IP4_31_28) +#define GPSR1_15 F_(A15, IP4_27_24) +#define GPSR1_14 F_(A14, IP4_23_20) +#define GPSR1_13 F_(A13, IP4_19_16) +#define GPSR1_12 F_(A12, IP4_15_12) +#define GPSR1_11 F_(A11, IP4_11_8) +#define GPSR1_10 F_(A10, IP4_7_4) +#define GPSR1_9F_(A9, IP4_3_0) +#define GPSR1_8F_(A8, IP3_31_28) +#define
[U-Boot] [PATCH 15/15] ARM: dts: rmobile: Sync R8A77990 Ebisu DTS with Linux
Import the R8A77990 and Ebisu DTS from linux-next to get the latest
version. This makes AVB ethernet work in U-Boot since the ethernet
node is now present in DT, as well as GPIOs.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
arch/arm/dts/r8a77990-ebisu.dts | 28 +
arch/arm/dts/r8a77990.dtsi | 220 +---
2 files changed, 213 insertions(+), 35 deletions(-)
diff --git a/arch/arm/dts/r8a77990-ebisu.dts b/arch/arm/dts/r8a77990-ebisu.dts
index 63ee1347bb..7a09d0524f 100644
--- a/arch/arm/dts/r8a77990-ebisu.dts
+++ b/arch/arm/dts/r8a77990-ebisu.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include "r8a77990.dtsi"
+#include
/ {
model = "Renesas Ebisu board based on r8a77990";
@@ -14,6 +15,7 @@
aliases {
serial0 =
+ ethernet0 =
};
chosen {
@@ -28,10 +30,36 @@
};
};
+ {
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+ renesas,no-ether-link;
+ phy-handle = <>;
+ phy-mode = "rgmii-txid";
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ rxc-skew-ps = <1500>;
+ reg = <0>;
+ interrupt-parent = <>;
+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = < 20 GPIO_ACTIVE_LOW>;
+ };
+};
+
_clk {
clock-frequency = <4800>;
};
+ {
+ avb_pins: avb {
+ mux {
+ groups = "avb_link", "avb_mii";
+ function = "avb";
+ };
+ };
+};
+
{
status = "okay";
};
diff --git a/arch/arm/dts/r8a77990.dtsi b/arch/arm/dts/r8a77990.dtsi
index 310bfd9d88..be4f519711 100644
--- a/arch/arm/dts/r8a77990.dtsi
+++ b/arch/arm/dts/r8a77990.dtsi
@@ -27,9 +27,8 @@
enable-method = "psci";
};
- L2_CA53: cache-controller@0 {
+ L2_CA53: cache-controller-0 {
compatible = "cache";
- reg = <0>;
power-domains = < 21>;
cache-unified;
cache-level = <2>;
@@ -43,8 +42,14 @@
clock-frequency = <0>;
};
+ pmu_a53 {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts-extended = < GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <_0>;
+ };
+
psci {
- compatible = "arm,psci-0.2";
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
@@ -55,39 +60,114 @@
#size-cells = <2>;
ranges;
- gic: interrupt-controller@f101 {
- compatible = "arm,gic-400";
- #interrupt-cells = <3>;
- #address-cells = <0>;
+ gpio0: gpio@e605 {
+ compatible = "renesas,gpio-r8a77990",
+"renesas,rcar-gen3-gpio";
+ reg = <0 0xe605 0 0x50>;
+ interrupts = ;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = < 0 0 18>;
+ #interrupt-cells = <2>;
interrupt-controller;
- reg = <0x0 0xf101 0 0x1000>,
- <0x0 0xf102 0 0x2>,
- <0x0 0xf104 0 0x2>,
- <0x0 0xf106 0 0x2>;
- interrupts = ;
- clocks = < CPG_MOD 408>;
- clock-names = "clk";
+ clocks = < CPG_MOD 912>;
power-domains = < 32>;
- resets = < 408>;
+ resets = < 912>;
+ };
+
+ gpio1: gpio@e6051000 {
+ compatible = "renesas,gpio-r8a77990",
+"renesas,rcar-gen3-gpio";
+ reg = <0 0xe6051000 0 0x50>;
+ interrupts = ;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = < 0 32 23>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = < CPG_MOD 911>;
+ power-domains = < 32>;
+ resets = < 911>;
+ };
+
+ gpio2: gpio@e6052000 {
+ compatible = "renesas,gpio-r8a77990",
+"renesas,rcar-gen3-gpio";
+ reg = <0 0xe6052000 0 0x50>;
+ interrupts = ;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = < 0 64 26>;
+
[U-Boot] [PATCH 12/15] ARM: dts: rmobile: Add Renesas R8A77990 SoC support
From: Yoshihiro Shimoda
This patch adds basic support for the Renesas R-Car E3 (R8A77990) SoC:
- PSCI
- CPU (single)
- Cache controller
- Main clocks and controller
- Interrupt controller
- Timer
- PMU
- Reset controller
- Product register
- System controller
- UART for console
Inspried by a patch by Takeshi Kihara in the BSP.
Signed-off-by: Yoshihiro Shimoda
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
arch/arm/dts/r8a77990.dtsi | 131 +
1 file changed, 131 insertions(+)
create mode 100644 arch/arm/dts/r8a77990.dtsi
diff --git a/arch/arm/dts/r8a77990.dtsi b/arch/arm/dts/r8a77990.dtsi
new file mode 100644
index 00..310bfd9d88
--- /dev/null
+++ b/arch/arm/dts/r8a77990.dtsi
@@ -0,0 +1,131 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Device Tree Source for the r8a77990 SoC
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+
+#include
+#include
+
+/ {
+ compatible = "renesas,r8a77990";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 1 core only at this point */
+ a53_0: cpu@0 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0>;
+ device_type = "cpu";
+ power-domains = < 5>;
+ next-level-cache = <_CA53>;
+ enable-method = "psci";
+ };
+
+ L2_CA53: cache-controller@0 {
+ compatible = "cache";
+ reg = <0>;
+ power-domains = < 21>;
+ cache-unified;
+ cache-level = <2>;
+ };
+ };
+
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ interrupt-parent = <>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gic: interrupt-controller@f101 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x0 0xf101 0 0x1000>,
+ <0x0 0xf102 0 0x2>,
+ <0x0 0xf104 0 0x2>,
+ <0x0 0xf106 0 0x2>;
+ interrupts = ;
+ clocks = < CPG_MOD 408>;
+ clock-names = "clk";
+ power-domains = < 32>;
+ resets = < 408>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = ,
+,
+,
+;
+ };
+
+ pmu_a53 {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = ;
+ interrupt-affinity = <_0>;
+ };
+
+ cpg: clock-controller@e615 {
+ compatible = "renesas,r8a77990-cpg-mssr";
+ reg = <0 0xe615 0 0x1000>;
+ clocks = <_clk>;
+ clock-names = "extal";
+ #clock-cells = <2>;
+ #power-domain-cells = <0>;
+ #reset-cells = <1>;
+ };
+
+ rst: reset-controller@e616 {
+ compatible = "renesas,r8a77990-rst";
+ reg = <0 0xe616 0 0x0200>;
+ };
+
+ prr: chipid@fff00044 {
+ compatible = "renesas,prr";
+ reg = <0 0xfff00044 0 4>;
+ };
+
+ sysc: system-controller@e618 {
+ compatible = "renesas,r8a77990-sysc";
+ reg = <0 0xe618 0 0x0400>;
+ #power-domain-cells = <1>;
+ };
+
+ scif2: serial@e6e88000 {
+ compatible = "renesas,scif-r8a77990",
+"renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6e88000 0 64>;
+ interrupts = ;
+ clocks = < CPG_MOD 310>;
+ clock-names = "fck";
+ power-domains = < 32>;
+ resets = <
Re: [U-Boot] [PULL] u-boot-socfpga/master
On 06/01/2018 09:30 AM, Ley Foon Tan wrote: > On Fri, Jun 1, 2018 at 2:31 PM, Marek Vasut wrote: >> On 06/01/2018 02:23 AM, Tom Rini wrote: >>> On Thu, May 31, 2018 at 08:06:50PM +0200, Marek Vasut wrote: >>> The following changes since commit c3c863880479edeb5b08226e622d13c91326e4a7: add FIT data-position & data-offset property support (2018-05-26 18:19:19 -0400) are available in the Git repository at: git://git.denx.de/u-boot-socfpga.git master for you to fetch changes up to a0029aea787286c72ca2411475f95519bf9a7f34: arm: socfpga: stratix10: Enable Stratix10 SoC build (2018-05-29 18:34:39 +0200) >>> >>> NAK. This adds warnings (which are errors in travis): >>> https://travis-ci.org/trini/u-boot/jobs/386306955#L866 >> >> Ley, can you send me a fix ? >> > Do you mean this one? > > +arch/arm/mach-socfpga/built-in.o: In function `do_bridge': > +arch/arm/mach-socfpga/misc.c:221: undefined reference to `do_bridge_reset' > +make[1]: *** [u-boot] Error 1 There's that and the cadence qspi error, yes. -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] arm: socfpga: Add do_bridge_reset for Arria 10
Add do_bridge_reset() function for Arria 10, it is required by misc.c.
arch/arm/mach-socfpga/built-in.o: In function `do_bridge':
arch/arm/mach-socfpga/misc.c:221: undefined reference to `do_bridge_reset'
make[1]: *** [u-boot] Error 1
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/misc_arria10.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/mach-socfpga/misc_arria10.c
b/arch/arm/mach-socfpga/misc_arria10.c
index 47a9d50..a75cbc4 100644
--- a/arch/arm/mach-socfpga/misc_arria10.c
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -14,6 +14,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -262,3 +263,11 @@ int arch_misc_init(void)
return socfpga_eth_reset();
}
#endif
+
+void do_bridge_reset(int enable)
+{
+ if (enable)
+ socfpga_reset_deassert_bridges_handoff();
+ else
+ socfpga_bridges_reset();
+}
--
2.2.2
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Re: [U-Boot] [PATCH] arm: socfpga: Add do_bridge_reset for Arria 10
On 06/01/2018 10:13 AM, Ley Foon Tan wrote:
> Add do_bridge_reset() function for Arria 10, it is required by misc.c.
>
> arch/arm/mach-socfpga/built-in.o: In function `do_bridge':
> arch/arm/mach-socfpga/misc.c:221: undefined reference to `do_bridge_reset'
> make[1]: *** [u-boot] Error 1
>
> Signed-off-by: Ley Foon Tan
> ---
> arch/arm/mach-socfpga/misc_arria10.c | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm/mach-socfpga/misc_arria10.c
> b/arch/arm/mach-socfpga/misc_arria10.c
> index 47a9d50..a75cbc4 100644
> --- a/arch/arm/mach-socfpga/misc_arria10.c
> +++ b/arch/arm/mach-socfpga/misc_arria10.c
> @@ -14,6 +14,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -262,3 +263,11 @@ int arch_misc_init(void)
> return socfpga_eth_reset();
> }
> #endif
> +
> +void do_bridge_reset(int enable)
> +{
> + if (enable)
> + socfpga_reset_deassert_bridges_handoff();
> + else
> + socfpga_bridges_reset();
> +}
>
http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=commit;h=8bed1b1dbaee66def9a8ded4f855e3d1f258d183
is probably better, since it uses the same command line API to operate
bridges as Gen5. Can you please rebase that one and submit it instead ?
--
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] spi: cadence_qspi: Fix warning cast from pointer to integer of different size
On 06/01/2018 10:52 AM, Ley Foon Tan wrote:
> Use "%p" to print cmdbuf.
>
> Compilation warning as below:
>
> CC spl/drivers/spi/cadence_qspi_apb.o
> LD spl/lib/built-in.o
> drivers/spi/cadence_qspi_apb.c: In function
> ‘cadence_qspi_apb_indirect_write_setup’:
> drivers/spi/cadence_qspi_apb.c:696:18: warning: cast from pointer to integer
> of different size [-Wpointer-to-int-cast]
> cmdlen, (unsigned int)cmdbuf);
>
> Signed-off-by: Ley Foon Tan
Acked-by: Marek Vasut
> ---
> v2: Use "%p" instead of cast to ulong data type.
> ---
> drivers/spi/cadence_qspi_apb.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
> index aa3a9ff..a8af352 100644
> --- a/drivers/spi/cadence_qspi_apb.c
> +++ b/drivers/spi/cadence_qspi_apb.c
> @@ -692,8 +692,8 @@ int cadence_qspi_apb_indirect_write_setup(struct
> cadence_spi_platdata *plat,
> unsigned int addr_bytes = cmdlen > 4 ? 4 : 3;
>
> if (cmdlen < 4 || cmdbuf == NULL) {
> - printf("QSPI: iInvalid input argument, len %d cmdbuf 0x%08x\n",
> -cmdlen, (unsigned int)cmdbuf);
> + printf("QSPI: Invalid input argument, len %d cmdbuf %p\n",
> +cmdlen, cmdbuf);
> return -EINVAL;
> }
> /* Setup the indirect trigger address */
>
--
Best regards,
Marek Vasut
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Re: [U-Boot] inappropriate PCI configuration on arm64 qemu?
On 06/01/2018 10:21 AM, AKASHI Takahiro wrote:
Tuomas,
On Thu, May 31, 2018 at 01:32:20PM +0300, Tuomas Tynkkynen wrote:
Hi Akashi,
On 05/31/2018 08:05 AM, AKASHI Takahiro wrote:
Simon,
On Wed, May 30, 2018 at 01:18:30PM -0600, Simon Glass wrote:
+Tuomas
Hi Akashi,
On 28 May 2018 at 01:59, AKASHI Takahiro wrote:
When I tried to add a SD card to qemu's virt machine (2.10.0) as,
--
-device sdhci-pci \
-device sd-card,drive=my_sd \
-drive if=none,id=my_sd,format=raw,file=/path/my/sd.img
--
u-boot doesn't configure a SDHCI controller properly and an attached
device is never detected.
Digging into the code, I found
* reading BAR5 in dm_pciauto_setup_device() shows BAR5 is a 32-bit address,
* pciauto_region_allocate() allocates a 64-bit address (0x80.ABCD.)
to BAR5 as res->bus_lower is 0x80..
* Upper 32-bit value is not written back to BAR5 because of !found_mem64
(BAR5 is the last one and no succeeding BAR anyway.)
On the other hand,
* Qemu defines two PCI memory regions for MMIO:
(from qemu's hw/arm/virt.c)
--
[VIRT_PCIE_MMIO] = { 0x1000, 0x2eff },
[VIRT_PCIE_PIO] = { 0x3eff, 0x0001 },
[VIRT_PCIE_ECAM] = { 0x3f00, 0x0100 },
[VIRT_MEM] ={ 0x4000, RAMLIMIT_BYTES },
/* Second PCIe window, 512GB wide at the 512GB boundary */
[VIRT_PCIE_MMIO_HIGH] = { 0x80ULL, 0x80ULL },
--
* A PCI card is configured in decode_regions() so that
'hose' has only one entry per each type of memory regions.
This behavior was introduced by Simon's patch:
--
commit 9526d83ac5a
Author: Simon Glass
Date: Thu Nov 19 20:26:58 2015 -0700
dm: pci: Support decoding ranges with duplicate entries
--
* As a result, MMIO region (0x1000.-0x2eff.) is overwritten
and MMIO_HIGH is the only one available at runtime.
I believe that this behavior is the root cause of my issue, and
by reverting the patch mentioned above, everything works fine.
While I understand a concern mentioned in the commit message,
there should be a better way to manage the case.
There was a series that changed things in this area. Can you take a look?
PCI: dm: Ignore 64-bit memory regions if CONFIG_SYS_PCI_64BIT not set
Ah, I didn't know that, but it seems to me that it is still insufficient.
This hack won't work on 32-bit PCI card. I found another patch from Tuomas:
Did you try it? As of today's master all of the patches are applied and at
least the e1000 NIC and the Intel AHCI card that I tested works.
The effect of the commit is to indeed avoid the problem you mentioned:
Yes, I ran my patch but *with* CONFIG_SYS_PCI_64BIT.
I meant: Did you try your QEMU command that enables the SDHCI on U-Boot
master, without any patches? It should just work.
* As a result, MMIO region (0x1000.-0x2eff.) is overwritten
and MMIO_HIGH is the only one available at runtime.
Note that even on aarch64, CONFIG_SYS_PCI_64BIT is *not* set by default.
And on ARM we would need to skip that region in U-Boot anyway because
we don't have the means to access physical addresses above the 4GB
boundary with the CPU using U-Boot's identity-mapped page tables.
Maybe you're right regarding aarch64, but the issue is not about arm/arm64
but PCI configuration. Some arch/machines, freescale mostly?, have
already enabled CONFIG_SYS_PCI_64BIT. I'm afraid that there may be
a possibility that your patch breaks them.
Which patch?
The "PCI: dm: Ignore 64-bit memory regions if CONFIG_SYS_PCI_64BIT not set"
commit adds:
+ if (!IS_ENABLED(CONFIG_SYS_PCI_64BIT) &&
+ type == PCI_REGION_MEM && upper_32_bits(pci_addr)) {
+ debug(" - beyond the 32-bit boundary, ignoring\n");
+ continue;
+ }
I.e. the patch is a no-op if CONFIG_SYS_PCI_64BIT is set. Also I don't
think PowerPC uses DM PCI, so that code is not executed at all on those
platforms.
If you mean in "PCI: autoconfig: Don't allocate 64-bit addresses to 32-bit only
resources" that someone could have been relying on the truncation of high
32 bits of bus addresses with 32-bit only devices, none of the FSL platforms
have bus addresses above 32-bits, only physical addresses (seen with
git grep CONFIG_SYS_PCIE._MEM_), so that shouldn't cause a problem either.
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Re: [U-Boot] [PULL] u-boot-socfpga/master
On Fri, Jun 1, 2018 at 2:31 PM, Marek Vasut wrote: > On 06/01/2018 02:23 AM, Tom Rini wrote: >> On Thu, May 31, 2018 at 08:06:50PM +0200, Marek Vasut wrote: >> >>> The following changes since commit c3c863880479edeb5b08226e622d13c91326e4a7: >>> >>> add FIT data-position & data-offset property support (2018-05-26 >>> 18:19:19 -0400) >>> >>> are available in the Git repository at: >>> >>> git://git.denx.de/u-boot-socfpga.git master >>> >>> for you to fetch changes up to a0029aea787286c72ca2411475f95519bf9a7f34: >>> >>> arm: socfpga: stratix10: Enable Stratix10 SoC build (2018-05-29 >>> 18:34:39 +0200) >>> >> >> NAK. This adds warnings (which are errors in travis): >> https://travis-ci.org/trini/u-boot/jobs/386306955#L866 > > Ley, can you send me a fix ? > Do you mean this one? +arch/arm/mach-socfpga/built-in.o: In function `do_bridge': +arch/arm/mach-socfpga/misc.c:221: undefined reference to `do_bridge_reset' +make[1]: *** [u-boot] Error 1 Regards Ley Foon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [RFC 3/3] efi_selftest: test writing to file
On 06/01/2018 09:13 AM, AKASHI, Takahiro wrote:
> Heinrich,
>
> On Sat, May 26, 2018 at 10:34:47AM +0200, Heinrich Schuchardt wrote:
>> Signed-off-by: Heinrich Schuchardt
>> ---
>> lib/efi_selftest/efi_selftest_block_device.c | 56
>> 1 file changed, 56 insertions(+)
>>
>> diff --git a/lib/efi_selftest/efi_selftest_block_device.c
>> b/lib/efi_selftest/efi_selftest_block_device.c
>> index 4af8bd8cb28..9209ce678ee 100644
>> --- a/lib/efi_selftest/efi_selftest_block_device.c
>> +++ b/lib/efi_selftest/efi_selftest_block_device.c
>> @@ -377,6 +377,7 @@ static int execute(void)
>> "Wrong volume label '%ps', expected 'U-BOOT TEST'\n",
>> system_info.info.volume_label);
>> }
>> +/* Read file */
>> ret = root->open(root, , (s16 *)L"hello.txt", EFI_FILE_MODE_READ,
>> 0);
>> if (ret != EFI_SUCCESS) {
>> @@ -389,6 +390,11 @@ static int execute(void)
>> efi_st_error("Failed to read file\n");
>> return EFI_ST_FAILURE;
>> }
>> +if (buf_size != 13) {
>> +efi_st_error("Wrong number of bytes read: %u\n",
>> + (unsigned int)buf_size);
>> +return EFI_ST_FAILURE;
>> +}
>> if (efi_st_memcmp(buf, "Hello world!", 12)) {
>> efi_st_error("Unexpected file content\n");
>> return EFI_ST_FAILURE;
>> @@ -399,6 +405,56 @@ static int execute(void)
>> return EFI_ST_FAILURE;
>> }
>> ret = root->close(root);
>
Your observation is correct. This is why I already sent a revised
version of the patch series. I unfortunately missed to put you on copy.
You can find the current patch here:
[PATCH v2 3/3] efi_selftest: test writing to file
https://patchwork.ozlabs.org/patch/921166/
https://lists.denx.de/pipermail/u-boot/2018-May/329730.html
Best regards
Heinrich
> We should not close 'root' here as
>> +/* Write file */
>> +ret = root->open(root, , (s16 *)L"u-boot.txt",
>> + EFI_FILE_MODE_WRITE | EFI_FILE_MODE_CREATE, 0);
>
> we will use it here.
>
>> +if (ret != EFI_SUCCESS) {
>> +efi_st_error("Failed to open file\n");
>> +return EFI_ST_FAILURE;
>> +}
>> +buf_size = 7;
>> +boottime->set_mem(buf, sizeof(buf), 0);
>> +boottime->copy_mem(buf, "U-Boot", buf_size);
>> +ret = file->write(file, _size, buf);
>> +if (ret != EFI_SUCCESS || buf_size != 7) {
>> +efi_st_error("Failed to write file\n");
>> +return EFI_ST_FAILURE;
>> +}
>> +ret = file->close(file);
>> +if (ret != EFI_SUCCESS) {
>> +efi_st_error("Failed to close file\n");
>> +return EFI_ST_FAILURE;
>> +}
>> +ret = root->close(root);
>
> ditto
>
> Thanks,
> -Takahiro AKASHI
>
>> +/* Verify file */
>> +boottime->set_mem(buf, sizeof(buf), 0);
>> +ret = root->open(root, , (s16 *)L"u-boot.txt", EFI_FILE_MODE_READ,
>> + 0);
>> +if (ret != EFI_SUCCESS) {
>> +efi_st_error("Failed to open file\n");
>> +return EFI_ST_FAILURE;
>> +}
>> +buf_size = sizeof(buf) - 1;
>> +ret = file->read(file, _size, buf);
>> +if (ret != EFI_SUCCESS) {
>> +efi_st_error("Failed to read file\n");
>> +return EFI_ST_FAILURE;
>> +}
>> +if (buf_size != 7) {
>> +efi_st_error("Wrong number of bytes read: %u\n",
>> + (unsigned int) buf_size);
>> +return EFI_ST_FAILURE;
>> +}
>> +if (efi_st_memcmp(buf, "U-Boot", 7)) {
>> +efi_st_error("Unexpected file content %s\n", buf);
>> +return EFI_ST_FAILURE;
>> +}
>> +ret = file->close(file);
>> +if (ret != EFI_SUCCESS) {
>> +efi_st_error("Failed to close file\n");
>> +return EFI_ST_FAILURE;
>> +}
>> +ret = root->close(root);
>> if (ret != EFI_SUCCESS) {
>> efi_st_error("Failed to close volume\n");
>> return EFI_ST_FAILURE;
>> --
>> 2.17.0
>>
>
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[U-Boot] [PATCH 8/8] ARM: rmobile: Represent SF partitioning with mtdparts on Stout
Add mtdparts description for the board. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- configs/stout_defconfig | 5 + 1 file changed, 5 insertions(+) diff --git a/configs/stout_defconfig b/configs/stout_defconfig index d940932baf..1a9e6ce366 100644 --- a/configs/stout_defconfig +++ b/configs/stout_defconfig @@ -46,6 +46,9 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nor0=spi0.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k(u-boot-env2),768k(u-boot),-(user)" CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_SPI_FLASH=y @@ -57,9 +60,11 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_RCAR_IIC=y CONFIG_DM_MMC=y CONFIG_RENESAS_SDHI=y +CONFIG_MTD=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_MICREL=y CONFIG_DM_ETH=y CONFIG_SH_ETHER=y -- 2.16.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 3/8] ARM: rmobile: Represent SF partitioning with mtdparts on Gose
Add mtdparts description for the board. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- configs/gose_defconfig | 5 + 1 file changed, 5 insertions(+) diff --git a/configs/gose_defconfig b/configs/gose_defconfig index 8479887604..4b8c5a4aea 100644 --- a/configs/gose_defconfig +++ b/configs/gose_defconfig @@ -46,6 +46,9 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nor0=spi0.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k(u-boot-env2),768k(u-boot),-(user)" CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_SPI_FLASH=y @@ -57,9 +60,11 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_RCAR_IIC=y CONFIG_DM_MMC=y CONFIG_RENESAS_SDHI=y +CONFIG_MTD=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_MICREL=y CONFIG_DM_ETH=y CONFIG_SH_ETHER=y -- 2.16.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 5/8] ARM: rmobile: Represent SF partitioning with mtdparts on Lager
Add mtdparts description for the board. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- configs/lager_defconfig | 5 + 1 file changed, 5 insertions(+) diff --git a/configs/lager_defconfig b/configs/lager_defconfig index 70083bcbfe..0eaf33d7f8 100644 --- a/configs/lager_defconfig +++ b/configs/lager_defconfig @@ -46,6 +46,9 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nor0=spi0.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k(u-boot-env2),768k(u-boot),-(user)" CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_SPI_FLASH=y @@ -59,9 +62,11 @@ CONFIG_SYS_I2C_RCAR_IIC=y CONFIG_DM_MMC=y CONFIG_SH_MMCIF=y CONFIG_RENESAS_SDHI=y +CONFIG_MTD=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_MICREL=y CONFIG_DM_ETH=y CONFIG_SH_ETHER=y -- 2.16.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 4/8] ARM: rmobile: Represent SF partitioning with mtdparts on Koelsch
Add mtdparts description for the board. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- configs/koelsch_defconfig | 5 + 1 file changed, 5 insertions(+) diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig index faca596115..39d5805f94 100644 --- a/configs/koelsch_defconfig +++ b/configs/koelsch_defconfig @@ -46,6 +46,9 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nor0=spi0.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k(u-boot-env2),768k(u-boot),-(user)" CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_SPI_FLASH=y @@ -57,9 +60,11 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_RCAR_IIC=y CONFIG_DM_MMC=y CONFIG_RENESAS_SDHI=y +CONFIG_MTD=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_MICREL=y CONFIG_DM_ETH=y CONFIG_SH_ETHER=y -- 2.16.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 7/8] ARM: rmobile: Represent SF partitioning with mtdparts on Silk
Add mtdparts description for the board. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- configs/silk_defconfig | 5 + 1 file changed, 5 insertions(+) diff --git a/configs/silk_defconfig b/configs/silk_defconfig index a1c4e5cde3..9a9301e7e0 100644 --- a/configs/silk_defconfig +++ b/configs/silk_defconfig @@ -46,6 +46,9 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nor0=spi0.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k(u-boot-env2),768k(u-boot),-(user)" CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_SPI_FLASH=y @@ -59,9 +62,11 @@ CONFIG_SYS_I2C_RCAR_IIC=y CONFIG_DM_MMC=y CONFIG_SH_MMCIF=y CONFIG_RENESAS_SDHI=y +CONFIG_MTD=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_MICREL=y CONFIG_DM_ETH=y CONFIG_SH_ETHER=y -- 2.16.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 05/15] clk: renesas: Add R8A77990 E3 clock tables
Add clock tables for R8A77990 E3 SoC .
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
drivers/clk/renesas/Kconfig | 7 +
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/r8a77990-cpg-mssr.c | 303 ++
include/dt-bindings/clock/r8a77990-cpg-mssr.h | 63 ++
4 files changed, 374 insertions(+)
create mode 100644 drivers/clk/renesas/r8a77990-cpg-mssr.c
create mode 100644 include/dt-bindings/clock/r8a77990-cpg-mssr.h
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index b5a6bcc3af..578e6a8049 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -74,6 +74,13 @@ config CLK_R8A77970
help
Enable this to support the clocks on Renesas R8A77970 SoC.
+config CLK_R8A77990
+ bool "Renesas R8A77990 clock driver"
+ def_bool y if R8A77990
+ depends on CLK_RCAR_GEN3
+ help
+ Enable this to support the clocks on Renesas R8A77990 SoC.
+
config CLK_R8A77995
bool "Renesas R8A77995 clock driver"
def_bool y if R8A77995
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index a65d89f59c..22a817a919 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -9,4 +9,5 @@ obj-$(CONFIG_CLK_RCAR_GEN3) += clk-rcar-gen3.o
obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c
b/drivers/clk/renesas/r8a77990-cpg-mssr.c
new file mode 100644
index 00..792d6101b8
--- /dev/null
+++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
@@ -0,0 +1,303 @@
+/*
+ * Renesas R8A77990 CPG MSSR driver
+ *
+ * Copyright (C) 2017-2018 Marek Vasut
+ *
+ * Based on the following driver from Linux kernel:
+ * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2016 Glider bvba
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+
+#include
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen3-cpg.h"
+
+enum clk_ids {
+ /* Core Clock Outputs exported to DT */
+ LAST_DT_CORE_CLK = R8A77990_CLK_CPEX,
+
+ /* External Input Clocks */
+ CLK_EXTAL,
+
+ /* Internal Core Clocks */
+ CLK_MAIN,
+ CLK_PLL0,
+ CLK_PLL1,
+ CLK_PLL3,
+ CLK_PLL0D4,
+ CLK_PLL0D6,
+ CLK_PLL0D8,
+ CLK_PLL0D20,
+ CLK_PLL0D24,
+ CLK_PLL1D2,
+ CLK_PE,
+ CLK_S0,
+ CLK_S1,
+ CLK_S2,
+ CLK_S3,
+ CLK_SDSRC,
+
+ /* Module Clocks */
+ MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a77990_core_clks[] = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+
+ /* Internal Core Clocks */
+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
+ DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
+
+ DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 1, 100),
+ DEF_FIXED(".pll0d4", CLK_PLL0D4, CLK_PLL0, 4, 1),
+ DEF_FIXED(".pll0d6", CLK_PLL0D6, CLK_PLL0, 6, 1),
+ DEF_FIXED(".pll0d8", CLK_PLL0D8, CLK_PLL0, 8, 1),
+ DEF_FIXED(".pll0d20", CLK_PLL0D20,CLK_PLL0, 20, 1),
+ DEF_FIXED(".pll0d24", CLK_PLL0D24,CLK_PLL0, 24, 1),
+ DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1),
+ DEF_FIXED(".pe", CLK_PE, CLK_PLL0D20,1, 1),
+ DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1),
+ DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1),
+ DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
+ DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
+ DEF_FIXED(".sdsrc",CLK_SDSRC, CLK_PLL1, 2, 1),
+
+ /* Core Clock Outputs */
+ DEF_FIXED("za2", R8A77990_CLK_ZA2, CLK_PLL0D24,1, 1),
+ DEF_FIXED("za8", R8A77990_CLK_ZA8, CLK_PLL0D8, 1, 1),
+ DEF_FIXED("ztr", R8A77990_CLK_ZTR, CLK_PLL1, 6, 1),
+ DEF_FIXED("zt",R8A77990_CLK_ZT,CLK_PLL1, 4, 1),
+ DEF_FIXED("zx",R8A77990_CLK_ZX,CLK_PLL1, 3, 1),
+ DEF_FIXED("s0d1", R8A77990_CLK_S0D1, CLK_S0, 1, 1),
+ DEF_FIXED("s0d3", R8A77990_CLK_S0D3, CLK_S0, 3, 1),
+ DEF_FIXED("s0d6", R8A77990_CLK_S0D6, CLK_S0, 6, 1),
+ DEF_FIXED("s0d12", R8A77990_CLK_S0D12, CLK_S0,12, 1),
+ DEF_FIXED("s0d24", R8A77990_CLK_S0D24, CLK_S0,24, 1),
+ DEF_FIXED("s1d1",
[U-Boot] [PATCH 11/15] ARM: renesas: Add R8A77990 E3 SoC ID
Add ID and Kconfig entry for the Renesas R8A77990 E3 SoC.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
arch/arm/mach-rmobile/Kconfig.64 | 3 +++
arch/arm/mach-rmobile/cpu_info.c | 1 +
arch/arm/mach-rmobile/include/mach/rmobile.h | 1 +
3 files changed, 5 insertions(+)
diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64
index 6112d79f0d..6b93d25358 100644
--- a/arch/arm/mach-rmobile/Kconfig.64
+++ b/arch/arm/mach-rmobile/Kconfig.64
@@ -12,6 +12,9 @@ config R8A7796
config R8A77970
bool "Renesas SoC R8A77970"
+config R8A77990
+ bool "Renesas SoC R8A77990"
+
config R8A77995
bool "Renesas SoC R8A77995"
diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c
index 4e6a191cb1..e110737471 100644
--- a/arch/arm/mach-rmobile/cpu_info.c
+++ b/arch/arm/mach-rmobile/cpu_info.c
@@ -59,6 +59,7 @@ static const struct {
{ RMOBILE_CPU_TYPE_R8A7796, "R8A7796" },
{ RMOBILE_CPU_TYPE_R8A77965, "R8A77965" },
{ RMOBILE_CPU_TYPE_R8A77970, "R8A77970" },
+ { RMOBILE_CPU_TYPE_R8A77990, "R8A77990" },
{ RMOBILE_CPU_TYPE_R8A77995, "R8A77995" },
{ 0x0, "CPU" },
};
diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h
b/arch/arm/mach-rmobile/include/mach/rmobile.h
index 94ea366f45..c94b3ff509 100644
--- a/arch/arm/mach-rmobile/include/mach/rmobile.h
+++ b/arch/arm/mach-rmobile/include/mach/rmobile.h
@@ -35,6 +35,7 @@
#define RMOBILE_CPU_TYPE_R8A7796 0x52
#define RMOBILE_CPU_TYPE_R8A77965 0x55
#define RMOBILE_CPU_TYPE_R8A77970 0x54
+#define RMOBILE_CPU_TYPE_R8A77990 0x57
#define RMOBILE_CPU_TYPE_R8A77995 0x58
#ifndef __ASSEMBLY__
--
2.16.2
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[U-Boot] [PATCH 02/15] clk: renesas: Pass clock rate around as 64bit number internally
The PLL rate could be in the GHz range, which could overflow a 32bit
data type. Since the hardware is 64bit anyway, pass the clock rates
as 64bit number internally to avoid this.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
drivers/clk/renesas/clk-rcar-gen3.c | 56 -
1 file changed, 31 insertions(+), 25 deletions(-)
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c
b/drivers/clk/renesas/clk-rcar-gen3.c
index 4f10fd6352..834cd5ac58 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -134,7 +134,7 @@ static int gen3_clk_disable(struct clk *clk)
return renesas_clk_endisable(clk, priv->base, false);
}
-static ulong gen3_clk_get_rate(struct clk *clk)
+static u64 gen3_clk_get_rate64(struct clk *clk)
{
struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
struct cpg_mssr_info *info = priv->info;
@@ -142,7 +142,8 @@ static ulong gen3_clk_get_rate(struct clk *clk)
const struct cpg_core_clk *core;
const struct rcar_gen3_cpg_pll_config *pll_config =
priv->cpg_pll_config;
- u32 value, mult, prediv, postdiv, rate = 0;
+ u32 value, mult, prediv, postdiv;
+ u64 rate = 0;
int i, ret;
debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id);
@@ -154,8 +155,8 @@ static ulong gen3_clk_get_rate(struct clk *clk)
}
if (renesas_clk_is_mod(clk)) {
- rate = gen3_clk_get_rate();
- debug("%s[%i] MOD clk: parent=%lu => rate=%u\n",
+ rate = gen3_clk_get_rate64();
+ debug("%s[%i] MOD clk: parent=%lu => rate=%llu\n",
__func__, __LINE__, parent.id, rate);
return rate;
}
@@ -168,14 +169,14 @@ static ulong gen3_clk_get_rate(struct clk *clk)
case CLK_TYPE_IN:
if (core->id == info->clk_extal_id) {
rate = clk_get_rate(>clk_extal);
- debug("%s[%i] EXTAL clk: rate=%u\n",
+ debug("%s[%i] EXTAL clk: rate=%llu\n",
__func__, __LINE__, rate);
return rate;
}
if (core->id == info->clk_extalr_id) {
rate = clk_get_rate(>clk_extalr);
- debug("%s[%i] EXTALR clk: rate=%u\n",
+ debug("%s[%i] EXTALR clk: rate=%llu\n",
__func__, __LINE__, rate);
return rate;
}
@@ -183,8 +184,8 @@ static ulong gen3_clk_get_rate(struct clk *clk)
return -EINVAL;
case CLK_TYPE_GEN3_MAIN:
- rate = gen3_clk_get_rate() / pll_config->extal_div;
- debug("%s[%i] MAIN clk: parent=%i extal_div=%i => rate=%u\n",
+ rate = gen3_clk_get_rate64() / pll_config->extal_div;
+ debug("%s[%i] MAIN clk: parent=%i extal_div=%i => rate=%llu\n",
__func__, __LINE__,
core->parent, pll_config->extal_div, rate);
return rate;
@@ -192,14 +193,14 @@ static ulong gen3_clk_get_rate(struct clk *clk)
case CLK_TYPE_GEN3_PLL0:
value = readl(priv->base + CPG_PLL0CR);
mult = (((value >> 24) & 0x7f) + 1) * 2;
- rate = gen3_clk_get_rate() * mult;
- debug("%s[%i] PLL0 clk: parent=%i mult=%u => rate=%u\n",
+ rate = gen3_clk_get_rate64() * mult;
+ debug("%s[%i] PLL0 clk: parent=%i mult=%u => rate=%llu\n",
__func__, __LINE__, core->parent, mult, rate);
return rate;
case CLK_TYPE_GEN3_PLL1:
- rate = gen3_clk_get_rate() * pll_config->pll1_mult;
- debug("%s[%i] PLL1 clk: parent=%i mul=%i => rate=%u\n",
+ rate = gen3_clk_get_rate64() * pll_config->pll1_mult;
+ debug("%s[%i] PLL1 clk: parent=%i mul=%i => rate=%llu\n",
__func__, __LINE__,
core->parent, pll_config->pll1_mult, rate);
return rate;
@@ -207,14 +208,14 @@ static ulong gen3_clk_get_rate(struct clk *clk)
case CLK_TYPE_GEN3_PLL2:
value = readl(priv->base + CPG_PLL2CR);
mult = (((value >> 24) & 0x7f) + 1) * 2;
- rate = gen3_clk_get_rate() * mult;
- debug("%s[%i] PLL2 clk: parent=%i mult=%u => rate=%u\n",
+ rate = gen3_clk_get_rate64() * mult;
+ debug("%s[%i] PLL2 clk: parent=%i mult=%u => rate=%llu\n",
__func__, __LINE__, core->parent, mult, rate);
return rate;
case CLK_TYPE_GEN3_PLL3:
- rate = gen3_clk_get_rate() * pll_config->pll3_mult;
- debug("%s[%i] PLL3 clk: parent=%i mul=%i => rate=%u\n",
+ rate = gen3_clk_get_rate64() * pll_config->pll3_mult;
+
Re: [U-Boot] [PULL] u-boot-socfpga/master
On Fri, Jun 1, 2018 at 3:49 PM, Marek Vasut wrote: > On 06/01/2018 09:30 AM, Ley Foon Tan wrote: >> On Fri, Jun 1, 2018 at 2:31 PM, Marek Vasut wrote: >>> On 06/01/2018 02:23 AM, Tom Rini wrote: On Thu, May 31, 2018 at 08:06:50PM +0200, Marek Vasut wrote: > The following changes since commit > c3c863880479edeb5b08226e622d13c91326e4a7: > > add FIT data-position & data-offset property support (2018-05-26 > 18:19:19 -0400) > > are available in the Git repository at: > > git://git.denx.de/u-boot-socfpga.git master > > for you to fetch changes up to a0029aea787286c72ca2411475f95519bf9a7f34: > > arm: socfpga: stratix10: Enable Stratix10 SoC build (2018-05-29 > 18:34:39 +0200) > NAK. This adds warnings (which are errors in travis): https://travis-ci.org/trini/u-boot/jobs/386306955#L866 >>> >>> Ley, can you send me a fix ? >>> >> Do you mean this one? >> >> +arch/arm/mach-socfpga/built-in.o: In function `do_bridge': >> +arch/arm/mach-socfpga/misc.c:221: undefined reference to `do_bridge_reset' >> +make[1]: *** [u-boot] Error 1 > > There's that and the cadence qspi error, yes. > Okay, I will send in patch for do_bridge. For QSPI warning, here are the patches, can you merge them too? https://patchwork.ozlabs.org/patch/909628/ https://patchwork.ozlabs.org/patch/909629/ https://patchwork.ozlabs.org/patch/909630/ Regards Ley Foon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 0/4] drivers: Add reset ctrl to drivers
Add reset ctrl to dwmmc socfpga, designware Ethernet and ns16550 serial drivers. A reset property is an optional feature, so only print out a warning and do not fail if a reset property is not present. If a reset property is discovered, then use it to deassert, thus bringing the IP out of reset. v4 change: - Add patch to check CONFIG_SPL_RESET_SUPPORT in reset.h History: v1: https://patchwork.ozlabs.org/cover/905519/ v2: https://patchwork.ozlabs.org/cover/908667/ v3: https://patchwork.ozlabs.org/cover/910018/ Ley Foon Tan (4): include: reset: check CONFIG_SPL_RESET_SUPPORT mmc: dwmmc: socfpga: Add reset ctrl to driver serial: ns16550: Add reset ctrl to driver net: designware: Add reset ctrl to driver drivers/mmc/socfpga_dw_mmc.c | 17 + drivers/net/designware.c | 8 drivers/serial/ns16550.c | 8 include/reset.h | 3 ++- 4 files changed, 35 insertions(+), 1 deletion(-) -- 2.2.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] spi: cadence_qspi: Fix warning cast from pointer to integer of different size
On 05/07/2018 11:42 AM, Ley Foon Tan wrote:
> Cast to ulong data type.
>
> Compilation warning as below:
>
> CC spl/drivers/spi/cadence_qspi_apb.o
> LD spl/lib/built-in.o
> drivers/spi/cadence_qspi_apb.c: In function
> ‘cadence_qspi_apb_indirect_write_setup’:
> drivers/spi/cadence_qspi_apb.c:696:18: warning: cast from pointer to integer
> of different size [-Wpointer-to-int-cast]
> cmdlen, (unsigned int)cmdbuf);
>
> Signed-off-by: Ley Foon Tan
> ---
> drivers/spi/cadence_qspi_apb.c |4 ++--
> 1 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
> index aa3a9ff..5bef0ae 100644
> --- a/drivers/spi/cadence_qspi_apb.c
> +++ b/drivers/spi/cadence_qspi_apb.c
> @@ -692,8 +692,8 @@ int cadence_qspi_apb_indirect_write_setup(struct
> cadence_spi_platdata *plat,
> unsigned int addr_bytes = cmdlen > 4 ? 4 : 3;
>
> if (cmdlen < 4 || cmdbuf == NULL) {
> - printf("QSPI: iInvalid input argument, len %d cmdbuf 0x%08x\n",
> -cmdlen, (unsigned int)cmdbuf);
> + printf("QSPI: Invalid input argument, len %d cmdbuf 0x%08lx\n",
> +cmdlen, (unsigned long)cmdbuf);
%p ?
> return -EINVAL;
> }
> /* Setup the indirect trigger address */
>
--
Best regards,
Marek Vasut
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Re: [U-Boot] [PULL] u-boot-socfpga/master
On 06/01/2018 10:03 AM, Ley Foon Tan wrote: > On Fri, Jun 1, 2018 at 3:49 PM, Marek Vasut wrote: >> On 06/01/2018 09:30 AM, Ley Foon Tan wrote: >>> On Fri, Jun 1, 2018 at 2:31 PM, Marek Vasut wrote: On 06/01/2018 02:23 AM, Tom Rini wrote: > On Thu, May 31, 2018 at 08:06:50PM +0200, Marek Vasut wrote: > >> The following changes since commit >> c3c863880479edeb5b08226e622d13c91326e4a7: >> >> add FIT data-position & data-offset property support (2018-05-26 >> 18:19:19 -0400) >> >> are available in the Git repository at: >> >> git://git.denx.de/u-boot-socfpga.git master >> >> for you to fetch changes up to a0029aea787286c72ca2411475f95519bf9a7f34: >> >> arm: socfpga: stratix10: Enable Stratix10 SoC build (2018-05-29 >> 18:34:39 +0200) >> > > NAK. This adds warnings (which are errors in travis): > https://travis-ci.org/trini/u-boot/jobs/386306955#L866 Ley, can you send me a fix ? >>> Do you mean this one? >>> >>> +arch/arm/mach-socfpga/built-in.o: In function `do_bridge': >>> +arch/arm/mach-socfpga/misc.c:221: undefined reference to `do_bridge_reset' >>> +make[1]: *** [u-boot] Error 1 >> >> There's that and the cadence qspi error, yes. >> > Okay, I will send in patch for do_bridge. For QSPI warning, here are > the patches, can you merge them too? > > https://patchwork.ozlabs.org/patch/909628/ > https://patchwork.ozlabs.org/patch/909629/ > https://patchwork.ozlabs.org/patch/909630/ I have some comments on those, so bridge patch is enough. The CQSPI patches should go through u-boot-spi anyway. -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] spi: cadence_qspi: Change to use devfdt_get_addr_index()
On 05/07/2018 11:42 AM, Ley Foon Tan wrote:
> Change to use devfdt_get_addr_index() function to get fdt address.
>
> Original code has compilation warning below:
>
> drivers/spi/cadence_qspi.c: In function ‘cadence_spi_ofdata_to_platdata’:
> drivers/spi/cadence_qspi.c:297:18: warning: cast to pointer from integer of
> different size [-Wint-to-pointer-cast]
> plat->regbase = (void *)data[0];
> ^
> drivers/spi/cadence_qspi.c:298:18: warning: cast to pointer from integer of
> different size [-Wint-to-pointer-cast]
> plat->ahbbase = (void *)data[2];
> ^
> Signed-off-by: Ley Foon Tan
Acked-by: Marek Vasut
> ---
> drivers/spi/cadence_qspi.c | 13 ++---
> 1 files changed, 2 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
> index 7b312f8..f80d073 100644
> --- a/drivers/spi/cadence_qspi.c
> +++ b/drivers/spi/cadence_qspi.c
> @@ -284,18 +284,9 @@ static int cadence_spi_ofdata_to_platdata(struct udevice
> *bus)
> const void *blob = gd->fdt_blob;
> int node = dev_of_offset(bus);
> int subnode;
> - u32 data[4];
> - int ret;
>
> - /* 2 base addresses are needed, lets get them from the DT */
> - ret = fdtdec_get_int_array(blob, node, "reg", data, ARRAY_SIZE(data));
> - if (ret) {
> - printf("Error: Can't get base addresses (ret=%d)!\n", ret);
> - return -ENODEV;
> - }
> -
> - plat->regbase = (void *)data[0];
> - plat->ahbbase = (void *)data[2];
> + plat->regbase = (void *)devfdt_get_addr_index(bus, 0);
> + plat->ahbbase = (void *)devfdt_get_addr_index(bus, 1);
> plat->is_decoded_cs = fdtdec_get_bool(blob, node, "cdns,is-decoded-cs");
> plat->fifo_depth = fdtdec_get_uint(blob, node, "cdns,fifo-depth", 128);
> plat->fifo_width = fdtdec_get_uint(blob, node, "cdns,fifo-width", 4);
>
--
Best regards,
Marek Vasut
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[U-Boot] [PATCH v4 3/4] serial: ns16550: Add reset ctrl to driver
Add code to reset all reset signals as in serial DT node. A reset property is
an optional feature,
so do not fail if a reset property is not present.
If a reset property is discovered, then use it to deassert, thus bringing the
IP out of reset.
Signed-off-by: Ley Foon Tan
Reviewed-by: Marek Vasut
---
drivers/serial/ns16550.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 53550bf..9c80090 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -177,6 +178,7 @@ void NS16550_init(NS16550_t com_port, int baud_divisor)
#if defined(CONFIG_ARCH_OMAP2PLUS)
serial_out(0x7, _port->mdr1); /* mode select reset TL16C750*/
#endif
+
serial_out(UART_MCRVAL, _port->mcr);
serial_out(ns16550_getfcr(com_port), _port->fcr);
if (baud_divisor != -1)
@@ -370,6 +372,12 @@ static int ns16550_serial_setbrg(struct udevice *dev, int
baudrate)
int ns16550_serial_probe(struct udevice *dev)
{
struct NS16550 *const com_port = dev_get_priv(dev);
+ struct reset_ctl_bulk reset_bulk;
+ int ret;
+
+ ret = reset_get_bulk(dev, _bulk);
+ if (!ret)
+ reset_deassert_bulk(_bulk);
com_port->plat = dev_get_platdata(dev);
NS16550_init(com_port, -1);
--
2.2.2
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[U-Boot] [PATCH v4 2/4] mmc: dwmmc: socfpga: Add reset ctrl to driver
Add code to reset all reset signals as in mmc DT node. A reset property is an
optional feature,
so only print out a warning and do not fail if a reset property is not present.
If a reset property is discovered, then use it to deassert, thus bringing the
IP out of reset.
Signed-off-by: Ley Foon Tan
---
drivers/mmc/socfpga_dw_mmc.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index d0a0362..4be4eb5 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -13,6 +13,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -33,6 +34,20 @@ struct dwmci_socfpga_priv_data {
unsigned intsmplsel;
};
+static void socfpga_dwmci_reset(struct udevice *dev)
+{
+ struct reset_ctl_bulk reset_bulk;
+ int ret;
+
+ ret = reset_get_bulk(dev, _bulk);
+ if (ret) {
+ dev_warn(dev, "Can't get reset: %d\n", ret);
+ return;
+ }
+
+ reset_deassert_bulk(_bulk);
+}
+
static void socfpga_dwmci_clksel(struct dwmci_host *host)
{
struct dwmci_socfpga_priv_data *priv = host->priv;
@@ -109,6 +124,8 @@ static int socfpga_dwmmc_probe(struct udevice *dev)
struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
struct dwmci_host *host = >host;
+ socfpga_dwmci_reset(dev);
+
#ifdef CONFIG_BLK
dwmci_setup_cfg(>cfg, host, host->bus_hz, 40);
host->mmc = >mmc;
--
2.2.2
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[U-Boot] [PATCH v4 1/4] include: reset: check CONFIG_SPL_RESET_SUPPORT
Add checking for CONFIG_SPL_RESET_SUPPORT to fix compilation error when
CONFIG_DM_RESET is enabled but CONFIG_SPL_RESET_SUPPORT is disabled in SPL
build.
Signed-off-by: Ley Foon Tan
---
include/reset.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/reset.h b/include/reset.h
index 201bafc..0ac0a47 100644
--- a/include/reset.h
+++ b/include/reset.h
@@ -77,7 +77,8 @@ struct reset_ctl_bulk {
unsigned int count;
};
-#ifdef CONFIG_DM_RESET
+#if (!defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM_RESET)) ||\
+(defined(CONFIG_SPL_RESET_SUPPORT) && defined(CONFIG_DM_RESET))
/**
* reset_get_by_index - Get/request a reset signal by integer index.
*
--
2.2.2
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[U-Boot] [PATCH v4 4/4] net: designware: Add reset ctrl to driver
Add code to reset all reset signals as in Ethernet DT node. A reset property is an optional feature, so only print out a warning and do not fail if a reset property is not present. If a reset property is discovered, then use it to deassert, thus bringing the IP out of reset. Signed-off-by: Ley Foon Tan --- drivers/net/designware.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/net/designware.c b/drivers/net/designware.c index cf12521..6797691 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -664,6 +665,7 @@ int designware_eth_probe(struct udevice *dev) u32 iobase = pdata->iobase; ulong ioaddr; int ret; + struct reset_ctl_bulk reset_bulk; #ifdef CONFIG_CLK int i, err, clock_nb; @@ -710,6 +712,12 @@ int designware_eth_probe(struct udevice *dev) } #endif + ret = reset_get_bulk(dev, _bulk); + if (ret) + dev_warn(dev, "Can't get reset: %d\n", ret); + else + reset_deassert_bulk(_bulk); + #ifdef CONFIG_DM_PCI /* * If we are on PCI bus, either directly attached to a PCI root port, -- 2.2.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] sunxi: allow CONFIG_DEFAULT_FDT_FILE override
On Fri, Jun 1, 2018 at 1:32 AM, Martin Kelly wrote: > On 05/31/2018 12:58 PM, klaus.go...@theobroma-systems.com wrote: >> [snip] >> >> >> I run into the same issue for the rockchip architecture[1]. After giving >> up on finding a >> rock-solid solution for detecting the emtpy string I decided to go with >> your option (b). >> Another solution would be to hide CONFIG_DEFAULT_DEVICE_TREE behind a >> Kconfig bool so it would not be defined until something like >> CONFIG_FDT_FILE is >> selected. But in favour of having U-Boot devicetree decoupled from any OS >> fdt I >> still prefer option (b). >> >> [1] https://patchwork.ozlabs.org/patch/920785/ >> >> > > Thanks, I'll go ahead with that solution and issue a follow-up patch. > > Jagan, should I make the patch against this one, or against master? on master ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] MIPS: add MIPS Release 6 build coverage for Boston boards
Now that Travis CI is building with gcc-7.3.0, we can add build coverage for all combinations of MIPS Release 6 instruction sets (MIPS32, MIPS64, Big Endian, Little Endian). Add mew default configs for Boston board for all MIPS Release 6 variants. Signed-off-by: Daniel Schwierzeck --- configs/boston32r6_defconfig | 41 + configs/boston32r6el_defconfig | 42 ++ configs/boston64r6_defconfig | 41 + configs/boston64r6el_defconfig | 42 ++ 4 files changed, 166 insertions(+) create mode 100644 configs/boston32r6_defconfig create mode 100644 configs/boston32r6el_defconfig create mode 100644 configs/boston64r6_defconfig create mode 100644 configs/boston64r6el_defconfig diff --git a/configs/boston32r6_defconfig b/configs/boston32r6_defconfig new file mode 100644 index 00..1cd5667ce5 --- /dev/null +++ b/configs/boston32r6_defconfig @@ -0,0 +1,41 @@ +CONFIG_MIPS=y +CONFIG_SYS_TEXT_BASE=0x9FC0 +CONFIG_TARGET_BOSTON=y +CONFIG_CPU_MIPS32_R6=y +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set +CONFIG_MIPS_BOOT_FDT=y +CONFIG_DEFAULT_DEVICE_TREE="img,boston" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_BEST_MATCH=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_PROMPT="boston # " +# CONFIG_CMD_ELF is not set +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_PCI=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_DNS=y +CONFIG_CMD_LINK_LOCAL=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set +CONFIG_OF_EMBED=y +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_CLK=y +CONFIG_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_CFI_FLASH=y +CONFIG_DM_ETH=y +CONFIG_PCH_GBE=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCI_XILINX=y +CONFIG_SYS_NS16550=y +CONFIG_LZ4=y diff --git a/configs/boston32r6el_defconfig b/configs/boston32r6el_defconfig new file mode 100644 index 00..c7f641c7d4 --- /dev/null +++ b/configs/boston32r6el_defconfig @@ -0,0 +1,42 @@ +CONFIG_MIPS=y +CONFIG_SYS_TEXT_BASE=0x9FC0 +CONFIG_TARGET_BOSTON=y +CONFIG_SYS_LITTLE_ENDIAN=y +CONFIG_CPU_MIPS32_R6=y +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set +CONFIG_MIPS_BOOT_FDT=y +CONFIG_DEFAULT_DEVICE_TREE="img,boston" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_BEST_MATCH=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_PROMPT="boston # " +# CONFIG_CMD_ELF is not set +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_PCI=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_DNS=y +CONFIG_CMD_LINK_LOCAL=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set +CONFIG_OF_EMBED=y +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_CLK=y +CONFIG_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_CFI_FLASH=y +CONFIG_DM_ETH=y +CONFIG_PCH_GBE=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCI_XILINX=y +CONFIG_SYS_NS16550=y +CONFIG_LZ4=y diff --git a/configs/boston64r6_defconfig b/configs/boston64r6_defconfig new file mode 100644 index 00..b4bb8a6d00 --- /dev/null +++ b/configs/boston64r6_defconfig @@ -0,0 +1,41 @@ +CONFIG_MIPS=y +CONFIG_SYS_TEXT_BASE=0x9FC0 +CONFIG_TARGET_BOSTON=y +CONFIG_CPU_MIPS64_R6=y +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set +CONFIG_MIPS_BOOT_FDT=y +CONFIG_DEFAULT_DEVICE_TREE="img,boston" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_BEST_MATCH=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_PROMPT="boston # " +# CONFIG_CMD_ELF is not set +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_PCI=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_DNS=y +CONFIG_CMD_LINK_LOCAL=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set +CONFIG_OF_EMBED=y +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_CLK=y +CONFIG_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_CFI_FLASH=y +CONFIG_DM_ETH=y +CONFIG_PCH_GBE=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCI_XILINX=y +CONFIG_SYS_NS16550=y +CONFIG_LZ4=y diff --git a/configs/boston64r6el_defconfig b/configs/boston64r6el_defconfig new file mode 100644 index 00..1cd4836b58 --- /dev/null +++ b/configs/boston64r6el_defconfig @@ -0,0 +1,42 @@ +CONFIG_MIPS=y +CONFIG_SYS_TEXT_BASE=0x9FC0 +CONFIG_TARGET_BOSTON=y +CONFIG_SYS_LITTLE_ENDIAN=y +CONFIG_CPU_MIPS64_R6=y +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set +CONFIG_MIPS_BOOT_FDT=y +CONFIG_DEFAULT_DEVICE_TREE="img,boston" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_BEST_MATCH=y
Re: [U-Boot] [RFC 3/3] efi_selftest: test writing to file
Heinrich,
On Sat, May 26, 2018 at 10:34:47AM +0200, Heinrich Schuchardt wrote:
> Signed-off-by: Heinrich Schuchardt
> ---
> lib/efi_selftest/efi_selftest_block_device.c | 56
> 1 file changed, 56 insertions(+)
>
> diff --git a/lib/efi_selftest/efi_selftest_block_device.c
> b/lib/efi_selftest/efi_selftest_block_device.c
> index 4af8bd8cb28..9209ce678ee 100644
> --- a/lib/efi_selftest/efi_selftest_block_device.c
> +++ b/lib/efi_selftest/efi_selftest_block_device.c
> @@ -377,6 +377,7 @@ static int execute(void)
> "Wrong volume label '%ps', expected 'U-BOOT TEST'\n",
> system_info.info.volume_label);
> }
> + /* Read file */
> ret = root->open(root, , (s16 *)L"hello.txt", EFI_FILE_MODE_READ,
>0);
> if (ret != EFI_SUCCESS) {
> @@ -389,6 +390,11 @@ static int execute(void)
> efi_st_error("Failed to read file\n");
> return EFI_ST_FAILURE;
> }
> + if (buf_size != 13) {
> + efi_st_error("Wrong number of bytes read: %u\n",
> + (unsigned int)buf_size);
> + return EFI_ST_FAILURE;
> + }
> if (efi_st_memcmp(buf, "Hello world!", 12)) {
> efi_st_error("Unexpected file content\n");
> return EFI_ST_FAILURE;
> @@ -399,6 +405,56 @@ static int execute(void)
> return EFI_ST_FAILURE;
> }
> ret = root->close(root);
We should not close 'root' here as
> + /* Write file */
> + ret = root->open(root, , (s16 *)L"u-boot.txt",
> + EFI_FILE_MODE_WRITE | EFI_FILE_MODE_CREATE, 0);
we will use it here.
> + if (ret != EFI_SUCCESS) {
> + efi_st_error("Failed to open file\n");
> + return EFI_ST_FAILURE;
> + }
> + buf_size = 7;
> + boottime->set_mem(buf, sizeof(buf), 0);
> + boottime->copy_mem(buf, "U-Boot", buf_size);
> + ret = file->write(file, _size, buf);
> + if (ret != EFI_SUCCESS || buf_size != 7) {
> + efi_st_error("Failed to write file\n");
> + return EFI_ST_FAILURE;
> + }
> + ret = file->close(file);
> + if (ret != EFI_SUCCESS) {
> + efi_st_error("Failed to close file\n");
> + return EFI_ST_FAILURE;
> + }
> + ret = root->close(root);
ditto
Thanks,
-Takahiro AKASHI
> + /* Verify file */
> + boottime->set_mem(buf, sizeof(buf), 0);
> + ret = root->open(root, , (s16 *)L"u-boot.txt", EFI_FILE_MODE_READ,
> + 0);
> + if (ret != EFI_SUCCESS) {
> + efi_st_error("Failed to open file\n");
> + return EFI_ST_FAILURE;
> + }
> + buf_size = sizeof(buf) - 1;
> + ret = file->read(file, _size, buf);
> + if (ret != EFI_SUCCESS) {
> + efi_st_error("Failed to read file\n");
> + return EFI_ST_FAILURE;
> + }
> + if (buf_size != 7) {
> + efi_st_error("Wrong number of bytes read: %u\n",
> + (unsigned int) buf_size);
> + return EFI_ST_FAILURE;
> + }
> + if (efi_st_memcmp(buf, "U-Boot", 7)) {
> + efi_st_error("Unexpected file content %s\n", buf);
> + return EFI_ST_FAILURE;
> + }
> + ret = file->close(file);
> + if (ret != EFI_SUCCESS) {
> + efi_st_error("Failed to close file\n");
> + return EFI_ST_FAILURE;
> + }
> + ret = root->close(root);
> if (ret != EFI_SUCCESS) {
> efi_st_error("Failed to close volume\n");
> return EFI_ST_FAILURE;
> --
> 2.17.0
>
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Re: [U-Boot] inappropriate PCI configuration on arm64 qemu?
Tuomas,
On Thu, May 31, 2018 at 01:32:20PM +0300, Tuomas Tynkkynen wrote:
> Hi Akashi,
>
> On 05/31/2018 08:05 AM, AKASHI Takahiro wrote:
> >Simon,
> >
> >On Wed, May 30, 2018 at 01:18:30PM -0600, Simon Glass wrote:
> >>+Tuomas
> >>
> >>Hi Akashi,
> >>
> >>On 28 May 2018 at 01:59, AKASHI Takahiro wrote:
> >>>When I tried to add a SD card to qemu's virt machine (2.10.0) as,
> >>> --
> >>> -device sdhci-pci \
> >>> -device sd-card,drive=my_sd \
> >>> -drive if=none,id=my_sd,format=raw,file=/path/my/sd.img
> >>> --
> >>>u-boot doesn't configure a SDHCI controller properly and an attached
> >>>device is never detected.
> >>>
> >>>Digging into the code, I found
> >>>* reading BAR5 in dm_pciauto_setup_device() shows BAR5 is a 32-bit address,
> >>>* pciauto_region_allocate() allocates a 64-bit address (0x80.ABCD.)
> >>> to BAR5 as res->bus_lower is 0x80..
> >>>* Upper 32-bit value is not written back to BAR5 because of !found_mem64
> >>> (BAR5 is the last one and no succeeding BAR anyway.)
> >>>
> >>>On the other hand,
> >>>* Qemu defines two PCI memory regions for MMIO:
> >>> (from qemu's hw/arm/virt.c)
> >>> --
> >>> [VIRT_PCIE_MMIO] = { 0x1000, 0x2eff },
> >>> [VIRT_PCIE_PIO] = { 0x3eff, 0x0001 },
> >>> [VIRT_PCIE_ECAM] = { 0x3f00, 0x0100 },
> >>> [VIRT_MEM] ={ 0x4000, RAMLIMIT_BYTES },
> >>> /* Second PCIe window, 512GB wide at the 512GB boundary */
> >>> [VIRT_PCIE_MMIO_HIGH] = { 0x80ULL, 0x80ULL },
> >>> --
> >>>* A PCI card is configured in decode_regions() so that
> >>> 'hose' has only one entry per each type of memory regions.
> >>> This behavior was introduced by Simon's patch:
> >>> --
> >>> commit 9526d83ac5a
> >>> Author: Simon Glass
> >>> Date: Thu Nov 19 20:26:58 2015 -0700
> >>>
> >>> dm: pci: Support decoding ranges with duplicate entries
> >>> --
> >>>* As a result, MMIO region (0x1000.-0x2eff.) is overwritten
> >>> and MMIO_HIGH is the only one available at runtime.
> >>>
> >>>I believe that this behavior is the root cause of my issue, and
> >>>by reverting the patch mentioned above, everything works fine.
> >>>
> >>>While I understand a concern mentioned in the commit message,
> >>>there should be a better way to manage the case.
> >>
> >>There was a series that changed things in this area. Can you take a look?
> >>
> >>PCI: dm: Ignore 64-bit memory regions if CONFIG_SYS_PCI_64BIT not set
> >
> >Ah, I didn't know that, but it seems to me that it is still insufficient.
> >This hack won't work on 32-bit PCI card. I found another patch from Tuomas:
>
> Did you try it? As of today's master all of the patches are applied and at
> least the e1000 NIC and the Intel AHCI card that I tested works.
> The effect of the commit is to indeed avoid the problem you mentioned:
Yes, I ran my patch but *with* CONFIG_SYS_PCI_64BIT.
> >>> * As a result, MMIO region (0x1000.-0x2eff.) is overwritten
> >>>and MMIO_HIGH is the only one available at runtime.
>
> Note that even on aarch64, CONFIG_SYS_PCI_64BIT is *not* set by default.
> And on ARM we would need to skip that region in U-Boot anyway because
> we don't have the means to access physical addresses above the 4GB
> boundary with the CPU using U-Boot's identity-mapped page tables.
Maybe you're right regarding aarch64, but the issue is not about arm/arm64
but PCI configuration. Some arch/machines, freescale mostly?, have
already enabled CONFIG_SYS_PCI_64BIT. I'm afraid that there may be
a possibility that your patch breaks them.
Thanks,
-Takahiro AKASHI
>
> >---
> > commit d71975ae6e0
> > Author: Tuomas Tynkkynen
> > Date: Mon May 14 19:38:13 2018 +0300
> >
> > PCI: autoconfig: Don't allocate 64-bit addresses to 32-bit only
> > resources
> >---
> >
> >This approach looks too conservative if 32-bit window is also available,
> >in addition to 64-bit space, as in the case of qemu-arm.
>
> Yes, the patch is very minimal - I just wanted to fix the silent truncation
> of 64-bit addresses to 32-bit addresses and complain instead, nothing more.
>
> (As the default config of qemu_arm* doesn't have CONFIG_SYS_PCI_64BIT,
> the condition won't actually trigger in practice).
>
> >I'd like to propose supporting at least two type of PCI memory regions,
> >low mem (normal case) and high mem.
> >Attached is my experimental implementation for this although I might have
> >made any mistake as I'm not very much familiar with PCI specification.
> >
>
> Yes, in theory it could be useful for some future hardware, but for QEMU
> point of view the current situation of totally ignoring the 64-bit mem region
> is probably good enough, given that most of the useful hardware that QEMU
> can enable is
[U-Boot] [PATCH 10/15] net: ravb: Add R8A77990 E3 compatible
Add new compatible to the Ethernet AVB driver for R8A77990 E3 SoC.
Signed-off-by: Marek Vasut
Cc: Joe Hershberger
Cc: Nobuhiro Iwamatsu
---
drivers/net/ravb.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c
index 3392e5854d..999894f0f6 100644
--- a/drivers/net/ravb.c
+++ b/drivers/net/ravb.c
@@ -659,6 +659,7 @@ static const struct udevice_id ravb_ids[] = {
{ .compatible = "renesas,etheravb-r8a7796" },
{ .compatible = "renesas,etheravb-r8a77965" },
{ .compatible = "renesas,etheravb-r8a77970" },
+ { .compatible = "renesas,etheravb-r8a77990" },
{ .compatible = "renesas,etheravb-r8a77995" },
{ .compatible = "renesas,etheravb-rcar-gen3" },
{ }
--
2.16.2
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Re: [U-Boot] [PATCH v2 1/2] mmc: sdhci: Update sdhci_send_command() to handle HS200
On 29.5.2018 16:33, Siva Durga Prasad Paladugu wrote:
> This patch updates sdhci_send_command() to handle MMC
> HS200 tuning command.
>
> Signed-off-by: Siva Durga Prasad Paladugu
> ---
> Changes from v1:
> - Fixed spacings as per comment
> ---
> drivers/mmc/sdhci.c | 9 ++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
> index 400f87e..40e28ab 100644
> --- a/drivers/mmc/sdhci.c
> +++ b/drivers/mmc/sdhci.c
> @@ -161,7 +161,8 @@ static int sdhci_send_command(struct mmc *mmc, struct
> mmc_cmd *cmd,
> /* We shouldn't wait for data inihibit for stop commands, even
> though they might use busy signaling */
> if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
> - cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
> + cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
> + cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
> mask &= ~SDHCI_DATA_INHIBIT;
>
> while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
> @@ -183,7 +184,8 @@ static int sdhci_send_command(struct mmc *mmc, struct
> mmc_cmd *cmd,
> sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
>
> mask = SDHCI_INT_RESPONSE;
> - if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
> + if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
> + cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
> mask = SDHCI_INT_DATA_AVAIL;
>
> if (!(cmd->resp_type & MMC_RSP_PRESENT))
> @@ -201,7 +203,8 @@ static int sdhci_send_command(struct mmc *mmc, struct
> mmc_cmd *cmd,
> flags |= SDHCI_CMD_CRC;
> if (cmd->resp_type & MMC_RSP_OPCODE)
> flags |= SDHCI_CMD_INDEX;
> - if (data || cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
> + if (data || cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
> + cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
> flags |= SDHCI_CMD_DATA;
>
> /* Set Transfer mode regarding to data flag */
>
Applied.
Thanks,
Michal
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Re: [U-Boot] [PATCH v2 2/2] mmc: zynqmp: Add HS200 modes support for ZynqMP
On 29.5.2018 16:33, Siva Durga Prasad Paladugu wrote:
> This patch adds HS200 suuport for ZynqMP and enables
> the same for ZC1751 DC1 board which has eMMC on it.
>
> Signed-off-by: Siva Durga Prasad Paladugu
> ---
> Changes from v1:
> - Fixed coding style as per comment
> ---
> configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 +
> drivers/mmc/zynq_sdhci.c | 25
>
> 2 files changed, 18 insertions(+), 8 deletions(-)
>
> diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
> b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
> index f5a3334..96abf61 100644
> --- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
> +++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
> @@ -54,6 +54,7 @@ CONFIG_DM_I2C=y
> CONFIG_SYS_I2C_CADENCE=y
> CONFIG_MISC=y
> CONFIG_DM_MMC=y
> +CONFIG_MMC_HS200_SUPPORT=y
> CONFIG_MMC_SDHCI=y
> CONFIG_MMC_SDHCI_ZYNQ=y
> CONFIG_SPI_FLASH=y
> diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
> index f99731f..ea5af47 100644
> --- a/drivers/mmc/zynq_sdhci.c
> +++ b/drivers/mmc/zynq_sdhci.c
> @@ -32,12 +32,21 @@ struct arasan_sdhci_priv {
> };
>
> #if defined(CONFIG_ARCH_ZYNQMP)
> +#define MMC_HS200_BUS_SPEED 5
> +
> static const u8 mode2timing[] = {
> - [UHS_SDR12] = UHS_SDR12_BUS_SPEED,
> - [UHS_SDR25] = UHS_SDR25_BUS_SPEED,
> - [UHS_SDR50] = UHS_SDR50_BUS_SPEED,
> - [UHS_SDR104] = UHS_SDR104_BUS_SPEED,
> - [UHS_DDR50] = UHS_DDR50_BUS_SPEED,
> + [MMC_LEGACY] = UHS_SDR12_BUS_SPEED,
> + [SD_LEGACY] = UHS_SDR12_BUS_SPEED,
> + [MMC_HS] = HIGH_SPEED_BUS_SPEED,
> + [SD_HS] = HIGH_SPEED_BUS_SPEED,
> + [MMC_HS_52] = HIGH_SPEED_BUS_SPEED,
> + [MMC_DDR_52] = HIGH_SPEED_BUS_SPEED,
> + [UHS_SDR12] = UHS_SDR12_BUS_SPEED,
> + [UHS_SDR25] = UHS_SDR25_BUS_SPEED,
> + [UHS_SDR50] = UHS_SDR50_BUS_SPEED,
> + [UHS_DDR50] = UHS_DDR50_BUS_SPEED,
> + [UHS_SDR104] = UHS_SDR104_BUS_SPEED,
> + [MMC_HS_200] = MMC_HS200_BUS_SPEED,
> };
>
> #define SDHCI_HOST_CTRL2 0x3E
> @@ -160,9 +169,6 @@ static void arasan_sdhci_set_tapdelay(struct sdhci_host
> *host)
> struct mmc *mmc = (struct mmc *)host->mmc;
> u8 uhsmode;
>
> - if (!IS_SD(mmc))
> - return;
> -
> uhsmode = mode2timing[mmc->selected_mode];
>
> if (uhsmode >= UHS_SDR25_BUS_SPEED)
> @@ -175,6 +181,9 @@ static void arasan_sdhci_set_control_reg(struct
> sdhci_host *host)
> struct mmc *mmc = (struct mmc *)host->mmc;
> u32 reg;
>
> + if (!IS_SD(mmc))
> + return;
> +
> if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
> reg = sdhci_readw(host, SDHCI_HOST_CTRL2);
> reg |= SDHCI_18V_SIGNAL;
>
Applied.
Thanks,
Michal
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[U-Boot] [PATCH v4 2/2] mmc: sunxi: run calibration on A64
Along with using new mode it fixes eMMC instability on Pinebook
Signed-off-by: Vasily Khoruzhick
---
arch/arm/include/asm/arch-sunxi/mmc.h | 6 +-
drivers/mmc/sunxi_mmc.c | 11 +++
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h
b/arch/arm/include/asm/arch-sunxi/mmc.h
index 1574b8e8fe..d6664a01f2 100644
--- a/arch/arm/include/asm/arch-sunxi/mmc.h
+++ b/arch/arm/include/asm/arch-sunxi/mmc.h
@@ -46,7 +46,9 @@ struct sunxi_mmc {
u32 cbda; /* 0x94 */
u32 res2[26];
#ifdef CONFIG_SUNXI_GEN_SUN6I
- u32 res3[64];
+ u32 res3[17];
+ u32 samp_dl;
+ u32 res4[46];
#endif
u32 fifo; /* 0x100 / 0x200 FIFO access address */
};
@@ -130,5 +132,7 @@ struct sunxi_mmc {
#define SUNXI_MMC_COMMON_CLK_GATE (1 << 16)
#define SUNXI_MMC_COMMON_RESET (1 << 18)
+#define SUNXI_MMC_CAL_DL_SW_EN (0x1 << 7)
+
struct mmc *sunxi_mmc_init(int sdc_no);
#endif /* _SUNXI_MMC_H */
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 34739c98b9..9e47e06239 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -225,6 +225,17 @@ static int mmc_config_clock(struct sunxi_mmc_priv *priv,
struct mmc *mmc)
rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
writel(rval, >reg->clkcr);
+#ifdef CONFIG_MACH_SUN50I
+ /* A64 needs to run calibration on eMMC controller and we
+* have to set delay of zero before starting calibration.
+* Allwinner BSP driver sets a delay only in the case of
+* using HS400 which is not supported by mainline U-Boot or
+* Linux at the moment
+*/
+ if (priv->mmc_no == 2)
+ writel(SUNXI_MMC_CAL_DL_SW_EN, >reg->samp_dl);
+#endif
+
/* Re-enable Clock */
rval |= SUNXI_MMC_CLK_ENABLE;
writel(rval, >reg->clkcr);
--
2.17.1
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[U-Boot] [PATCH v4 1/2] sunxi-mmc: use new mode on A64
That is necessary for using automatic calibration on A64 eMMC.
Signed-off-by: Vasily khoruzhick
---
arch/arm/mach-sunxi/Kconfig | 1 +
drivers/mmc/sunxi_mmc.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 66fb094ac5..8a35033d1f 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -257,6 +257,7 @@ config MACH_SUN50I
select SUNXI_GEN_SUN6I
select SUN6I_PRCM
select SUNXI_HIGH_SRAM
+ select MMC_SUNXI_HAS_NEW_MODE
select SUPPORT_SPL
select SUNXI_DRAM_DW
select SUNXI_DRAM_DW_32BIT
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index fe6d82c7b4..34739c98b9 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -166,7 +166,9 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv,
unsigned int hz)
if (new_mode) {
#ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE
+#ifndef CONFIG_MACH_SUN50I
val = CCM_MMC_CTRL_MODE_SEL_NEW;
+#endif
setbits_le32(>reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);
#endif
} else {
--
2.17.1
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Re: [U-Boot] [PATCH v3 1/2] sunxi-mmc: use new mode on A64
On Fri, Jun 1, 2018 at 1:42 AM Maxime Ripard wrote:
>
> On Thu, May 31, 2018 at 09:43:20AM -0700, Vasily Khoruzhick wrote:
> > On Thu, May 31, 2018 at 5:00 AM, Maxime Ripard
> > wrote:
> > > On Wed, May 30, 2018 at 09:02:18PM -0700, Vasily Khoruzhick wrote:
> > >> That is necessary for using automatic calibration on A64 eMMC.
> > >>
> > >> Signed-off-by: Vasily khoruzhick
> > >> ---
> > >> arch/arm/mach-sunxi/Kconfig | 1 +
> > >> drivers/mmc/sunxi_mmc.c | 4 ++--
> > >> 2 files changed, 3 insertions(+), 2 deletions(-)
> > >>
> > >> diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> > >> index 66fb094ac5..8a35033d1f 100644
> > >> --- a/arch/arm/mach-sunxi/Kconfig
> > >> +++ b/arch/arm/mach-sunxi/Kconfig
> > >> @@ -257,6 +257,7 @@ config MACH_SUN50I
> > >> select SUNXI_GEN_SUN6I
> > >> select SUN6I_PRCM
> > >> select SUNXI_HIGH_SRAM
> > >> + select MMC_SUNXI_HAS_NEW_MODE
> > >> select SUPPORT_SPL
> > >> select SUNXI_DRAM_DW
> > >> select SUNXI_DRAM_DW_32BIT
> > >> diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
> > >> index fe6d82c7b4..3bffb1b02e 100644
> > >> --- a/drivers/mmc/sunxi_mmc.c
> > >> +++ b/drivers/mmc/sunxi_mmc.c
> > >> @@ -165,10 +165,10 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv
> > >> *priv, unsigned int hz)
> > >> }
> > >>
> > >> if (new_mode) {
> > >> -#ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE
> > >> +#if defined(CONFIG_MMC_SUNXI_HAS_NEW_MODE) &&
> > >> !defined(CONFIG_MACH_SUN50I)
> > >> val = CCM_MMC_CTRL_MODE_SEL_NEW;
> > >> - setbits_le32(>reg->ntsr,
> > >> SUNXI_MMC_NTSR_MODE_SEL_NEW);
> > >> #endif
> > >> + setbits_le32(>reg->ntsr,
> > >> SUNXI_MMC_NTSR_MODE_SEL_NEW);
> > >
> > > This is slightly more complicated than that, we have three cases we
> > > need to support:
> > > - Devices without the new mode (A31 and before)
> > > - Devices with support for the new mode that can be toggled (A23/A33 to
> > > H3/H5 iirc)
> > > - Devices with support for the new mode only
> >
> > Right.
> >
> > > The latter was introduced by the A64, but is also found on other SoCs
> > > now (such as the H6).
> > >
> > > So I guess here we need an extra config option to handle it, or even
> > > better, base the decision on the compatible like we're doing in Linux.
> >
> > OK, sounds reasonable. However using compatibles (and thus switching
> > to DM_MMC) would be more invasive chance and I won't be able to test
> > it on all platforms that use sunxi_mmc driver.
>
> We already have DM_MMC support in the driver. The only thing that
> seems to be missing are the A64 compatibles, and to test. But most of
> the driver is shared, so I don't expect a lot of trouble there.
With DM_MMC enabled SPL doesn't fit into 32k on A64:
aarch64-linux-gnu-ld.bfd: region `.sram' overflowed by 10584 bytes
>
> Maxime
>
> --
> Maxime Ripard, Bootlin (formerly Free Electrons)
> Embedded Linux and Kernel engineering
> https://bootlin.com
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Re: [U-Boot] [PULL] u-boot-mips/master
On Fri, Jun 01, 2018 at 09:24:58PM +0200, Daniel Schwierzeck wrote: > Travis CI build: > > https://travis-ci.org/danielschwierzeck/u-boot/builds/386679112 > > > > The following changes since commit c3c863880479edeb5b08226e622d13c91326e4a7: > > add FIT data-position & data-offset property support (2018-05-26 18:19:19 > -0400) > > are available in the Git repository at: > > git://git.denx.de/u-boot-mips.git master > > for you to fetch changes up to 9ca33ebf1c3a950d06cb50dba8d0a94e150bc0fd: > > phy: bcm6318-usbh: convert to use live dt (2018-06-01 15:56:02 +0200) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [GIT PULL] Xilinx changes for v2018.07-2
On Fri, Jun 01, 2018 at 03:23:33PM +0200, Michal Simek wrote: > Hi Tom, > > please pull these changes to your tree. > Buildman and travis looks good > https://travis-ci.org/michalsimek/u-boot/builds/386578029 > > Thanks, > Michal > > The following changes since commit c3c863880479edeb5b08226e622d13c91326e4a7: > > add FIT data-position & data-offset property support (2018-05-26 > 18:19:19 -0400) > > are available in the Git repository at: > > git://www.denx.de/git/u-boot-microblaze.git tags/xilinx-for-v2018.07-2 > > for you to fetch changes up to a18d09ea384fb66105fbfa24fd2d1288754b8f07: > > fpga: zynqmp: Add secure bitstream loading for ZynqMP (2018-06-01 > 11:37:31 +0200) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 0/2] sunxi: fix eMMC stability issues on A64
eMMC seems to require new clocking mode and calibration on A64, otherwise it is pretty unstable on some boards (e.g. Pinebook) with some eMMCs. v2: - improve comment about calibration for eMMC on A64 - simplify ifdef-s around configuring delays v3: - fix fallout due to ifdef simplification in v2 v4: - really fix ifdefs this time Vasily Khoruzhick (2): sunxi-mmc: use new mode on A64 mmc: sunxi: run calibration on A64 arch/arm/include/asm/arch-sunxi/mmc.h | 6 +- arch/arm/mach-sunxi/Kconfig | 1 + drivers/mmc/sunxi_mmc.c | 13 + 3 files changed, 19 insertions(+), 1 deletion(-) -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH V2] spl: fit: Fix support for loading FPGA bitstream
Move the FPGA loading from IS_ENABLED(CONFIG_SPL_OS_BOOT) &&
IS_ENABLED(CONFIG_SPL_GZIP) conditional. The FPGA loading can
be used without OS loading and GZIP support in SPL. This issue
was most likely induced by some merge conflict, so fix it.
Signed-off-by: Marek Vasut
Cc: Tom Rini
---
V2: Wrap the FPGA loading into a conditional to prevent platforms
from going oversize
---
common/spl/spl_fit.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 2821a3e268..0cd7f7b076 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -185,16 +185,19 @@ static int spl_load_fit_image(struct spl_load_info *info,
ulong sector,
int ret;
#endif
+ if (IS_ENABLED(CONFIG_SPL_FPGA_SUPPORT) ||
+ (IS_ENABLED(CONFIG_SPL_OS_BOOT) && IS_ENABLED(CONFIG_SPL_GZIP))) {
+ if (fit_image_get_type(fit, node, ))
+ puts("Cannot get image type.\n");
+ else
+ debug("%s ", genimg_get_type_name(type));
+ }
+
if (IS_ENABLED(CONFIG_SPL_OS_BOOT) && IS_ENABLED(CONFIG_SPL_GZIP)) {
if (fit_image_get_comp(fit, node, _comp))
puts("Cannot get image compression format.\n");
else
debug("%s ", genimg_get_comp_name(image_comp));
-
- if (fit_image_get_type(fit, node, ))
- puts("Cannot get image type.\n");
- else
- debug("%s ", genimg_get_type_name(type));
}
if (fit_image_get_load(fit, node, _addr))
--
2.16.2
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[U-Boot] [PULL] u-boot-sh/master
The following changes since commit c3c863880479edeb5b08226e622d13c91326e4a7: add FIT data-position & data-offset property support (2018-05-26 18:19:19 -0400) are available in the Git repository at: git://git.denx.de/u-boot-sh.git master for you to fetch changes up to 0bb5d24852d8051b70b2becc74f3a2c4fb925dbb: ARM: dts: rmobile: Sync R8A77990 Ebisu DTS with Linux (2018-06-01 09:47:22 +0200) Marek Vasut (20): ARM: rmobile: Enable MTD partitioning on Gen2 with SF ARM: rmobile: Represent SF partitioning with mtdparts on Alt ARM: rmobile: Represent SF partitioning with mtdparts on Gose ARM: rmobile: Represent SF partitioning with mtdparts on Koelsch ARM: rmobile: Represent SF partitioning with mtdparts on Lager ARM: rmobile: Represent SF partitioning with mtdparts on Porter ARM: rmobile: Represent SF partitioning with mtdparts on Silk ARM: rmobile: Represent SF partitioning with mtdparts on Stout clk: renesas: Fix swapped arguments in debug message clk: renesas: Pass clock rate around as 64bit number internally clk: renesas: Add PLL1 and PLL3 dividers clk: renesas: Add PE clock handling clk: renesas: Add R8A77990 E3 clock tables pinctrl: renesas: Initial R8A77990 PFC support gpio: rmobile: Add R8A77990 E3 compatible mmc: renesas-sdhi: Add R8A77990 E3 compatible net: ravb: Add R8A77990 E3 compatible ARM: renesas: Add R8A77990 E3 SoC ID ARM: renesas: Add R8A77990 E3 Ebisu board ARM: dts: rmobile: Sync R8A77990 Ebisu DTS with Linux Takeshi Kihara (2): pinctrl: renesas: Add PORT_GP_11 helper macro ARM: dts: rmobile: Add Renesas Ebisu board support Yoshihiro Shimoda (1): ARM: dts: rmobile: Add Renesas R8A77990 SoC support arch/arm/dts/Makefile |1 + arch/arm/dts/r8a77990-ebisu-u-boot.dts| 10 + arch/arm/dts/r8a77990-ebisu.dts | 65 ++ arch/arm/dts/r8a77990-u-boot.dtsi |9 + arch/arm/dts/r8a77990.dtsi| 281 +++ arch/arm/mach-rmobile/Kconfig.64 |9 + arch/arm/mach-rmobile/cpu_info.c |1 + arch/arm/mach-rmobile/include/mach/rmobile.h |1 + board/renesas/ebisu/Kconfig | 15 ++ board/renesas/ebisu/MAINTAINERS |6 + board/renesas/ebisu/Makefile |9 + board/renesas/ebisu/ebisu.c | 87 +++ configs/alt_defconfig |5 + configs/gose_defconfig|5 + configs/koelsch_defconfig |5 + configs/lager_defconfig |5 + configs/porter_defconfig |5 + configs/r8a77990_ebisu_defconfig | 64 ++ configs/silk_defconfig|5 + configs/stout_defconfig |5 + drivers/clk/renesas/Kconfig |7 + drivers/clk/renesas/Makefile |1 + drivers/clk/renesas/clk-rcar-gen3.c | 102 ++--- drivers/clk/renesas/r8a77990-cpg-mssr.c | 303 + drivers/clk/renesas/rcar-gen3-cpg.h |6 +- drivers/gpio/gpio-rcar.c |1 + drivers/mmc/renesas-sdhi.c|1 + drivers/net/ravb.c|1 + drivers/pinctrl/renesas/Kconfig | 11 + drivers/pinctrl/renesas/Makefile |1 + drivers/pinctrl/renesas/pfc-r8a77990.c| 1732 drivers/pinctrl/renesas/pfc.c | 11 + drivers/pinctrl/renesas/sh_pfc.h |9 +- include/configs/ebisu.h | 34 +++ include/configs/rcar-gen2-common.h|8 + include/dt-bindings/clock/r8a77990-cpg-mssr.h | 63 ++ 36 files changed, 2850 insertions(+), 34 deletions(-) create mode 100644 arch/arm/dts/r8a77990-ebisu-u-boot.dts create mode 100644 arch/arm/dts/r8a77990-ebisu.dts create mode 100644 arch/arm/dts/r8a77990-u-boot.dtsi create mode 100644 arch/arm/dts/r8a77990.dtsi create mode 100644 board/renesas/ebisu/Kconfig create mode 100644 board/renesas/ebisu/MAINTAINERS create mode 100644 board/renesas/ebisu/Makefile create mode 100644 board/renesas/ebisu/ebisu.c create mode 100644 configs/r8a77990_ebisu_defconfig create mode 100644 drivers/clk/renesas/r8a77990-cpg-mssr.c create mode 100644 drivers/pinctrl/renesas/pfc-r8a77990.c create mode 100644 include/configs/ebisu.h create mode 100644 include/dt-bindings/clock/r8a77990-cpg-mssr.h -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PULL] u-boot-mips/master
Travis CI build: https://travis-ci.org/danielschwierzeck/u-boot/builds/386679112 The following changes since commit c3c863880479edeb5b08226e622d13c91326e4a7: add FIT data-position & data-offset property support (2018-05-26 18:19:19 -0400) are available in the Git repository at: git://git.denx.de/u-boot-mips.git master for you to fetch changes up to 9ca33ebf1c3a950d06cb50dba8d0a94e150bc0fd: phy: bcm6318-usbh: convert to use live dt (2018-06-01 15:56:02 +0200) Álvaro Fernández Rojas (17): dm: core: add functions to get memory-mapped I/O addresses watchdog: bcm6345: convert to use live dt serial: bcm6345: convert to use live dt clk: bcm6345: convert to use live dt reset: bcm6345: convert to use live dt gpio: bcm6345: convert to use live dt led: bcm6358: convert to use live dt led: bcm6328: convert to use live dt power: domain: bcm6328: convert to use live dt spi: bcm63xx_spi: convert to use live dt spi: bcm63xx_hsspi: convert to use live dt ram: bmips: convert to use live dt cpu: bmips: convert to use live dt phy: bcm6348-usbh: convert to use live dt phy: bcm6358-usbh: convert to use live dt phy: bcm6368-usbh: convert to use live dt phy: bcm6318-usbh: convert to use live dt drivers/clk/clk_bcm6345.c | 8 ++-- drivers/core/fdtaddr.c | 15 +++ drivers/core/read.c | 17 + drivers/cpu/bmips_cpu.c | 12 +++- drivers/gpio/bcm6345_gpio.c | 18 +- drivers/led/led_bcm6328.c | 52 +--- drivers/led/led_bcm6358.c | 44 +++- drivers/phy/bcm6318-usbh-phy.c | 10 +++--- drivers/phy/bcm6348-usbh-phy.c | 10 +++--- drivers/phy/bcm6358-usbh-phy.c | 10 +++--- drivers/phy/bcm6368-usbh-phy.c | 9 +++-- drivers/power/domain/bcm6328-power-domain.c | 8 ++-- drivers/ram/bmips_ram.c | 7 ++- drivers/reset/reset-bcm6345.c | 8 ++-- drivers/serial/serial_bcm6345.c | 8 ++-- drivers/spi/bcm63xx_hsspi.c | 12 +++- drivers/spi/bcm63xx_spi.c | 12 +++- drivers/watchdog/bcm6345_wdt.c | 8 ++-- include/dm/fdtaddr.h| 22 ++ include/dm/read.h | 32 test/dm/test-fdt.c | 42 ++ 21 files changed, 198 insertions(+), 166 deletions(-) signature.asc Description: OpenPGP digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 2/2] watchdog: Kconfig: add config to disable wdog reset
Add Kconfig support for CONFIG_WATCHDOG_RESET_DISABLE, use this config
to disable watchdog reset in imx_watchdog driver, so that the watchdog
will not be fed in u-boot.
Signed-off-by: Xiaoliang Yang
---
arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2 |3 +++
drivers/watchdog/Kconfig |6 ++
drivers/watchdog/imx_watchdog.c|2 ++
3 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2
b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2
index 87b91eb..c43a99b 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2
@@ -18,3 +18,6 @@ Use following config to set watchdog timeout, if this config
is not defined,
the default timeout value is 128s which is the maximum. Set 10 seconds for
example:
#define CONFIG_WATCHDOG_TIMEOUT_MSECS 1
+Use following config to disable reset watchdog, so that the watchdog will
+not be fed in u-boot:
+#define CONFIG_WATCHDOG_RESET_DISABLE
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index a526afd..1958c17 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -109,4 +109,10 @@ config IMX_WATCHDOG
Select this to enable IMX watchdog timer, which can be found on
some i.mx and fsl-lsch2 SoCs.
+config WATCHDOG_RESET_DISABLE
+ bool "Disable reset watchdog"
+ help
+ Disable reset watchdog, which can let WATCHDOG_RESET invalid, so
+ that the watchdog will not be fed in u-boot.
+
endmenu
diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c
index 3ad4e55..6691ee9 100644
--- a/drivers/watchdog/imx_watchdog.c
+++ b/drivers/watchdog/imx_watchdog.c
@@ -20,10 +20,12 @@
#ifdef CONFIG_IMX_WATCHDOG
void hw_watchdog_reset(void)
{
+#ifndef CONFIG_WATCHDOG_RESET_DISABLE
struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
writew(0x, >wsr);
writew(0x, >wsr);
+#endif /* CONFIG_WATCHDOG_RESET_DISABLE*/
}
void hw_watchdog_init(void)
--
1.7.1
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Re: [U-Boot] [PATCH v2 1/2] watchdog: driver support for fsl-lsch2
v1 -> v2: Because of imx_watchdog.c driver not supports all layerscape SoCs, change to build imx_watchdog.o only when enable IMX_WATCHDOG for fsl-lsch2 SoCs. Add IMX_WATCHDOG in drivers/watchdog/Kconfig. Changes in v2: drivers/watchdog/Kconfig |6 ++ drivers/watchdog/Makefile |2 ++ ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 1/2] watchdog: driver support for fsl-lsch2
Support watchdog driver for fsl-lsch2. If you want to use it, please enable CONFIG_IMX_WATCHDOG, and CONFIG_HW_WATCHDOG. define CONFIG_WATCHDOG_TIMEOUT_MSECS to set watchdog timeout. Signed-off-by: Xiaoliang Yang --- arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2 | 10 ++ drivers/watchdog/Kconfig |6 ++ drivers/watchdog/Makefile |2 ++ drivers/watchdog/imx_watchdog.c| 11 +++ 4 files changed, 29 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2 index a6ef830..87b91eb 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2 +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2 @@ -8,3 +8,13 @@ Freescale LayerScape with Chassis Generation 2 This architecture supports Freescale ARMv8 SoCs with Chassis generation 2, for example LS1043A. + +Watchdog support Overview +--- +Support watchdog driver for Layerscape. Use following configs to enable it: +#define CONFIG_IMX_WATCHDOG +#define CONFIG_HW_WATCHDOG +Use following config to set watchdog timeout, if this config is not defined, +the default timeout value is 128s which is the maximum. Set 10 seconds for +example: +#define CONFIG_WATCHDOG_TIMEOUT_MSECS 1 diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 148c6a0..a526afd 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -103,4 +103,10 @@ config WDT_CDNS Select this to enable Cadence watchdog timer, which can be found on some Xilinx Microzed Platform. +config IMX_WATCHDOG + bool "IMX watchdog timer support" + help + Select this to enable IMX watchdog timer, which can be found on + some i.mx and fsl-lsch2 SoCs. + endmenu diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index f405f51..159fc11 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -7,6 +7,8 @@ obj-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 mx7 vf610)) obj-y += imx_watchdog.o +else +obj-$(CONFIG_IMX_WATCHDOG) += imx_watchdog.o endif obj-$(CONFIG_S5P) += s5p_wdt.o obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c index 3f826d1..3ad4e55 100644 --- a/drivers/watchdog/imx_watchdog.c +++ b/drivers/watchdog/imx_watchdog.c @@ -8,6 +8,13 @@ #include #include #include +#ifdef CONFIG_FSL_LAYERSCAPE +#ifdef CONFIG_FSL_LSCH3 +#include +#elif defined(CONFIG_FSL_LSCH2) +#include +#endif +#endif #include #ifdef CONFIG_IMX_WATCHDOG @@ -33,8 +40,12 @@ void hw_watchdog_init(void) #define CONFIG_WATCHDOG_TIMEOUT_MSECS 128000 #endif timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1; +#ifdef CONFIG_FSL_LAYERSCAPE + writew((WCR_WDA | WCR_SRS | WCR_WDE) << 8 | timeout, >wcr); +#else writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | WCR_SRS | WCR_WDA | SET_WCR_WT(timeout), >wcr); +#endif /* CONFIG_FSL_LAYERSCAPE*/ hw_watchdog_reset(); } #endif -- 1.7.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/7] usb: introduce a separate config option for DM USB device
Hi Jean-Jacques,
> Using CONFIG_DM_USB for this purpose prevents using DM_USB for host
> and not for device.
>
> Signed-off-by: Jean-Jacques Hiblot
>
> ---
>
> Changes in v2:
> - select DM_USB_DEV by default for zynqmp platforms
>
> arch/arm/Kconfig| 2 ++
> drivers/usb/Kconfig | 6 ++
> drivers/usb/dwc3/core.c | 2 +-
> drivers/usb/dwc3/dwc3-generic.c | 4 +++-
> 4 files changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 0d1802b..caf7053 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -841,6 +841,7 @@ config ARCH_ZYNQMP_R5
> select DM
> select DM_SERIAL
> select CLK
> + imply DM_USB_DEV
>
> config ARCH_ZYNQMP
> bool "Xilinx ZynqMP based platform"
> @@ -855,6 +856,7 @@ config ARCH_ZYNQMP
> select SPL_CLK if SPL
> select DM_USB if USB
> imply FAT_WRITE
> + imply DM_USB_DEV
>
> config TEGRA
> bool "NVIDIA Tegra"
> diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
> index 4fbe172..3587ba4 100644
> --- a/drivers/usb/Kconfig
> +++ b/drivers/usb/Kconfig
> @@ -47,6 +47,12 @@ config DM_USB
> declared with the U_BOOT_USB_DEVICE() macro and will be
> automatically probed when found on the bus.
>
> +config DM_USB_DEV
> + bool "Enable driver model for USB (Peripheral mode)"
> + depends on DM_USB
> + help
> + Enable driver model for USB (Peripheral mode).
> +
> source "drivers/usb/host/Kconfig"
>
> source "drivers/usb/dwc3/Kconfig"
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index 1ab5cee..d5ee6d9 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -789,7 +789,7 @@ MODULE_AUTHOR("Felipe Balbi ");
> MODULE_LICENSE("GPL v2");
> MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
>
> -#ifdef CONFIG_DM_USB
> +#ifdef CONFIG_DM_USB_DEV
>
> int dwc3_init(struct dwc3 *dwc)
> {
> diff --git a/drivers/usb/dwc3/dwc3-generic.c
> b/drivers/usb/dwc3/dwc3-generic.c index ca63eac..2c1e696 100644
> --- a/drivers/usb/dwc3/dwc3-generic.c
> +++ b/drivers/usb/dwc3/dwc3-generic.c
> @@ -21,7 +21,7 @@
> #include "gadget.h"
> #include "linux-compat.h"
>
> -DECLARE_GLOBAL_DATA_PTR;
> +#ifdef CONFIG_DM_USB_DEV
>
> int usb_gadget_handle_interrupts(int index)
> {
> @@ -98,6 +98,8 @@ U_BOOT_DRIVER(dwc3_generic_peripheral) = {
> .flags = DM_FLAG_ALLOC_PRIV_DMA,
> };
>
> +#endif
> +
> static int dwc3_generic_bind(struct udevice *parent)
> {
> const void *fdt = gd->fdt_blob;
Reviewed-by: Lukasz Majewski
Best regards,
Lukasz Majewski
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Re: [U-Boot] [PATCH v2 1/7] usb: gadget: Do not call board_usb_xxx() directly in USB gadget drivers
Hi Jean-Jacques,
> Add 2 functions to wrap the calls to board_usb_init() and
> board_usb_cleanup().
> This is a preparatory work for DM support for UDC drivers
> (DM_USB_DEV).
>
> Signed-off-by: Jean-Jacques Hiblot
>
> ---
>
> Changes in v2:
> - Updated commit log
> - Fixed typo in thordown.c
>
> cmd/fastboot.c | 4 ++--
> cmd/rockusb.c | 4 ++--
> cmd/thordown.c | 4 ++--
> cmd/usb_gadget_sdp.c | 4 ++--
> cmd/usb_mass_storage.c | 4 ++--
> common/dfu.c | 6 +++---
> drivers/usb/gadget/ether.c | 38
> +- include/linux/usb/gadget.h |
> 10 ++ 8 files changed, 28 insertions(+), 46 deletions(-)
>
> diff --git a/cmd/fastboot.c b/cmd/fastboot.c
> index a5ec5f4..93f97fd 100644
> --- a/cmd/fastboot.c
> +++ b/cmd/fastboot.c
> @@ -24,7 +24,7 @@ static int do_fastboot(cmd_tbl_t *cmdtp, int flag,
> int argc, char *const argv[]) usb_controller = argv[1];
> controller_index = simple_strtoul(usb_controller, NULL, 0);
>
> - ret = board_usb_init(controller_index, USB_INIT_DEVICE);
> + ret = usb_gadget_initialize(controller_index);
> if (ret) {
> pr_err("USB init failed: %d", ret);
> return CMD_RET_FAILURE;
> @@ -55,7 +55,7 @@ static int do_fastboot(cmd_tbl_t *cmdtp, int flag,
> int argc, char *const argv[]) exit:
> g_dnl_unregister();
> g_dnl_clear_detach();
> - board_usb_cleanup(controller_index, USB_INIT_DEVICE);
> + usb_gadget_release(controller_index);
>
> return ret;
> }
> diff --git a/cmd/rockusb.c b/cmd/rockusb.c
> index 8206643..e0c1480 100644
> --- a/cmd/rockusb.c
> +++ b/cmd/rockusb.c
> @@ -33,7 +33,7 @@ static int do_rockusb(cmd_tbl_t *cmdtp, int flag,
> int argc, char *const argv[]) dev_index = simple_strtoul(devnum,
> NULL, 0); rockusb_dev_init(devtype, dev_index);
>
> - ret = board_usb_init(controller_index, USB_INIT_DEVICE);
> + ret = usb_gadget_initialize(controller_index);
> if (ret) {
> printf("USB init failed: %d\n", ret);
> return CMD_RET_FAILURE;
> @@ -62,7 +62,7 @@ static int do_rockusb(cmd_tbl_t *cmdtp, int flag,
> int argc, char *const argv[]) exit:
> g_dnl_unregister();
> g_dnl_clear_detach();
> - board_usb_cleanup(controller_index, USB_INIT_DEVICE);
> + usb_gadget_release(controller_index);
>
> return ret;
> }
> diff --git a/cmd/thordown.c b/cmd/thordown.c
> index e297de2..05f308a 100644
> --- a/cmd/thordown.c
> +++ b/cmd/thordown.c
> @@ -30,7 +30,7 @@ int do_thor_down(cmd_tbl_t *cmdtp, int flag, int
> argc, char * const argv[]) goto done;
>
> int controller_index = simple_strtoul(usb_controller, NULL,
> 0);
> - ret = board_usb_init(controller_index, USB_INIT_DEVICE);
> + ret = usb_gadget_initialize(controller_index);
> if (ret) {
> pr_err("USB init failed: %d", ret);
> ret = CMD_RET_FAILURE;
> @@ -55,7 +55,7 @@ int do_thor_down(cmd_tbl_t *cmdtp, int flag, int
> argc, char * const argv[])
> exit:
> g_dnl_unregister();
> - board_usb_cleanup(controller_index, USB_INIT_DEVICE);
> + usb_gadget_release(controller_index);
> done:
> dfu_free_entities();
>
> diff --git a/cmd/usb_gadget_sdp.c b/cmd/usb_gadget_sdp.c
> index ba1f66a..808ed97 100644
> --- a/cmd/usb_gadget_sdp.c
> +++ b/cmd/usb_gadget_sdp.c
> @@ -20,7 +20,7 @@ static int do_sdp(cmd_tbl_t *cmdtp, int flag, int
> argc, char * const argv[])
> char *usb_controller = argv[1];
> int controller_index = simple_strtoul(usb_controller, NULL,
> 0);
> - board_usb_init(controller_index, USB_INIT_DEVICE);
> + usb_gadget_initialize(controller_index);
>
> g_dnl_clear_detach();
> g_dnl_register("usb_dnl_sdp");
> @@ -37,7 +37,7 @@ static int do_sdp(cmd_tbl_t *cmdtp, int flag, int
> argc, char * const argv[])
> exit:
> g_dnl_unregister();
> - board_usb_cleanup(controller_index, USB_INIT_DEVICE);
> + usb_gadget_release(controller_index);
>
> return ret;
> }
> diff --git a/cmd/usb_mass_storage.c b/cmd/usb_mass_storage.c
> index 89b9ddf..7c6d0c6 100644
> --- a/cmd/usb_mass_storage.c
> +++ b/cmd/usb_mass_storage.c
> @@ -160,7 +160,7 @@ static int do_usb_mass_storage(cmd_tbl_t *cmdtp,
> int flag,
> controller_index = (unsigned int)(simple_strtoul(
> usb_controller, NULL, 0));
> - if (board_usb_init(controller_index, USB_INIT_DEVICE)) {
> + if (usb_gadget_initialize(controller_index)) {
> pr_err("Couldn't init USB controller.");
> rc = CMD_RET_FAILURE;
> goto cleanup_ums_init;
> @@ -231,7 +231,7 @@ static int do_usb_mass_storage(cmd_tbl_t *cmdtp,
> int flag, cleanup_register:
> g_dnl_unregister();
> cleanup_board:
> - board_usb_cleanup(controller_index, USB_INIT_DEVICE);
> + usb_gadget_release(controller_index);
> cleanup_ums_init:
> ums_fini();
>
> diff --git
Re: [U-Boot] Exception Level switching seems broken on RK3399
On Thu, May 24, 2018 at 7:05 PM, Dr. Philipp Tomsich wrote: > Vincente, > > On 24 May 2018, at 18:48, Vicente Bergas wrote: > > Hello Philipp, > your answer is much appreciated. > > On Thu, May 24, 2018 at 1:07 PM, Dr. Philipp Tomsich > wrote: > > Vincente, > > On 19 May 2018, at 16:58, Vicente Bergas wrote: > > Hello, > I am writing this from a standalone Sapphire board [1], > that is, without the Excavator base board. > The CPU is the Rockchip RK3399, which implements ARMv8.0-A. > > Currently the boot process is: > 1.- Boot ROM > 2.- SPL, provided as closed source binary blob [2] > > > SPL-support is available in mainline U-Boot. We developed this for > the RK3399-Q7 and it has been successfully used on other RK3399 > boards (e.g. I know that some Firefly-users are using this). > > > Thank you! > > > 3.- ATF, closed source binary blob [3] >(not using the one from [2] because of stability issues) > > > Why use the closed-source blob, if the RK3399 is supported in the ATF > mainline and an ATF can be compiled from source? > > > Currently I am using both binary blobs (SPL and ATF) because I could > not make it work another way. I'll give it another try. > > > 4.- Mainline u-boot, master branch > 5.- Mainline linux, master branch > > I would like to use an opensource boot process. > As a first approach I try to completely remove the ATF and > replace the SPL with the one from u-boot. > The modified boot process looks like: > 1.- Boot ROM > 2.- SPL, from mainline u-boot, master branch > 3.- Mainline u-boot, master branch > 4.- Mainline linux, master branch > But it is not working. > > The replaced SPL works fine and loads u-boot. > U-boot also works fine, loads linux and jumps into it. > > > Yes, we’ve done some work to enable us to run U-Boot in EL3 on > the RK3399 (as we use it for programming the secure e-fuses on > the RK3399-Q7 in our factory programming setup). > > > I can indeed confirm that U-Boot runs fine in EL3. > > > But then, linux never gets executed. > > I have traced the issue to: arch/arm/include/asm/macro.h > 202: msr spsr_el3, \tmp > 203: msr elr_el3, \ep > 204: eret // This is the last instruction executed > > For testing, I have also set CONFIG_ARMV8_SWITCH_TO_EL1 and > checked that switch_to_el1 from arch/arm/lib/bootm.c is not reached. > > At this point I have a few questions: > 1.- Is my first approach feasible? That is, is it possible to boot >this CPU without ATF? > > > It is feasible (i.e.: requires implementation work) but not recommended: > Linux will use PSCI to bring up the secondary CPUs. We have run Linux > (limited to a single CPU) in EL3 on this CPU during our own board bringup, > but I would strongly discourage this as it will entail unnecessary effort. > > > There is a misunderstanding here. My intention was to run U-Boot in EL3, > then switch to EL2 or EL1 from within U-Boot and afterwards run Linux > in the lower EL. > > > 2.- If so, what should I do to make it work? Probably it is just >a configuration issue, but I do not know what to check. [4] > 3.- Else, why do I need ATF? > > > ATF is the secure monitor on ARMv8 and provides services such as PSCI > to start up secondary CPUs. It will usually also be part of > power-management > on most SoCs (after all: power configuration needs to be done in the secure > envelope). > > > Do you mean that without ATF I can only run a single CPU core? > > > Linux (on the RK3399) uses PSCI to start the secondary CPUs and uses SMC > (secure monitor call) to call into PSCI. The PSCI handlers thus live within > ATF. > > While it is technically possible to start up the other cores using other > mechanisms, > it is the ‘road less travelled’. > > Cheers, > Philipp. > > > Regards, > Vicenç. > > > Regards, > Philipp. > > > Regards, > Vicenç. Hello Philipp, I have managed to make it work. It turns out that support for this platform was added to mainline after my first attempt. In doing so I have modified the configuration this way: --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -11,7 +11,7 @@ CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" +CONFIG_SPL_FIT_GENERATOR="tools/make_fit_atf" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y @@ -27,7 +27,7 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_SPL_OF_PLATDATA=y +CONFIG_MKIMAGE_DTC_PATH="scripts/dtc/dtc" CONFIG_ENV_IS_IN_MMC=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y SPL_FIT_GENERATOR and SPL_OF_PLATDATA require python. In order to remove this dependency: 1.- I have written a C version for SPL_FIT_GENERATOR. 2.- Disabled SPL_OF_PLATDATA, it just works. MKIMAGE_DTC_PATH requires dtc in the PATH. In order to remove this dependency, I have changed it to use the built-in
[U-Boot] DRAM clock frequency issue
Hi - I have a target Atheros 9344 board on which I have loaded U-boot version 1.23.2. On the reference board, the DRAM clock frequency has been set to 400 MHz and it works well. But when the same clock frequency is used on my target board , mtest (memory test) fails. However, when I reduced the clock frequency to 300 MHz, the mtest passes and it appears to be stable. The reference and target boards are alike in almost every respect. The DRAM specifications are the same but the manufacturer is different. I tried setting the DRAM timing parameters on my target DRAM to be aligned with the numbers in the data sheet. When I load the Linux kernel after this, there are a variety of kernel panics seen if I leave it on overnight. They are OOPS messages such as "Unable to handle kernel paging request at virtual address", I think they may be related to the DRAM clock frequency setting. I'd like to eventually use 400 MHz clock for the DRAM clock frequency on my target board. If anyone has faced a similar scenario earlier, kindly share your tips to debug the problem. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] sunxi: use CONFIG_DEFAULT_FDT_FILE everywhere
On Thu, May 31, 2018 at 05:59:16PM -0700, Martin Kelly wrote: > Currently, sunxi-common.h ignores CONFIG_DEFAULT_FDT_FILE and assumes > the kernel fdtfile and the u-boot devicetree names are the same. > Although this is typically the case, sometimes you might want to > customize one of these differently, so it's useful to allow them to be > different. > > Fix this to use only CONFIG_DEFAULT_FDT_FILE as other boards do, and set > CONFIG_DEFAULT_FDT_FILE in board files to be the same as the current > fdtfile= setting. > > Signed-off-by: Martin Kelly I'd really prefer not to do that. There's going to be a long trail of defconfig that will be sent at pretty much the same time that are not going to have it and that will go unnotice for some time. And there's obviously the useless churn in all the defconfig that are not in the case where it makes sense to override DEFAULT_FDT_FILE. Why not create a Kconfig boolean that allows to select whether or not you want DEFAULT_FDT_FILE to be DEFAULT_DEVICE_TREE + .dtb or a custom value. Maxime -- Maxime Ripard, Bootlin (formerly Free Electrons) Embedded Linux and Kernel engineering https://bootlin.com signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] watchdog: driver support for layerscape
Hi York, I think it's better not to affect the original i.mx SoCs. If not in i.mx SoCs, we can enable it by define CONFIG_IMX_WATCHDOG in config file. Or do you think it's better to use "select IMX_WATCHDOG" to enable it in default for our LSCH2 SoCs/platforms? Here is the patch I have changed: > diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile > index 86cf94b..ea47ccf 100644 > --- a/drivers/watchdog/Makefile > +++ b/drivers/watchdog/Makefile > @@ -7,8 +7,12 @@ > > obj-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o > obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o -ifneq (,$(filter > $(SOC), mx31 mx35 mx5 mx6 mx7 vf610 fsl-layerscape)) > +ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 mx7 vf610)) > obj-y += imx_watchdog.o > +else > +obj-$(CONFIG_IMX_WATCHDOG) += imx_watchdog.o > endif > Regards, Xiaoliang Yang -Original Message- From: York Sun Sent: 2018年6月1日 0:03 To: Xiaoliang Yang ; u-boot@lists.denx.de Subject: Re: [PATCH 1/2] watchdog: driver support for layerscape Why don't move IMX_WATCHDOG to drivers/watchdog/Kconfig and enabled this option for the selected SoCs/platforms? York ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] watchdog: driver support for layerscape
Hi York， Sure, thanks for your suggestion. I'll add IMX_WATCHDOG in Kconfig, users can enable it for the platforms they needed. I will push v2 patch later, please help to review it, thanks. Regards, Xiaoliang Yang -Original Message- From: York Sun Sent: 2018年6月1日 11:20 To: Xiaoliang Yang ; u-boot@lists.denx.de Subject: Re: [PATCH 1/2] watchdog: driver support for layerscape On 05/31/2018 08:16 PM, Xiaoliang Yang wrote: > Hi York, > > I think it's better not to affect the original i.mx SoCs. If not in i.mx > SoCs, we can enable it by define CONFIG_IMX_WATCHDOG in config file. Or do > you think it's better to use "select IMX_WATCHDOG" to enable it in default > for our LSCH2 SoCs/platforms? It is a trend to use Kconfig instead of CONFIG_ macros. If you don't convert today, make sure you make it easy to convert. If you expect this watchdog to be enabled for all LS2 platforms, you can enable it in LS2 config file. Otherwise, only enable it for the platforms you need. York ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 0/7] Improvements for the dwc3_generic driver
Hi, On 29.5.2018 14:36, Jean-Jacques Hiblot wrote: > This series aims at bringing improvements to the dwc3_generic driver so > that it can be used by most of the platforms using the dwc3 controller. > This series applies on top of the master branch of USB tree. > It also also available on github: > https://github.com/jjhiblot/u-boot/tree/dwc3_generic_v2 > > I tested this on with DRA7 and AM57x platforms for both Peripheral and Host > operations. The code to enable DM USB host & dev support for those > platforms will be submitted in a separate series. > > Enhancements: > - use separate Kconfig option for DM USB Periphal and DM USB Host. This > allow platforms to keep their non-DM USB peripheral code and use the DM > USB host. > - fixes the bind/probe confusion in dwc3_generic. The probe is done when > the USB device is first needed. > - handles PHYs when in the peripheral mode. The code to handle the PHYs is > shared with the host side > - handles clock and reset > - bind host controller to the more generic driver 'xhci-dwc3' > > > Changes in v2: > - Updated commit log > - Fixed typo in thordown.c > - select DM_USB_DEV by default for zynqmp platforms > > Jean-Jacques Hiblot (7): > usb: gadget: Do not call board_usb_xxx() directly in USB gadget > drivers > usb: introduce a separate config option for DM USB device > usb: udc: implement DM versions of > usb_gadget_initialize()/_release()/_handle_interrupt() > dwc3_generic: do not probe the USB device driver when it's bound > dwc3: move phy operation to core.c > dwc3-generic: Handle the PHYs, the clocks and the reset lines > dwc3-generic: Add select_dr_mode operation > > arch/arm/Kconfig | 2 + > cmd/fastboot.c| 4 +- > cmd/rockusb.c | 4 +- > cmd/thordown.c| 4 +- > cmd/usb_gadget_sdp.c | 4 +- > cmd/usb_mass_storage.c| 4 +- > common/dfu.c | 6 +- > drivers/usb/Kconfig | 6 ++ > drivers/usb/dwc3/Kconfig | 7 +- > drivers/usb/dwc3/core.c | 86 +++- > drivers/usb/dwc3/dwc3-generic.c | 207 > +- > drivers/usb/dwc3/ep0.c| 1 - > drivers/usb/gadget/ether.c| 38 +-- > drivers/usb/gadget/udc/udc-core.c | 44 +++- > drivers/usb/host/xhci-dwc3.c | 93 ++--- > include/dwc3-uboot.h | 7 ++ > include/linux/usb/gadget.h| 18 > 17 files changed, 351 insertions(+), 184 deletions(-) > I have tested it on zcu100 with usb stick, usb to ethernet converter and also dfu. Tested-by: Michal Simek Thanks, Michal ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [GIT PULL] Xilinx changes for v2018.07-2
Hi Tom, please pull these changes to your tree. Buildman and travis looks good https://travis-ci.org/michalsimek/u-boot/builds/386578029 Thanks, Michal The following changes since commit c3c863880479edeb5b08226e622d13c91326e4a7: add FIT data-position & data-offset property support (2018-05-26 18:19:19 -0400) are available in the Git repository at: git://www.denx.de/git/u-boot-microblaze.git tags/xilinx-for-v2018.07-2 for you to fetch changes up to a18d09ea384fb66105fbfa24fd2d1288754b8f07: fpga: zynqmp: Add secure bitstream loading for ZynqMP (2018-06-01 11:37:31 +0200) Xilinx changes for v2018.07 second pull zynqmp: - Show reset reason - Remove emulation platform - Update pmufw version - Simplify mmc bootmode - Remove dc2 useless configuration file - Cleanup mini config - Defconfig syncup - zcu100, zcu104 and zcu111 dts fixes xilinx: - Use live-tree functions in some drivers - Add support for Avnet Minized and Antminer S9 fpga: - Add secure bitstream loading support mmc: - Add hs200 mode support usb xhci: - Header fix Ezequiel Garcia (1): arm: zynq: Add support for Bitmain Antminer S9 control board Ibai Erkiaga (1): arm: zynq: Add initial support for Avnet MiniZed Michal Simek (15): usb: xhci: zynqmp: Fix header location arm64: zynqmp: Show reset reason arm64: zynqmp: Get rid of emulation platforms arm64: zynqmp: Setup the first boot_target at run time serial: zynq: Use live-tree functions mmc: zynq: Use live-tree functions watchdog: cadence: Use live-tree functions timer: cadence: Use live-tree functions arm64: zynqmp: Remove empty configuration file arm64: zynqmp: Remove CMD_UNZIP for mini configuration arm64: zynqmp: Sync defconfigs with latest Kconfig layout arm64: zynqmp: Add ina226 to zcu104 revC arm64: zynqmp: Fix address for tca6416_u97 chip on zcu104 arm64: zynqmp: Remove broken-cd from zcu100-revC arm64: zynqmp: Disable WP on zcu111 Rajan Vaja (2): soc: zynqmp: Update required API version to 1.0 arm64: zynqmp: Add TTC clocks Siva Durga Prasad Paladugu (5): mmc: sdhci: Update sdhci_send_command() to handle HS200 mmc: zynqmp: Add HS200 modes support for ZynqMP cmd: fpga: Reorder the arguments parsing code cmd: fpga: Add support to load secure bitstreams fpga: zynqmp: Add secure bitstream loading for ZynqMP arch/arm/cpu/armv8/zynqmp/clk.c | 10 +- arch/arm/cpu/armv8/zynqmp/cpu.c | 8 ++--- arch/arm/dts/Makefile| 1 + arch/arm/dts/bitmain-antminer-s9.dts | 78 arch/arm/dts/zynq-minized.dts| 106 +++ arch/arm/dts/zynqmp-clk-ccf.dtsi | 16 + arch/arm/dts/zynqmp-zcu100-revC.dts | 1 - arch/arm/dts/zynqmp-zcu104-revA.dts | 4 +-- arch/arm/dts/zynqmp-zcu104-revC.dts | 15 +--- arch/arm/dts/zynqmp-zcu111-revA.dts | 1 + arch/arm/include/asm/arch-zynqmp/hardware.h | 14 ++-- arch/arm/include/asm/arch-zynqmp/sys_proto.h | 6 board/bitmain/antminer_s9/MAINTAINERS| 6 board/bitmain/antminer_s9/Makefile | 8 + board/bitmain/antminer_s9/bitmain-antminer-s9/ps7_init_gpl.c | 280 board/bitmain/antminer_s9/board.c| 2 ++ board/xilinx/zynqmp/zynqmp.c | 88 +++-- cmd/Kconfig | 7 cmd/fpga.c | 93 +--- configs/bitmain_antminer_s9_defconfig| 66 ++ configs/xilinx_zynqmp_zc1232_revA_defconfig | 2 +- configs/xilinx_zynqmp_zc1254_revA_defconfig | 2 +- configs/xilinx_zynqmp_zc1275_revA_defconfig | 2 +- configs/xilinx_zynqmp_zc1275_revB_defconfig | 2 +- configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 + configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 3 +- configs/xilinx_zynqmp_zcu102_rev1_0_defconfig| 1 + configs/zynq_minized_defconfig | 66 ++ drivers/fpga/fpga.c
Re: [U-Boot] [PATCH 4/5] include: dma: Update the function description for dma_memcpy
Hi, On 31 May 2018 at 02:08, wrote: > From: Tien Fong Chee > > Update the dma_memcpy description on return argument for DMA330 driver. > > Signed-off-by: Tien Fong Chee > --- > include/dma.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/include/dma.h b/include/dma.h > index 0a0c9dd..b825c1e 100644 > --- a/include/dma.h > +++ b/include/dma.h > @@ -79,8 +79,8 @@ int dma_get_device(u32 transfer_type, struct udevice > **devp); > * @dst - destination pointer > * @src - souce pointer > * @len - data length to be copied > - * @return - on successful transfer returns no of bytes > -transferred and on failure return error code. > + * @return - on successful transfer returns no of bytes or zero(for DMA330) > + * transferred and on failure return error code. This is a public API so you cannot change it just for one device. You can change the API for everyone if you like. But why would it want to return 0? > */ > int dma_memcpy(struct udevice *dev, void *dst, void *src, size_t len); > > -- > 2.2.0 > Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 5/5] arm: dts: socfpga: stratix10: update pdma
On 31 May 2018 at 02:08, wrote: > From: Tien Fong Chee > > Update pdma properties for Stratix 10 > > Signed-off-by: Tien Fong Chee > --- > arch/arm/dts/socfpga_stratix10.dtsi | 20 > 1 file changed, 20 insertions(+) Reviewed-by: Simon Glass Is there a DT binding file for this somewhere? ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3] board: sun50i: Add Amarula A64-Relic initial support
On Thu, May 31, 2018 at 03:13:15PM +0530, Jagan Teki wrote: > On Thu, May 31, 2018 at 3:07 PM, Maxime Ripard > wrote: > > On Tue, May 29, 2018 at 09:50:39PM +0530, Jagan Teki wrote: > >> On Tue, May 29, 2018 at 9:44 PM, Maxime Ripard > >> wrote: > >> > On Mon, May 28, 2018 at 04:34:43PM +0530, Jagan Teki wrote: > >> >> +CONFIG_CMD_USB_MASS_STORAGE=y > >> > > >> > You still haven't explained why this is useful to add it by default on > >> > this particular board. > >> > >> This board does have only eMMC and no external storage > >> possibilities(like eMMC or Ethernet) so to copy images between eMMC vs > >> host intermediate way (other than fastboot) ums can be the possible > >> way. > > > > We have fastboot and DFU to address that already, and a number of > > other boards accomodate that just fine (the CHIP, the NES Classic, > > etc.). > > Yes, but ums is different where we can simply mount the flash on host > and update the partitions data directly instead of create partitions > with new data to write again. what's wrong with using ums. I always > believe fastboot, DFU is different than ums where former need to > create image file and later simply copy. I'm not arguing the usefulness of the UMS gadget itself, I don't have any objections to that, and I totally get why and how it can be useful. What I'm arguing for is why you should enable it *by default*. You can very easily do that with menuconfig already, and we won't enable each and every command and feature someone finds interesting. We've already been bitten hard by this, and I have no intention of doing that kind of thing a second time. So yeah, you can definitely use UMS if you wish so. But enabling it by default when we have already two alternatives for the same use case enabled is pointless. Maxime -- Maxime Ripard, Bootlin (formerly Free Electrons) Embedded Linux and Kernel engineering https://bootlin.com signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/3] cmd: fpga: Reorder the arguments parsing code
On 31.5.2018 11:40, Siva Durga Prasad Paladugu wrote:
> This patch modifies the arguments parsing code by parsing
> based on requested operation for fpga loadfs and then
> parses the most common/basic args for other fpga load
> commands. This makes it easy for new command extensions
> or additions especially the commands with more args.
>
> Signed-off-by: Siva Durga Prasad Paladugu
> ---
> Changes for v2:
> - Correct the argc check as per comment.
> ---
> cmd/fpga.c | 31 +++
> 1 file changed, 19 insertions(+), 12 deletions(-)
>
> diff --git a/cmd/fpga.c b/cmd/fpga.c
> index 14ad4e5..3f09d42 100644
> --- a/cmd/fpga.c
> +++ b/cmd/fpga.c
> @@ -60,15 +60,31 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char
> *const argv[])
> if (datastr)
> fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
>
> - switch (argc) {
> + if (argc > 9 || argc < 2) {
> + debug("%s: Too many or too few args (%d)\n", __func__, argc);
> + return CMD_RET_USAGE;
> + }
> +
> + op = (int)fpga_get_op(argv[1]);
> +
> + switch (op) {
> #if defined(CONFIG_CMD_FPGA_LOADFS)
> - case 9:
> + case FPGA_LOADFS:
> + if (argc < 9)
> + return CMD_RET_USAGE;
> fpga_fsinfo.blocksize = (unsigned int)
> - simple_strtoul(argv[5], NULL, 16);
> + simple_strtoul(argv[5], NULL, 16);
> fpga_fsinfo.interface = argv[6];
> fpga_fsinfo.dev_part = argv[7];
> fpga_fsinfo.filename = argv[8];
> + argc = 5;
> + break;
> #endif
> + default:
> + break;
> + }
> +
> + switch (argc) {
> case 5: /* fpga */
> data_size = simple_strtoul(argv[4], NULL, 16);
>
> @@ -117,15 +133,6 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char
> *const argv[])
> __func__, (ulong)fpga_data);
> dev = FPGA_INVALID_DEVICE; /* reset device num */
> }
> -
> - case 2: /* fpga */
> - op = (int)fpga_get_op(argv[1]);
> - break;
> -
> - default:
> - debug("%s: Too many or too few args (%d)\n", __func__, argc);
> - op = FPGA_NONE; /* force usage display */
> - break;
> }
>
> if (dev == FPGA_INVALID_DEVICE) {
>
Applied all.
Thanks,
Michal
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Re: [U-Boot] [PATCH 00/12] binman: A few more features
Hi Tom,
On 28 May 2018 at 13:17, Tom Rini wrote:
> On Sat, May 26, 2018 at 04:18:45PM -0600, Simon Glass wrote:
>> Hi,
>>
>> On 15 May 2018 at 19:52, Simon Glass wrote:
>> > This series ads a few more features to binman, principally the ability to
>> > nest entries within other entries, to form hierarchical images.
>> >
>> > Also included are support for a map file and some docs tidy-ups.
>> >
>> >
>> > Simon Glass (12):
>> > binman: Allow unit addresses for binaries
>> > binman: Refactor much of the image code into 'section'
>> > binman: Rename ELF parameters to 'section'
>> > binman: Rename Entry property to 'section'
>> > binman: Avoid setting sys.path globally
>> > binman: Add support for sections
>> > binman: Add documentation for pos-unset property
>> > binman: Allow a single test to be executed
>> > binman: Tidy up some docs and comments
>> > binman: Add support for outputing a map file
>> > binman: Add support for adding a name prefix to entries
>> > binman: Mark 'align-end' as implemented
>> >
>> > tools/binman/README | 89 -
>> > tools/binman/binman.py| 24 +-
>> > tools/binman/bsection.py | 318 ++
>> > tools/binman/cmdline.py | 2 +
>> > tools/binman/control.py | 2 +
>> > tools/binman/elf.py | 10 +-
>> > tools/binman/elf_test.py | 28 +-
>> > tools/binman/{etype => }/entry.py | 74 +++-
>> > tools/binman/etype/_testing.py| 4 +-
>> > tools/binman/etype/blob.py| 4 +-
>> > tools/binman/etype/intel_cmc.py | 4 +-
>> > tools/binman/etype/intel_descriptor.py| 4 +-
>> > tools/binman/etype/intel_fsp.py | 4 +-
>> > tools/binman/etype/intel_me.py| 4 +-
>> > tools/binman/etype/intel_mrc.py | 4 +-
>> > tools/binman/etype/intel_vbt.py | 4 +-
>> > tools/binman/etype/intel_vga.py | 4 +-
>> > tools/binman/etype/section.py | 60
>> > tools/binman/etype/u_boot.py | 4 +-
>> > tools/binman/etype/u_boot_dtb.py | 4 +-
>> > tools/binman/etype/u_boot_dtb_with_ucode.py | 12 +-
>> > tools/binman/etype/u_boot_img.py | 4 +-
>> > tools/binman/etype/u_boot_nodtb.py| 4 +-
>> > tools/binman/etype/u_boot_spl.py | 8 +-
>> > tools/binman/etype/u_boot_spl_bss_pad.py | 4 +-
>> > tools/binman/etype/u_boot_spl_dtb.py | 4 +-
>> > tools/binman/etype/u_boot_spl_nodtb.py| 4 +-
>> > .../binman/etype/u_boot_spl_with_ucode_ptr.py | 4 +-
>> > tools/binman/etype/u_boot_ucode.py| 14 +-
>> > tools/binman/etype/u_boot_with_ucode_ptr.py | 20 +-
>> > tools/binman/etype/x86_start16.py | 4 +-
>> > tools/binman/etype/x86_start16_spl.py | 4 +-
>> > tools/binman/ftest.py | 98 --
>> > tools/binman/image.py | 262 ++-
>> > tools/binman/image_test.py| 18 +-
>> > tools/binman/test/54_unit_address.dts | 13 +
>> > tools/binman/test/55_sections.dts | 26 ++
>> > tools/binman/test/56_name_prefix.dts | 28 ++
>> > 38 files changed, 810 insertions(+), 372 deletions(-)
>> > create mode 100644 tools/binman/bsection.py
>> > rename tools/binman/{etype => }/entry.py (75%)
>> > create mode 100644 tools/binman/etype/section.py
>> > create mode 100644 tools/binman/test/54_unit_address.dts
>> > create mode 100644 tools/binman/test/55_sections.dts
>> > create mode 100644 tools/binman/test/56_name_prefix.dts
>>
>> Any comments on this one please?
>
> Makes sense to me. I think you have one or two new files where the SPDX
> tags need to be moved to the first / first-possible line. And I'd
> really like to see automating the coverage tests ;)
OK I'll take a look at the SPDX problems. For me the coverage stuff
works, so we''ll have to figure that out.
Regards,
Simon
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Re: [U-Boot] [PATCH v2 1/2] watchdog: driver support for fsl-lsch2
On 06/01/2018 12:37 AM, Xiaoliang Yang wrote: > Support watchdog driver for fsl-lsch2. If you want to use it, > please enable CONFIG_IMX_WATCHDOG, and CONFIG_HW_WATCHDOG. > define CONFIG_WATCHDOG_TIMEOUT_MSECS to set watchdog timeout. > > Signed-off-by: Xiaoliang Yang > --- > arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2 | 10 ++ > drivers/watchdog/Kconfig |6 ++ > drivers/watchdog/Makefile |2 ++ > drivers/watchdog/imx_watchdog.c| 11 +++ > 4 files changed, 29 insertions(+), 0 deletions(-) > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2 > b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2 > index a6ef830..87b91eb 100644 > --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2 > +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2 > @@ -8,3 +8,13 @@ Freescale LayerScape with Chassis Generation 2 > > This architecture supports Freescale ARMv8 SoCs with Chassis generation 2, > for example LS1043A. > + > +Watchdog support Overview > +--- > +Support watchdog driver for Layerscape. Use following configs to enable it: > +#define CONFIG_IMX_WATCHDOG > +#define CONFIG_HW_WATCHDOG > +Use following config to set watchdog timeout, if this config is not defined, > +the default timeout value is 128s which is the maximum. Set 10 seconds for > +example: > +#define CONFIG_WATCHDOG_TIMEOUT_MSECS 1 > diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig > index 148c6a0..a526afd 100644 > --- a/drivers/watchdog/Kconfig > +++ b/drivers/watchdog/Kconfig > @@ -103,4 +103,10 @@ config WDT_CDNS > Select this to enable Cadence watchdog timer, which can be found on > some > Xilinx Microzed Platform. > > +config IMX_WATCHDOG > + bool "IMX watchdog timer support" > + help > +Select this to enable IMX watchdog timer, which can be found on > +some i.mx and fsl-lsch2 SoCs. > + > endmenu > diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile > index f405f51..159fc11 100644 > --- a/drivers/watchdog/Makefile > +++ b/drivers/watchdog/Makefile > @@ -7,6 +7,8 @@ obj-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o > obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o > ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 mx7 vf610)) > obj-y += imx_watchdog.o > +else > +obj-$(CONFIG_IMX_WATCHDOG) += imx_watchdog.o It is good to see you convert this macro to Kconfig option. But it is not right to mix these two. You should create a patch before this one to convert this macro to Kconfig (and remove it from whitelist). It shouldn't be hard, I only see 7 files defining this macro. Please make sure you CC maintainers for the Kconfig change. > endif > obj-$(CONFIG_S5P) += s5p_wdt.o > obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o > diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c > index 3f826d1..3ad4e55 100644 > --- a/drivers/watchdog/imx_watchdog.c > +++ b/drivers/watchdog/imx_watchdog.c > @@ -8,6 +8,13 @@ > #include > #include > #include > +#ifdef CONFIG_FSL_LAYERSCAPE > +#ifdef CONFIG_FSL_LSCH3 > +#include You said LSCH3 doesn't support this watchdog. York ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 3/4] serial: ns16550: Add reset ctrl to driver
On 1 June 2018 at 02:45, Ley Foon Tan wrote:
> Add code to reset all reset signals as in serial DT node. A reset property is
> an optional feature,
> so do not fail if a reset property is not present.
>
> If a reset property is discovered, then use it to deassert, thus bringing the
> IP out of reset.
>
> Signed-off-by: Ley Foon Tan
> Reviewed-by: Marek Vasut
> ---
> drivers/serial/ns16550.c | 8
> 1 file changed, 8 insertions(+)
>
Reviewed-by: Simon Glass
> diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
> index 53550bf..9c80090 100644
> --- a/drivers/serial/ns16550.c
> +++ b/drivers/serial/ns16550.c
> @@ -9,6 +9,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -177,6 +178,7 @@ void NS16550_init(NS16550_t com_port, int baud_divisor)
> #if defined(CONFIG_ARCH_OMAP2PLUS)
> serial_out(0x7, _port->mdr1); /* mode select reset
> TL16C750*/
> #endif
> +
Unrelated change?
> serial_out(UART_MCRVAL, _port->mcr);
> serial_out(ns16550_getfcr(com_port), _port->fcr);
> if (baud_divisor != -1)
> @@ -370,6 +372,12 @@ static int ns16550_serial_setbrg(struct udevice *dev,
> int baudrate)
> int ns16550_serial_probe(struct udevice *dev)
> {
> struct NS16550 *const com_port = dev_get_priv(dev);
> + struct reset_ctl_bulk reset_bulk;
> + int ret;
> +
> + ret = reset_get_bulk(dev, _bulk);
> + if (!ret)
> + reset_deassert_bulk(_bulk);
>
> com_port->plat = dev_get_platdata(dev);
> NS16550_init(com_port, -1);
> --
> 2.2.2
>
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Re: [U-Boot] [RFC][DO NOT APPLY] binman: Switch to 'python-coverage'
Hi Tom, On 26 May 2018 at 11:06, Tom Rini wrote: > The most portable way to get access to coverage is to invoke it as > 'python-coverage'. > > Cc: Simon Glass > Signed-off-by: Tom Rini > --- > So, here's the set of problems I have. First, running 'pip install > coverage' doesn't get me a 'coverage' binary, so I've just never made > good use of 'make tests' and so never have these run. It also means > they aren't strictly in travis-ci, so they're never run automatically. > With this patch, make tests executes for me, and now fails noting that a > lot of things don't have coverage. I'm honestly not sure what the best > path forward here is. > --- > tools/binman/README| 3 +-- > tools/binman/binman.py | 4 ++-- > 2 files changed, 3 insertions(+), 4 deletions(-) > Reviewed-by: Simon Glass For me this patch works fine. The -T option works correctly. Typing 'python-coverage html' produces this report: https://pste.eu/p/NI7q.html Note that your patch needs to update this line too: print "Type 'coverage html' to get a report in htmlcov/index.html" Can you send me the output you see? Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 4/4] net: designware: Add reset ctrl to driver
On 1 June 2018 at 02:45, Ley Foon Tan wrote: > Add code to reset all reset signals as in Ethernet DT node. A reset property > is an optional feature, > so only print out a warning and do not fail if a reset property is not > present. > > If a reset property is discovered, then use it to deassert, thus bringing the > IP out of reset. > > Signed-off-by: Ley Foon Tan > --- > drivers/net/designware.c | 8 > 1 file changed, 8 insertions(+) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 1/4] include: reset: check CONFIG_SPL_RESET_SUPPORT
Hi,
On 1 June 2018 at 02:45, Ley Foon Tan wrote:
> Add checking for CONFIG_SPL_RESET_SUPPORT to fix compilation error when
> CONFIG_DM_RESET is enabled but CONFIG_SPL_RESET_SUPPORT is disabled in SPL
> build.
>
> Signed-off-by: Ley Foon Tan
> ---
> include/reset.h | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/include/reset.h b/include/reset.h
> index 201bafc..0ac0a47 100644
> --- a/include/reset.h
> +++ b/include/reset.h
> @@ -77,7 +77,8 @@ struct reset_ctl_bulk {
> unsigned int count;
> };
>
> -#ifdef CONFIG_DM_RESET
> +#if (!defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM_RESET)) ||\
> +(defined(CONFIG_SPL_RESET_SUPPORT) && defined(CONFIG_DM_RESET))
CONFIG_SPL_RESET_SUPPORT should move to Kconfig
Also it should be renamed to CONFIG_SPL_DM_RESET
so that you can use:
#if CONFIG_IS_ENABLED(DM_RESET)
> /**
> * reset_get_by_index - Get/request a reset signal by integer index.
> *
> --
> 2.2.2
>
Regards,
Simon
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Re: [U-Boot] [PATCH v4 2/4] mmc: dwmmc: socfpga: Add reset ctrl to driver
On 1 June 2018 at 02:45, Ley Foon Tan wrote: > Add code to reset all reset signals as in mmc DT node. A reset property is an > optional feature, > so only print out a warning and do not fail if a reset property is not > present. > > If a reset property is discovered, then use it to deassert, thus bringing the > IP out of reset. > > Signed-off-by: Ley Foon Tan > --- > drivers/mmc/socfpga_dw_mmc.c | 17 + > 1 file changed, 17 insertions(+) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/5] drivers: dma: Enable DMA-330 driver support
Hi Tien,
On 31 May 2018 at 02:08, wrote:
> From: Tien Fong Chee
>
> Enable DMAC driver support for DMA-330 controller.
> The driver is also compatible to PL330 product.
>
> Signed-off-by: Tien Fong Chee
> ---
> drivers/dma/Kconfig |9 +-
> drivers/dma/Makefile |1 +
> drivers/dma/dma330.c | 1514
> ++
> include/dma330.h | 136 +
> 4 files changed, 1659 insertions(+), 1 deletion(-)
> create mode 100644 drivers/dma/dma330.c
> create mode 100644 include/dma330.h
>
> diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
> index 4ee6afa..6e77e07 100644
> --- a/drivers/dma/Kconfig
> +++ b/drivers/dma/Kconfig
> @@ -2,7 +2,7 @@ menu "DMA Support"
>
> config DMA
> bool "Enable Driver Model for DMA drivers"
> - depends on DM
> + depends on DM || SPL_DM
> help
> Enable driver model for DMA. DMA engines can do
> asynchronous data transfers without involving the host
> @@ -34,4 +34,11 @@ config APBH_DMA_BURST8
>
> endif
>
> +config DMA330_DMA
> + bool "PL330/DMA-330 DMA Controller(DMAC) driver"
> + depends on DMA
> + help
> +Enable the DMA controller driver for both PL330 and
> +DMA-330 products.
> +
> endmenu # menu "DMA Support"
> diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
> index 4eaef8a..bfad0dd 100644
> --- a/drivers/dma/Makefile
> +++ b/drivers/dma/Makefile
> @@ -11,3 +11,4 @@ obj-$(CONFIG_FSL_DMA) += fsl_dma.o
> obj-$(CONFIG_TI_KSNAV) += keystone_nav.o keystone_nav_cfg.o
> obj-$(CONFIG_TI_EDMA3) += ti-edma3.o
> obj-$(CONFIG_DMA_LPC32XX) += lpc32xx_dma.o
> +obj-$(CONFIG_DMA330_DMA) += dma330.o
> diff --git a/drivers/dma/dma330.c b/drivers/dma/dma330.c
> new file mode 100644
> index 000..66575d8
> --- /dev/null
> +++ b/drivers/dma/dma330.c
> @@ -0,0 +1,1514 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2018 Intel Corporation
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +/* Register and Bit field Definitions */
> +
> +/* DMA Status */
> +#define DS 0x0
> +#define DS_ST_STOP 0x0
> +#define DS_ST_EXEC 0x1
> +#define DS_ST_CMISS0x2
> +#define DS_ST_UPDTPC 0x3
> +#define DS_ST_WFE 0x4
> +#define DS_ST_ATBRR0x5
> +#define DS_ST_QBUSY0x6
> +#define DS_ST_WFP 0x7
> +#define DS_ST_KILL 0x8
> +#define DS_ST_CMPLT0x9
> +#define DS_ST_FLTCMP 0xe
> +#define DS_ST_FAULT0xf
It is possible to use enum for some of these?
enum {
DS = 0,
DS_ST_STOP,
...
}
> +
> +/* DMA Program Count register */
> +#define DPC0x4
> +/* Interrupt Enable register */
> +#define INTEN 0x20
> +/* event-Interrupt Raw Status register */
> +#define ES 0x24
> +/* Interrupt Status register */
> +#define INTSTATUS 0x28
> +/* Interrupt Clear register */
> +#define INTCLR 0x2c
> +/* Fault Status DMA Manager register */
> +#define FSM0x30
> +/* Fault Status DMA Channel register */
> +#define FSC0x34
> +/* Fault Type DMA Manager register */
> +#define FTM0x38
> +
> +/* Fault Type DMA Channel register */
> +#define _FTC 0x40
> +#define FTC(n) (_FTC + (n) * 0x4)
> +
> +/* Channel Status register */
> +#define _CS0x100
> +#define CS(n) (_CS + (n) * 0x8)
> +#define CS_CNS BIT(21)
> +
> +/* Channel Program Counter register */
> +#define _CPC 0x104
> +#define CPC(n) (_CPC + (n) * 0x8)
> +
> +/* Source Address register */
> +#define _SA0x400
> +#define SA(n) (_SA + (n) * 0x20)
> +
> +/* Destination Address register */
> +#define _DA0x404
> +#define DA(n) (_DA + (n) * 0x20)
> +
> +/* Channel Control register */
> +#define _CC0x408
> +#define CC(n) (_CC + (n) * 0x20)
> +
> +/* Channel Control register (CCR) Setting */
> +#define CC_SRCINC BIT(0)
> +#define CC_DSTINC BIT(14)
> +#define CC_SRCPRI BIT(8)
> +#define CC_DSTPRI BIT(22)
> +#define CC_SRCNS BIT(9)
> +#define CC_DSTNS BIT(23)
> +#define CC_SRCIA BIT(10)
> +#define CC_DSTIA BIT(24)
> +#define CC_SRCBRSTLEN_SHFT 4
> +#define CC_DSTBRSTLEN_SHFT 18
> +#define CC_SRCBRSTSIZE_SHFT1
> +#define CC_DSTBRSTSIZE_SHFT15
> +#define CC_SRCCCTRL_SHFT 11
> +#define CC_SRCCCTRL_MASK 0x7
Can you make the mask a shifted mask? Then it is easier to use in
clrsetbits_le32(), for example.
e.g.
#define CC_SRCCCTRL_MASK (7 << CC_SRCCCTRL_SHFT)
> +#define CC_DSTCCTRL_SHFT 25
>
Re: [U-Boot] [PATCH] power: regulator: denied disable on always-on regulator
On 31 May 2018 at 01:57, Patrice Chotard wrote: > From: Patrick Delaunay > > Don't disable regulator which are tagged as "regulator-always-on" in DT. > > Signed-off-by: Patrick Delaunay > Signed-off-by: Patrice Chotard > --- > > drivers/power/regulator/regulator-uclass.c | 5 + > 1 file changed, 5 insertions(+) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/5] drivers: dma: Add function to zeroes a range of destination such as memory
Hi Tien,
On 31 May 2018 at 02:08, wrote:
> From: Tien Fong Chee
>
> This new DMA class function enables DMA being used for initializing
> a range of destination such as memory to zeros. This is quite useful to
> help accelerating the performance in scrubbing memory when ECC is enabled.
>
> Signed-off-by: Tien Fong Chee
> ---
> drivers/dma/dma-uclass.c | 15 +++
> include/dma.h| 12
> 2 files changed, 27 insertions(+)
>
> diff --git a/drivers/dma/dma-uclass.c b/drivers/dma/dma-uclass.c
> index a33f7d5..cb83c24 100644
> --- a/drivers/dma/dma-uclass.c
> +++ b/drivers/dma/dma-uclass.c
> @@ -61,6 +61,21 @@ int dma_memcpy(void *dst, void *src, size_t len)
> return ops->transfer(dev, DMA_MEM_TO_MEM, dst, src, len);
> }
>
> +int dma_memcpy_zeroes(struct udevice *dev, void *dst, size_t len)
> +{
> + const struct dma_ops *ops;
> +
> + ops = device_get_ops(dev);
> + if (!ops->transfer_zeroes)
> + return -ENOSYS;
> +
> + /* Invalidate the area, so no writeback into the RAM races with DMA */
> + invalidate_dcache_range((unsigned long)dst, (unsigned long)dst +
> + roundup(len, ARCH_DMA_MINALIGN));
> +
> + return ops->transfer_zeroes(dev, dst, len);
> +}
> +
> UCLASS_DRIVER(dma) = {
> .id = UCLASS_DMA,
> .name = "dma",
> diff --git a/include/dma.h b/include/dma.h
> index 50e9652..6bad2264 100644
> --- a/include/dma.h
> +++ b/include/dma.h
> @@ -46,6 +46,7 @@ struct dma_ops {
> */
> int (*transfer)(struct udevice *dev, int direction, void *dst,
> void *src, size_t len);
> + int (*transfer_zeroes)(struct udevice *dev, void *dst, size_t len);
I wonder if this could be done by using transfer() with a src of NULL ?
> };
>
> /*
> @@ -82,4 +83,15 @@ int dma_get_device(u32 transfer_type, struct udevice
> **devp);
> */
> int dma_memcpy(void *dst, void *src, size_t len);
>
> +/*
> + * dma_memcpy_zeroes - Fill up destination with zeros through DMA.
> + *
> + * @dev: The DMA device
> + * @dst: destination pointer
> + * @len: length to be copied with zero
> + * @return: on successful transfer returns zero.
> + * on failure returns error code.
> + */
> +int dma_memcpy_zeroes(struct udevice *dev, void *dst, size_t len);
> +
> #endif /* _DMA_H_ */
> --
> 2.2.0
>
Regards,
Simon
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Re: [U-Boot] [PATCH 3/5] drivers: dma: Factor out dma_get_device from DMA class function
On 31 May 2018 at 02:08, wrote: > From: Tien Fong Chee > > Factor out the dma_get_device from DMA class function so caller can > set some configuration and changes on the DMA device structure which > is return by calling dma_get_device before device instance is processed by > DMA class functions. > > Signed-off-by: Tien Fong Chee > --- > drivers/dma/dma-uclass.c| 8 +--- > drivers/mtd/spi/spi_flash.c | 9 - > include/dma.h | 3 ++- > 3 files changed, 11 insertions(+), 9 deletions(-) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 00/12] binman: A few more features
This series ads a few more features to binman, principally the ability to
nest entries within other entries, to form hierarchical images.
Also included are support for a map file and some docs tidy-ups.
Changes in v2:
- Add SPDX tag to .dts file
- Put SPDX on the first line in bsection.py
Simon Glass (12):
binman: Allow unit addresses for binaries
binman: Refactor much of the image code into 'section'
binman: Rename ELF parameters to 'section'
binman: Rename Entry property to 'section'
binman: Avoid setting sys.path globally
binman: Add support for sections
binman: Add documentation for pos-unset property
binman: Allow a single test to be executed
binman: Tidy up some docs and comments
binman: Add support for outputing a map file
binman: Add support for adding a name prefix to entries
binman: Mark 'align-end' as implemented
tools/binman/README | 89 -
tools/binman/binman.py| 24 +-
tools/binman/bsection.py | 318 ++
tools/binman/cmdline.py | 2 +
tools/binman/control.py | 2 +
tools/binman/elf.py | 10 +-
tools/binman/elf_test.py | 28 +-
tools/binman/{etype => }/entry.py | 74 +++-
tools/binman/etype/_testing.py| 4 +-
tools/binman/etype/blob.py| 4 +-
tools/binman/etype/intel_cmc.py | 4 +-
tools/binman/etype/intel_descriptor.py| 4 +-
tools/binman/etype/intel_fsp.py | 4 +-
tools/binman/etype/intel_me.py| 4 +-
tools/binman/etype/intel_mrc.py | 4 +-
tools/binman/etype/intel_vbt.py | 4 +-
tools/binman/etype/intel_vga.py | 4 +-
tools/binman/etype/section.py | 59
tools/binman/etype/u_boot.py | 4 +-
tools/binman/etype/u_boot_dtb.py | 4 +-
tools/binman/etype/u_boot_dtb_with_ucode.py | 12 +-
tools/binman/etype/u_boot_img.py | 4 +-
tools/binman/etype/u_boot_nodtb.py| 4 +-
tools/binman/etype/u_boot_spl.py | 8 +-
tools/binman/etype/u_boot_spl_bss_pad.py | 4 +-
tools/binman/etype/u_boot_spl_dtb.py | 4 +-
tools/binman/etype/u_boot_spl_nodtb.py| 4 +-
.../binman/etype/u_boot_spl_with_ucode_ptr.py | 4 +-
tools/binman/etype/u_boot_ucode.py| 14 +-
tools/binman/etype/u_boot_with_ucode_ptr.py | 20 +-
tools/binman/etype/x86_start16.py | 4 +-
tools/binman/etype/x86_start16_spl.py | 4 +-
tools/binman/ftest.py | 98 --
tools/binman/image.py | 262 ++-
tools/binman/image_test.py| 18 +-
tools/binman/test/54_unit_address.dts | 15 +
tools/binman/test/55_sections.dts | 28 ++
tools/binman/test/56_name_prefix.dts | 30 ++
38 files changed, 815 insertions(+), 372 deletions(-)
create mode 100644 tools/binman/bsection.py
rename tools/binman/{etype => }/entry.py (75%)
create mode 100644 tools/binman/etype/section.py
create mode 100644 tools/binman/test/54_unit_address.dts
create mode 100644 tools/binman/test/55_sections.dts
create mode 100644 tools/binman/test/56_name_prefix.dts
--
2.17.0.921.gf22659ad46-goog
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[U-Boot] [PATCH v2 04/12] binman: Rename Entry property to 'section'
Entries are now passed a Section object rather than an Image. Rename this
property to avoid confusion.
Signed-off-by: Simon Glass
---
Changes in v2: None
tools/binman/etype/_testing.py| 4 ++--
tools/binman/etype/blob.py| 4 ++--
tools/binman/etype/entry.py | 24 +--
tools/binman/etype/intel_cmc.py | 4 ++--
tools/binman/etype/intel_descriptor.py| 4 ++--
tools/binman/etype/intel_fsp.py | 4 ++--
tools/binman/etype/intel_me.py| 4 ++--
tools/binman/etype/intel_mrc.py | 4 ++--
tools/binman/etype/intel_vbt.py | 4 ++--
tools/binman/etype/intel_vga.py | 4 ++--
tools/binman/etype/u_boot.py | 4 ++--
tools/binman/etype/u_boot_dtb.py | 4 ++--
tools/binman/etype/u_boot_dtb_with_ucode.py | 12 ++
tools/binman/etype/u_boot_img.py | 4 ++--
tools/binman/etype/u_boot_nodtb.py| 4 ++--
tools/binman/etype/u_boot_spl.py | 4 ++--
tools/binman/etype/u_boot_spl_bss_pad.py | 4 ++--
tools/binman/etype/u_boot_spl_dtb.py | 4 ++--
tools/binman/etype/u_boot_spl_nodtb.py| 4 ++--
.../binman/etype/u_boot_spl_with_ucode_ptr.py | 4 ++--
tools/binman/etype/u_boot_ucode.py| 14 +--
tools/binman/etype/u_boot_with_ucode_ptr.py | 20
tools/binman/etype/x86_start16.py | 4 ++--
tools/binman/etype/x86_start16_spl.py | 4 ++--
tools/binman/ftest.py | 2 +-
25 files changed, 77 insertions(+), 75 deletions(-)
diff --git a/tools/binman/etype/_testing.py b/tools/binman/etype/_testing.py
index b166a71c4a9..c376dd5c9ca 100644
--- a/tools/binman/etype/_testing.py
+++ b/tools/binman/etype/_testing.py
@@ -10,8 +10,8 @@ import fdt_util
import tools
class Entry__testing(Entry):
-def __init__(self, image, etype, node):
-Entry.__init__(self, image, etype, node)
+def __init__(self, section, etype, node):
+Entry.__init__(self, section, etype, node)
def ObtainContents(self):
self.data = 'a'
diff --git a/tools/binman/etype/blob.py b/tools/binman/etype/blob.py
index 10e59e980d6..16b1e5f64d9 100644
--- a/tools/binman/etype/blob.py
+++ b/tools/binman/etype/blob.py
@@ -10,8 +10,8 @@ import fdt_util
import tools
class Entry_blob(Entry):
-def __init__(self, image, etype, node):
-Entry.__init__(self, image, etype, node)
+def __init__(self, section, etype, node):
+Entry.__init__(self, section, etype, node)
self._filename = fdt_util.GetString(self._node, "filename", self.etype)
def ObtainContents(self):
diff --git a/tools/binman/etype/entry.py b/tools/binman/etype/entry.py
index 39da7f86022..cbcabe20582 100644
--- a/tools/binman/etype/entry.py
+++ b/tools/binman/etype/entry.py
@@ -19,10 +19,10 @@ import tools
modules = {}
class Entry(object):
-"""An Entry in the image
+"""An Entry in the section
An entry corresponds to a single node in the device-tree description
-of the image. Each entry ends up being a part of the final image.
+of the section. Each entry ends up being a part of the final section.
Entries can be placed either right next to each other, or with padding
between them. The type of the entry determines the data that is in it.
@@ -30,9 +30,9 @@ class Entry(object):
Entry.
Attributes:
-image: The image containing this entry
+section: The section containing this entry
node: The node that created this entry
-pos: Absolute position of entry within the image, None if not known
+pos: Absolute position of entry within the section, None if not known
size: Entry size in bytes, None if not known
contents_size: Size of contents in bytes, 0 by default
align: Entry start position alignment, or None
@@ -42,8 +42,8 @@ class Entry(object):
pad_after: Number of pad bytes after the contents, 0 if none
data: Contents of entry (string of bytes)
"""
-def __init__(self, image, etype, node, read_node=True):
-self.image = image
+def __init__(self, section, etype, node, read_node=True):
+self.section = section
self.etype = etype
self._node = node
self.pos = None
@@ -59,11 +59,11 @@ class Entry(object):
self.ReadNode()
@staticmethod
-def Create(image, node, etype=None):
+def Create(section, node, etype=None):
"""Create a new entry for a node.
Args:
-image: Image object containing this node
+section: Image object containing this node
node: Node object containing information about the entry to
create
etype: Entry type to use, or None to work it out (used for tests)
@@ -94,7 +94,7 @@ class Entry(object):
# Call its
[U-Boot] [PATCH v2 06/12] binman: Add support for sections
It is useful to be able to split an image into multiple sections,
each with its own size and position, for cases where a flash device has
read-only and read-write portions.
Add support for this.
Signed-off-by: Simon Glass
---
Changes in v2:
- Add SPDX tag to .dts file
tools/binman/README | 41 +++--
tools/binman/bsection.py | 1 +
tools/binman/entry.py | 9 ++
tools/binman/etype/section.py | 50 +++
tools/binman/ftest.py | 5
tools/binman/test/55_sections.dts | 28 +
6 files changed, 132 insertions(+), 2 deletions(-)
create mode 100644 tools/binman/etype/section.py
create mode 100644 tools/binman/test/55_sections.dts
diff --git a/tools/binman/README b/tools/binman/README
index 196dda1fb4c..5ef1246f296 100644
--- a/tools/binman/README
+++ b/tools/binman/README
@@ -392,6 +392,45 @@ either by using a unit number suffix (u-boot@0, u-boot@1)
or by using a
different name for each and specifying the type with the 'type' attribute.
+Sections and hiearchical images
+---
+
+Sometimes it is convenient to split an image into several pieces, each of which
+contains its own set of binaries. An example is a flash device where part of
+the image is read-only and part is read-write. We can set up sections for each
+of these, and place binaries in them independently. The image is still produced
+as a single output file.
+
+This feature provides a way of creating hierarchical images. For example here
+is an example with two copies of U-Boot. One is read-only (ro), intended to be
+written only in the factory. Another is read-write (rw), so that it can be
+upgraded in the field. The sizes are fixed so that the ro/rw boundary is known
+and can be programmed:
+
+ binman {
+ section@0 {
+ read-only;
+ size = <0x10>;
+ u-boot {
+ };
+ };
+ section@1 {
+ size = <0x10>;
+ u-boot {
+ };
+ };
+ };
+
+This image could be placed into a SPI flash chip, with the protection boundary
+set at 1MB.
+
+A few special properties are provided for sections:
+
+read-only:
+ Indicates that this section is read-only. This has no impact on binman's
+ operation, but his property can be read at run time.
+
+
Special properties
--
@@ -586,8 +625,6 @@ Some ideas:
- Allow easy building of images by specifying just the board name
- Produce a full Python binding for libfdt (for upstream)
- Add an option to decode an image into the constituent binaries
-- Suppoort hierarchical images (packing of binaries into another binary
- which is then placed in the image)
- Support building an image for a board (-b) more completely, with a
configurable build directory
- Consider making binman work with buildman, although if it is used in the
diff --git a/tools/binman/bsection.py b/tools/binman/bsection.py
index 07c72d34c43..331f806d9ab 100644
--- a/tools/binman/bsection.py
+++ b/tools/binman/bsection.py
@@ -201,6 +201,7 @@ class Section(object):
pos = 0
prev_name = 'None'
for entry in self._entries.values():
+entry.CheckPosition()
if (entry.pos < self._skip_at_start or
entry.pos >= self._skip_at_start + self._size):
entry.Raise("Position %#x (%d) is outside the section starting
"
diff --git a/tools/binman/entry.py b/tools/binman/entry.py
index 5374178542e..8b46fbb5fa6 100644
--- a/tools/binman/entry.py
+++ b/tools/binman/entry.py
@@ -220,3 +220,12 @@ class Entry(object):
section: Section containing the entry
"""
pass
+
+def CheckPosition(self):
+"""Check that the entry positions are correct
+
+This is used for entries which have extra position requirements (other
+than having to be fully inside their section). Sub-classes can
implement
+this function and raise if there is a problem.
+"""
+pass
diff --git a/tools/binman/etype/section.py b/tools/binman/etype/section.py
new file mode 100644
index 000..4e2f686eea8
--- /dev/null
+++ b/tools/binman/etype/section.py
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2018 Google, Inc
+# Written by Simon Glass
+#
+# Entry-type module for sections, which are entries which can contain other
+# entries.
+#
+
+from entry import Entry
+import fdt_util
+import tools
+
+import bsection
+
+class Entry_section(Entry):
+def __init__(self, image, etype, node):
+Entry.__init__(self, image, etype, node)
+self._section = bsection.Section(node.name, node)
+
+def ObtainContents(self):
+self._section.GetEntryContents()
+
+def GetData(self):
+return
[U-Boot] [PATCH v2 05/12] binman: Avoid setting sys.path globally
At present we set the Python path at the start of binman so we can read
modules in the 'etype' directory. This is a bit messy since it affects
'import' statements through binman.
Adjust the code to set the path locally, just where it is needed. Move
the 'entry' module in with the other base modules to help with this. It
makes more sense here anyway since it does not implement an entry type.
Signed-off-by: Simon Glass
---
Changes in v2: None
tools/binman/binman.py| 3 ---
tools/binman/{etype => }/entry.py | 10 ++
2 files changed, 10 insertions(+), 3 deletions(-)
rename tools/binman/{etype => }/entry.py (96%)
diff --git a/tools/binman/binman.py b/tools/binman/binman.py
index fa2f551f554..d49402a977e 100755
--- a/tools/binman/binman.py
+++ b/tools/binman/binman.py
@@ -23,9 +23,6 @@ for dirname in ['../patman', '../dtoc', '..']:
# Bring in the libfdt module
sys.path.insert(0, 'scripts/dtc/pylibfdt')
-# Also allow entry-type modules to be brought in from the etype directory.
-sys.path.insert(0, os.path.join(our_path, 'etype'))
-
import cmdline
import command
import control
diff --git a/tools/binman/etype/entry.py b/tools/binman/entry.py
similarity index 96%
rename from tools/binman/etype/entry.py
rename to tools/binman/entry.py
index cbcabe20582..5374178542e 100644
--- a/tools/binman/etype/entry.py
+++ b/tools/binman/entry.py
@@ -14,10 +14,14 @@ except:
have_importlib = False
import fdt_util
+import os
+import sys
import tools
modules = {}
+our_path = os.path.dirname(os.path.realpath(__file__))
+
class Entry(object):
"""An Entry in the section
@@ -80,8 +84,12 @@ class Entry(object):
module_name = module_name.split('@')[0]
module = modules.get(module_name)
+# Also allow entry-type modules to be brought in from the etype
directory.
+
# Import the module if we have not already done so.
if not module:
+old_path = sys.path
+sys.path.insert(0, os.path.join(our_path, 'etype'))
try:
if have_importlib:
module = importlib.import_module(module_name)
@@ -90,6 +98,8 @@ class Entry(object):
except ImportError:
raise ValueError("Unknown entry type '%s' in node '%s'" %
(etype, node.path))
+finally:
+sys.path = old_path
modules[module_name] = module
# Call its constructor to get the object we want.
--
2.17.0.921.gf22659ad46-goog
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[U-Boot] [PATCH v2 07/12] binman: Add documentation for pos-unset property
This property is not documented. Add a note to the README. Signed-off-by: Simon Glass --- Changes in v2: None tools/binman/README | 7 +++ 1 file changed, 7 insertions(+) diff --git a/tools/binman/README b/tools/binman/README index 5ef1246f296..32d89194dd0 100644 --- a/tools/binman/README +++ b/tools/binman/README @@ -316,6 +316,13 @@ type: possible to use any name, and then add (for example) 'type = "u-boot"' to specify the type. +pos-unset: + Indicates that the position of this entry should not be set by placing + it immediately after the entry before. Instead, is set by another + entry which knows where this entry should go. When this boolean + property is present, binman will give an error if another entry does + not set the position (with the GetPositions() method). + The attributes supported for images are described below. Several are similar to those for entries. -- 2.17.0.921.gf22659ad46-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] sandbox_flattree: Switch to TPMv2 support
+Miquel due to sandbox TPM issue Hi Tom, On 25 May 2018 at 06:27, Tom Rini wrote: > In order to have the test.py tests for TPMv2 run automatically we need > to have one of our sandbox builds use TPMv2 rather than TPMv1. Switch > sandbox_flattree over to this style of TPM. The problem seems to be that the sandbox driver is only built with either TPMv1 or TPMv2. It needs to be able to build with both, so we can run tests with both. It really doesn't make any sense to have build-time branches for sandbox. We currently have: sandbox - should be used for most tests sandbox64 - special build that forces a 64-bit host sandbox_flattree - builds with dev_read_...() functions defined as inline. We need this build so that we can test those inline functions, and we cannot build with both the inline functions and the non-inline functions since they are named the same sandbox_noblk - builds without CONFIG_BLK, which means the legacy block drivers are used. We cannot use both the legacy and driver-model block drivers since they implement the same functions sandbox_spl - builds sandbox with SPL support, so you can run spl/u-boot-spl and it will start up and then load ./u-boot. We could probably remove this and add SPL support to the vanilla sandbox build, since people can still run ./u-boot directly At present there are unnecessary config differences between these builds. This is explained by the fact that it is a pain for people to have to add configs separately to each defconfig. But we should probably make them more common. I will take a look. What do you think about dropping sandbox_spl and make sandbox build SPL? It does take slightly longer to build, perhaps 25%. > > Cc: Simon Glass > Signed-off-by: Tom Rini > --- > I'm tempted to switch the main sandbox target over instead as I don't > quite see where we're running the tpm1.x tests automatically. Would > that be a better idea? > --- Miquel, can we adjust the code to build both TPMv1 and v2 for sandbox, and select at run-time? > configs/sandbox_flattree_defconfig | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 02/12] binman: Refactor much of the image code into 'section'
We want to support multiple sections within a single image. To do this,
move most of the Image class implementation into a new Section class. An
Image contains only a single Section, but at some point we will support
a new 'section' entry, thus allowing Sections within Sections.
Use the name 'bsection' for the module so we can use 'section' for the
etype module.
Signed-off-by: Simon Glass
---
Changes in v2:
- Put SPDX on the first line in bsection.py
tools/binman/bsection.py | 302 +
tools/binman/ftest.py | 16 +-
tools/binman/image.py | 247 +++---
tools/binman/image_test.py | 18 ++-
4 files changed, 340 insertions(+), 243 deletions(-)
create mode 100644 tools/binman/bsection.py
diff --git a/tools/binman/bsection.py b/tools/binman/bsection.py
new file mode 100644
index 000..07c72d34c43
--- /dev/null
+++ b/tools/binman/bsection.py
@@ -0,0 +1,302 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2018 Google, Inc
+# Written by Simon Glass
+#
+# Base class for sections (collections of entries)
+#
+
+from __future__ import print_function
+
+from collections import OrderedDict
+import sys
+
+import fdt_util
+import re
+import tools
+
+class Section(object):
+"""A section which contains multiple entries
+
+A section represents a collection of entries. There must be one or more
+sections in an image. Sections are used to group entries together.
+
+Attributes:
+_node: Node object that contains the section definition in device tree
+_size: Section size in bytes, or None if not known yet
+_align_size: Section size alignment, or None
+_pad_before: Number of bytes before the first entry starts. This
+effectively changes the place where entry position 0 starts
+_pad_after: Number of bytes after the last entry ends. The last
+entry will finish on or before this boundary
+_pad_byte: Byte to use to pad the section where there is no entry
+_sort: True if entries should be sorted by position, False if they
+must be in-order in the device tree description
+_skip_at_start: Number of bytes before the first entry starts. These
+effectively adjust the starting position of entries. For example,
+if _pad_before is 16, then the first entry would start at 16.
+An entry with pos = 20 would in fact be written at position 4
+in the image file.
+_end_4gb: Indicates that the section ends at the 4GB boundary. This is
+used for x86 images, which want to use positions such that a
+ memory address (like 0xff80) is the first entry position.
+ This causes _skip_at_start to be set to the starting memory
+ address.
+_entries: OrderedDict() of entries
+"""
+def __init__(self, name, node, test=False):
+global entry
+global Entry
+import entry
+from entry import Entry
+
+self._node = node
+self._size = None
+self._align_size = None
+self._pad_before = 0
+self._pad_after = 0
+self._pad_byte = 0
+self._sort = False
+self._skip_at_start = 0
+self._end_4gb = False
+self._entries = OrderedDict()
+if not test:
+self._ReadNode()
+self._ReadEntries()
+
+def _ReadNode(self):
+"""Read properties from the section node"""
+self._size = fdt_util.GetInt(self._node, 'size')
+self._align_size = fdt_util.GetInt(self._node, 'align-size')
+if tools.NotPowerOfTwo(self._align_size):
+self._Raise("Alignment size %s must be a power of two" %
+self._align_size)
+self._pad_before = fdt_util.GetInt(self._node, 'pad-before', 0)
+self._pad_after = fdt_util.GetInt(self._node, 'pad-after', 0)
+self._pad_byte = fdt_util.GetInt(self._node, 'pad-byte', 0)
+self._sort = fdt_util.GetBool(self._node, 'sort-by-pos')
+self._end_4gb = fdt_util.GetBool(self._node, 'end-at-4gb')
+if self._end_4gb and not self._size:
+self._Raise("Section size must be provided when using end-at-4gb")
+if self._end_4gb:
+self._skip_at_start = 0x1 - self._size
+
+def _ReadEntries(self):
+for node in self._node.subnodes:
+self._entries[node.name] = Entry.Create(self, node)
+
+def CheckSize(self):
+"""Check that the section contents does not exceed its size, etc."""
+contents_size = 0
+for entry in self._entries.values():
+contents_size = max(contents_size, entry.pos + entry.size)
+
+contents_size -= self._skip_at_start
+
+size = self._size
+if not size:
+size = self._pad_before + contents_size + self._pad_after
+size = tools.Align(size, self._align_size)
+
+if
[U-Boot] [PATCH v2 01/12] binman: Allow unit addresses for binaries
Allow the same binary to appear multiple times in an image by using the
device-tree unit-address feature (u-boot@0, u-boot@1).
Signed-off-by: Simon Glass
---
Changes in v2:
- Add SPDX tag to .dts file
tools/binman/README | 4
tools/binman/etype/entry.py | 5 +
tools/binman/ftest.py | 5 +
tools/binman/test/54_unit_address.dts | 15 +++
4 files changed, 29 insertions(+)
create mode 100644 tools/binman/test/54_unit_address.dts
diff --git a/tools/binman/README b/tools/binman/README
index b20098177ee..196dda1fb4c 100644
--- a/tools/binman/README
+++ b/tools/binman/README
@@ -387,6 +387,10 @@ end-at-4gb:
Examples of the above options can be found in the tests. See the
tools/binman/test directory.
+It is possible to have the same binary appear multiple times in the image,
+either by using a unit number suffix (u-boot@0, u-boot@1) or by using a
+different name for each and specifying the type with the 'type' attribute.
+
Special properties
--
diff --git a/tools/binman/etype/entry.py b/tools/binman/etype/entry.py
index c331312c491..23e436a2e9d 100644
--- a/tools/binman/etype/entry.py
+++ b/tools/binman/etype/entry.py
@@ -72,7 +72,12 @@ class Entry(object):
"""
if not etype:
etype = fdt_util.GetString(node, 'type', node.name)
+
+# Convert something like 'u-boot@0' to 'u_boot' since we are only
+# interested in the type.
module_name = etype.replace('-', '_')
+if '@' in module_name:
+module_name = module_name.split('@')[0]
module = modules.get(module_name)
# Import the module if we have not already done so.
diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py
index a3abbc4b84b..b5e8736fbb5 100644
--- a/tools/binman/ftest.py
+++ b/tools/binman/ftest.py
@@ -909,6 +909,11 @@ class TestFunctional(unittest.TestCase):
sym_values + U_BOOT_SPL_DATA[16:])
self.assertEqual(expected, data)
+def testPackUnitAddress(self):
+"""Test that we support multiple binaries with the same name"""
+data = self._DoReadFile('54_unit_address.dts')
+self.assertEqual(U_BOOT_DATA + U_BOOT_DATA, data)
+
if __name__ == "__main__":
unittest.main()
diff --git a/tools/binman/test/54_unit_address.dts
b/tools/binman/test/54_unit_address.dts
new file mode 100644
index 000..3216dbbcc19
--- /dev/null
+++ b/tools/binman/test/54_unit_address.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ u-boot@0 {
+ };
+ u-boot@1 {
+ };
+ };
+};
--
2.17.0.921.gf22659ad46-goog
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