[PATCH] ARM: tegra: Add NVIDIA Jetson Nano Developer Kit support
From: Tom Warren
The Jetson Nano Developer Kit is a Tegra X1-based development board. It
is similar to Jetson TX1 but it is not pin compatible. It features 4GB
of LPDDR4, a SPI NOR flash for early boot firmware and an SD card slot
used for storage.
HDMI 2.0 or DP 1.2 are available for display, four USB ports (3 USB 2.0
and 1 USB 3.0) can be used to attach a variety of peripherals and a PCI
Ethernet controller provides onboard network connectivity. NVMe support
has also been added. Env save is at the end of QSPI (4MB-8K).
A 40-pin header on the board can be used to extend the capabilities and
exposed interfaces of the Jetson Nano.
Signed-off-by: Thierry Reding
Signed-off-by: Tom Warren
---
retry send-email to see if it shows up in Patchwork
arch/arm/dts/Makefile| 3 +-
arch/arm/dts/tegra210-p3450-.dts | 147 +
arch/arm/mach-tegra/board2.c | 25 +
arch/arm/mach-tegra/tegra210/Kconfig | 7 ++
board/nvidia/p3450-/Kconfig | 12 +++
board/nvidia/p3450-/MAINTAINERS | 6 ++
board/nvidia/p3450-/Makefile | 8 ++
board/nvidia/p3450-/p3450-.c | 178 +++
configs/p3450-_defconfig | 64 +
include/configs/p3450-.h | 46 +
10 files changed, 495 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/tegra210-p3450-.dts
create mode 100644 board/nvidia/p3450-/Kconfig
create mode 100644 board/nvidia/p3450-/MAINTAINERS
create mode 100644 board/nvidia/p3450-/Makefile
create mode 100644 board/nvidia/p3450-/p3450-.c
create mode 100644 configs/p3450-_defconfig
create mode 100644 include/configs/p3450-.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9c593b2..820ee97 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -180,7 +180,8 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra210-e2220-1170.dtb \
tegra210-p2371-.dtb \
tegra210-p2371-2180.dtb \
- tegra210-p2571.dtb
+ tegra210-p2571.dtb \
+ tegra210-p3450-.dtb
dtb-$(CONFIG_ARCH_MVEBU) +=\
armada-3720-db.dtb \
diff --git a/arch/arm/dts/tegra210-p3450-.dts
b/arch/arm/dts/tegra210-p3450-.dts
new file mode 100644
index 000..9ef744a
--- /dev/null
+++ b/arch/arm/dts/tegra210-p3450-.dts
@@ -0,0 +1,147 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019-2020 NVIDIA Corporation
+ */
+/dts-v1/;
+
+#include "tegra210.dtsi"
+
+/ {
+ model = "NVIDIA Jetson Nano Developer Kit";
+ compatible = "nvidia,p3450-", "nvidia,tegra210";
+
+ chosen {
+ stdout-path =
+ };
+
+ aliases {
+ ethernet = "/pcie@1003000/pci@2,0/ethernet@0,0";
+ i2c0 = "/i2c@7000d000";
+ i2c2 = "/i2c@7000c400";
+ i2c3 = "/i2c@7000c500";
+ i2c4 = "/i2c@7000c700";
+ mmc0 = "/sdhci@700b0600";
+ mmc1 = "/sdhci@700b";
+ spi0 = "/spi@7041";
+ usb0 = "/usb@7d00";
+ };
+
+ memory {
+ reg = <0x0 0x8000 0x0 0xc000>;
+ };
+
+ pcie@1003000 {
+ status = "okay";
+
+ pci@1,0 {
+ status = "okay";
+ };
+
+ pci@2,0 {
+ status = "okay";
+
+ ethernet@0,0 {
+ reg = <0x00 0 0 0 0>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ };
+ };
+ };
+
+ serial@70006000 {
+ status = "okay";
+ };
+
+ padctl@7009f000 {
+ pinctrl-0 = <_default>;
+ pinctrl-names = "default";
+
+ padctl_default: pinmux {
+ xusb {
+ nvidia,lanes = "otg-1", "otg-2";
+ nvidia,function = "xusb";
+ nvidia,iddq = <0>;
+ };
+
+ usb3 {
+ nvidia,lanes = "pcie-5", "pcie-6";
+ nvidia,function = "usb3";
+ nvidia,iddq = <0>;
+ };
+
+ pcie-x1 {
+ nvidia,lanes = "pcie-0";
+ nvidia,function = "pcie-x1";
+ nvidia,iddq = <0>;
+ };
+
+ pcie-x4 {
+ nvidia,lanes = "pcie-1", "pcie-2",
+ "pcie-3", "pcie-4";
+ nvidia,function = "pcie-x4";
+ nvidia,iddq = <0>;
+ };
+
+ sata {
+
[PATCH] mtd: spi: Add Macronix MX25U3235F device
From: Tom Warren
Add Macronix MX25U3235F flash device description.
This is a 4MiB part.
Signed-off-by: Tom Warren
---
drivers/mtd/spi/spi-nor-ids.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 973b6f8..abdf560 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -147,6 +147,7 @@ const struct flash_info spi_nor_ids[] = {
{ INFO("mx25l6405d", 0xc22017, 0, 64 * 1024, 128, SECT_4K) },
{ INFO("mx25u2033e", 0xc22532, 0, 64 * 1024, 4, SECT_4K) },
{ INFO("mx25u1635e", 0xc22535, 0, 64 * 1024, 32, SECT_4K) },
+ { INFO("mx25u3235f", 0xc22536, 0, 4 * 1024, 1024, SECT_4K) },
{ INFO("mx25u6435f", 0xc22537, 0, 64 * 1024, 128, SECT_4K) },
{ INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, 0) },
{ INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) },
--
1.8.2.1.610.g562af5b
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[PATCH 0/3] Misc fixes for Tegra
From: Tom Warren These fixes originated on our downstream L4T U-Boot, and include fdt, pll and code relocation changes. Stephen Warren (1): ARM: tegra: p2371-2180: add I2C nodes to DT Tom Warren (1): fdt: Fix 'system' command Vishruth (1): ARM: tegra: p2771-: enable PIE relocation arch/arm/dts/tegra210-p2371-2180.dts | 18 ++ cmd/fdt.c| 2 +- configs/p2771--000_defconfig | 1 + configs/p2771--500_defconfig | 1 + 4 files changed, 21 insertions(+), 1 deletion(-) -- 1.8.2.1.610.g562af5b --- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. ---
[PATCH 1/2] net: rt8169: WAR for DHCP not getting IP after kernel boot/reboot
From: Tom Warren
This is a WAR for DHCP failure after rebooting from the L4T kernel. The
r8169.c kernel driver is setting bit 19 of the rt816x HW register 0xF0,
which goes by FuncEvent and MISC in various driver source/datasheets.
That bit is called RxDv_Gated_En in the r8169.c kernel driver. Clear it
here at the end of probe to ensure that U-Boot can get an IP assigned
via DHCP.
Signed-off-by: Tom Warren
---
drivers/net/rtl8169.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
index 5ccdfdd..ff89e28 100644
--- a/drivers/net/rtl8169.c
+++ b/drivers/net/rtl8169.c
@@ -237,6 +237,9 @@ enum RTL8169_register_content {
/*_TBICSRBit*/
TBILinkOK = 0x0200,
+
+ /* FuncEvent/Misc */
+ RxDv_Gated_En = 0x8,
};
static struct {
@@ -1207,6 +1210,19 @@ static int rtl8169_eth_probe(struct udevice *dev)
return ret;
}
+ /*
+* WAR for DHCP failure after rebooting from kernel.
+* Clear RxDv_Gated_En bit which was set by kernel driver.
+* Without this, U-Boot can't get an IP via DHCP.
+* Register (FuncEvent, aka MISC) and RXDV_GATED_EN bit are from
+* the r8169.c kernel driver.
+*/
+
+ u32 val = RTL_R32(FuncEvent);
+ debug("%s: FuncEvent/Misc (0xF0) = 0x%08X\n", __func__, val);
+ val &= ~RxDv_Gated_En;
+ RTL_W32(FuncEvent, val);
+
return 0;
}
--
1.8.2.1.610.g562af5b
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[PATCH 2/2] tegra: Enable CONFIG_BOOTP_PREFER_SERVERIP for all Jetson boards
From: Tom Warren This allows the user to set $serverip in the environment before executing a DHCP request. If they do, U-Boot will use that IP rather than using the IP in the DHCP response. Signed-off-by: Tom Warren Acked-by: Stephen Warren --- configs/e2220-1170_defconfig | 1 + configs/p2371-_defconfig | 1 + configs/p2371-2180_defconfig | 1 + configs/p2571_defconfig | 1 + configs/p2771--000_defconfig | 1 + configs/p2771--500_defconfig | 1 + 6 files changed, 6 insertions(+) diff --git a/configs/e2220-1170_defconfig b/configs/e2220-1170_defconfig index 1639040..951ed1d 100644 --- a/configs/e2220-1170_defconfig +++ b/configs/e2220-1170_defconfig @@ -43,3 +43,4 @@ CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_BOOTP_PREFER_SERVERIP=y diff --git a/configs/p2371-_defconfig b/configs/p2371-_defconfig index 2070199..7081719 100644 --- a/configs/p2371-_defconfig +++ b/configs/p2371-_defconfig @@ -44,3 +44,4 @@ CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_BOOTP_PREFER_SERVERIP=y diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig index 8c808ae..c70217c 100644 --- a/configs/p2371-2180_defconfig +++ b/configs/p2371-2180_defconfig @@ -52,3 +52,4 @@ CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_BOOTP_PREFER_SERVERIP=y diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig index 721c5c5..43c24b8 100644 --- a/configs/p2571_defconfig +++ b/configs/p2571_defconfig @@ -44,3 +44,4 @@ CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_BOOTP_PREFER_SERVERIP=y diff --git a/configs/p2771--000_defconfig b/configs/p2771--000_defconfig index e347a77..8bf8419 100644 --- a/configs/p2771--000_defconfig +++ b/configs/p2771--000_defconfig @@ -37,3 +37,4 @@ CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_POSITION_INDEPENDENT=y +CONFIG_BOOTP_PREFER_SERVERIP=y diff --git a/configs/p2771--500_defconfig b/configs/p2771--500_defconfig index 0803b26..1f40333 100644 --- a/configs/p2771--500_defconfig +++ b/configs/p2771--500_defconfig @@ -37,3 +37,4 @@ CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_POSITION_INDEPENDENT=y +CONFIG_BOOTP_PREFER_SERVERIP=y -- 1.8.2.1.610.g562af5b --- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. ---
[PATCH 1/3] qspi: t210: Fix claim_bus's use of the wrong bus/device
From: Tom Warren
claim_bus() is passed a udevice *dev, which is the bus device's parent.
In this driver, claim_bus assumed it was the bus, which caused the
'priv' info pointer to be wrong, and periph_id was incorrect. This in
turn caused the periph clock call to assign the wrong clock (PLLM
instead of PLLP0), which caused a kernel warning. I only saw the 'bad'
periph_id when enabling DEBUG due to an assert. Not sure how QSPI was
working w/this errant clock, but it was moot as QSPI wasn't active
unless you probed it, and that wasn't happening until I posted a patch
to enable env save to QSPI for Nano (coming soon).
Signed-off-by: Tom Warren
---
Changes in v2:
- None
drivers/spi/tegra210_qspi.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/tegra210_qspi.c b/drivers/spi/tegra210_qspi.c
index d82ecaa..2a77126 100644
--- a/drivers/spi/tegra210_qspi.c
+++ b/drivers/spi/tegra210_qspi.c
@@ -2,7 +2,8 @@
/*
* NVIDIA Tegra210 QSPI controller driver
*
- * (C) Copyright 2015 NVIDIA Corporation
+ * (C) Copyright 2015-2019 NVIDIA Corporation
+ *
*/
#include
@@ -137,8 +138,9 @@ static int tegra210_qspi_probe(struct udevice *bus)
return 0;
}
-static int tegra210_qspi_claim_bus(struct udevice *bus)
+static int tegra210_qspi_claim_bus(struct udevice *dev)
{
+ struct udevice *bus = dev->parent;
struct tegra210_qspi_priv *priv = dev_get_priv(bus);
struct qspi_regs *regs = priv->regs;
--
1.8.2.1.610.g562af5b
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[PATCH 3/3] qspi: t210: Use dev_read calls to get FDT data like base, freq
From: Tom Warren
This Tegra QSPI driver hadn't been brought up to date with how
DM drivers are fetching data from the FDT now, and was pulling
in bogus data for base, max freq, etc. Fixed ofdata_to_platdata
to work the same way it does in the tegra114 SPI driver, using
dev_read_ functions.
Signed-off-by: Tom Warren
---
Changes in v2:
- New
drivers/spi/tegra210_qspi.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/spi/tegra210_qspi.c b/drivers/spi/tegra210_qspi.c
index 4284ea9..466d572 100644
--- a/drivers/spi/tegra210_qspi.c
+++ b/drivers/spi/tegra210_qspi.c
@@ -2,7 +2,7 @@
/*
* NVIDIA Tegra210 QSPI controller driver
*
- * (C) Copyright 2015-2019 NVIDIA Corporation
+ * (C) Copyright 2015-2020 NVIDIA Corporation
*
*/
@@ -97,10 +97,8 @@ struct tegra210_qspi_priv {
static int tegra210_qspi_ofdata_to_platdata(struct udevice *bus)
{
struct tegra_spi_platdata *plat = bus->platdata;
- const void *blob = gd->fdt_blob;
- int node = dev_of_offset(bus);
- plat->base = devfdt_get_addr(bus);
+ plat->base = dev_read_addr(bus);
plat->periph_id = clock_decode_periph_id(bus);
if (plat->periph_id == PERIPH_ID_NONE) {
@@ -110,9 +108,9 @@ static int tegra210_qspi_ofdata_to_platdata(struct udevice
*bus)
}
/* Use 500KHz as a suitable default */
- plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
+ plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
50);
- plat->deactivate_delay_us = fdtdec_get_int(blob, node,
+ plat->deactivate_delay_us = dev_read_u32_default(bus,
"spi-deactivate-delay", 0);
debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d,
deactivate_delay=%d\n",
__func__, plat->base, plat->periph_id, plat->frequency,
--
1.8.2.1.610.g562af5b
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[PATCH 0/3 v2] qspi: t210: fix claim_bus and clock/tap delays
From: Tom Warren These patches fix a couple of problems encountered in the T210 QSPI driver discovered during Jetson Nano bringup, and adapt the driver to upstream DM norms. Tom Warren (3): qspi: t210: Fix claim_bus's use of the wrong bus/device qspi: t210: Fix QSPI clock and tap delays qspi: t210: Use dev_read calls to get FDT data like base, freq drivers/spi/tegra210_qspi.c | 33 +++-- 1 file changed, 19 insertions(+), 14 deletions(-) -- 1.8.2.1.610.g562af5b --- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. ---
[PATCH 2/3] qspi: t210: Fix QSPI clock and tap delays
From: Tom Warren
When claim_bus was setting the clock, it reset the QSPI controller,
which wipes out any tap delays set by previous bootloaders (nvtboot,
CBoot for example on Nano). Instead of doing that in claim_bus, which
gets called a lot, moved clock setting to probe(), and set tap delays
there, too. Also updated clock to 80MHz to match CBoot. Now QSPI env
save works reliably again.
Signed-off-by: Tom Warren
---
Changes in v2:
- None
drivers/spi/tegra210_qspi.c | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/tegra210_qspi.c b/drivers/spi/tegra210_qspi.c
index 2a77126..4284ea9 100644
--- a/drivers/spi/tegra210_qspi.c
+++ b/drivers/spi/tegra210_qspi.c
@@ -42,10 +42,10 @@ DECLARE_GLOBAL_DATA_PTR;
#define QSPI_CMD1_BITLEN_SHIFT 0
/* COMMAND2 */
-#define QSPI_CMD2_TX_CLK_TAP_DELAY BIT(6)
-#define QSPI_CMD2_TX_CLK_TAP_DELAY_MASKGENMASK(11,6)
-#define QSPI_CMD2_RX_CLK_TAP_DELAY BIT(0)
-#define QSPI_CMD2_RX_CLK_TAP_DELAY_MASKGENMASK(5,0)
+#define QSPI_CMD2_TX_CLK_TAP_DELAY_SHIFT 10
+#define QSPI_CMD2_TX_CLK_TAP_DELAY_MASKGENMASK(14,10)
+#define QSPI_CMD2_RX_CLK_TAP_DELAY_SHIFT 0
+#define QSPI_CMD2_RX_CLK_TAP_DELAY_MASKGENMASK(7,0)
/* TRANSFER STATUS */
#define QSPI_XFER_STS_RDY BIT(30)
@@ -127,14 +127,22 @@ static int tegra210_qspi_probe(struct udevice *bus)
struct tegra210_qspi_priv *priv = dev_get_priv(bus);
priv->regs = (struct qspi_regs *)plat->base;
+ struct qspi_regs *regs = priv->regs;
priv->last_transaction_us = timer_get_us();
priv->freq = plat->frequency;
priv->periph_id = plat->periph_id;
+ debug("%s: Freq = %u, id = %d\n", __func__, priv->freq,
priv->periph_id);
/* Change SPI clock to correct frequency, PLLP_OUT0 source */
clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq);
+ /* Set tap delays here, clock change above resets QSPI controller */
+ u32 reg = (0x09 << QSPI_CMD2_TX_CLK_TAP_DELAY_SHIFT) |
+ (0x0C << QSPI_CMD2_RX_CLK_TAP_DELAY_SHIFT);
+ writel(reg, >command2);
+ debug("%s: COMMAND2 = %08x\n", __func__, readl(>command2));
+
return 0;
}
@@ -144,9 +152,6 @@ static int tegra210_qspi_claim_bus(struct udevice *dev)
struct tegra210_qspi_priv *priv = dev_get_priv(bus);
struct qspi_regs *regs = priv->regs;
- /* Change SPI clock to correct frequency, PLLP_OUT0 source */
- clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq);
-
debug("%s: FIFO STATUS = %08x\n", __func__, readl(>fifo_status));
/* Set master mode and sw controlled CS */
--
1.8.2.1.610.g562af5b
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[PATCH 3/3] t210: pinmux: Remove pinmux/GPIO init from T210 boards
From: Tom Warren
T210 CBoot is now doing the full pinmux and GPIO init, based on the DTB
tables. Remove pinmux/GPIO init tables & code from all T210-based builds
below:
p2371-2180 aka TX1
p2371-
e2220-1170
p2571
Signed-off-by: Tom Warren
Acked-by: Stephen Warren
---
arch/arm/mach-tegra/tegra210/Makefile | 3 +-
arch/arm/mach-tegra/tegra210/pinmux.c | 194 --
board/nvidia/e2220-1170/e2220-1170.c | 21 +-
board/nvidia/e2220-1170/pinmux-config-e2220-1170.h | 276
board/nvidia/p2371-/p2371-.c | 21 +-
board/nvidia/p2371-/pinmux-config-p2371-.h | 267
board/nvidia/p2371-2180/p2371-2180.c | 21 +-
board/nvidia/p2371-2180/pinmux-config-p2371-2180.h | 278 -
board/nvidia/p2571/p2571.c | 21 +-
board/nvidia/p2571/pinmux-config-p2571.h | 242 --
10 files changed, 5 insertions(+), 1339 deletions(-)
delete mode 100644 arch/arm/mach-tegra/tegra210/pinmux.c
delete mode 100644 board/nvidia/e2220-1170/pinmux-config-e2220-1170.h
delete mode 100644 board/nvidia/p2371-/pinmux-config-p2371-.h
delete mode 100644 board/nvidia/p2371-2180/pinmux-config-p2371-2180.h
delete mode 100644 board/nvidia/p2571/pinmux-config-p2571.h
diff --git a/arch/arm/mach-tegra/tegra210/Makefile
b/arch/arm/mach-tegra/tegra210/Makefile
index b6012fc..cfcba5b 100644
--- a/arch/arm/mach-tegra/tegra210/Makefile
+++ b/arch/arm/mach-tegra/tegra210/Makefile
@@ -1,5 +1,5 @@
#
-# (C) Copyright 2013-2015
+# (C) Copyright 2013-2020
# NVIDIA Corporation
#
# SPDX-License-Identifier: GPL-2.0+
@@ -7,6 +7,5 @@
obj-y += clock.o
obj-y += funcmux.o
-obj-y += pinmux.o
obj-y += xusb-padctl.o
obj-y += ../xusb-padctl-common.o
diff --git a/arch/arm/mach-tegra/tegra210/pinmux.c
b/arch/arm/mach-tegra/tegra210/pinmux.c
deleted file mode 100644
index 6158099..000
--- a/arch/arm/mach-tegra/tegra210/pinmux.c
+++ /dev/null
@@ -1,194 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
- */
-
-#include
-#include
-#include
-
-#define PIN(pin, f0, f1, f2, f3) \
- { \
- .funcs = { \
- PMUX_FUNC_##f0, \
- PMUX_FUNC_##f1, \
- PMUX_FUNC_##f2, \
- PMUX_FUNC_##f3, \
- }, \
- }
-
-#define PIN_RESERVED {}
-
-static const struct pmux_pingrp_desc tegra210_pingroups[] = {
- /* pin, f0, f1, f2,f3 */
- /* Offset 0x3000 */
- PIN(SDMMC1_CLK_PM0, SDMMC1, RSVD1, RSVD2, RSVD3),
- PIN(SDMMC1_CMD_PM1, SDMMC1, SPI3, RSVD2, RSVD3),
- PIN(SDMMC1_DAT3_PM2, SDMMC1, SPI3, RSVD2, RSVD3),
- PIN(SDMMC1_DAT2_PM3, SDMMC1, SPI3, RSVD2, RSVD3),
- PIN(SDMMC1_DAT1_PM4, SDMMC1, SPI3, RSVD2, RSVD3),
- PIN(SDMMC1_DAT0_PM5, SDMMC1, RSVD1, RSVD2, RSVD3),
- PIN_RESERVED,
- /* Offset 0x301c */
- PIN(SDMMC3_CLK_PP0, SDMMC3, RSVD1, RSVD2, RSVD3),
- PIN(SDMMC3_CMD_PP1, SDMMC3, RSVD1, RSVD2, RSVD3),
- PIN(SDMMC3_DAT0_PP5, SDMMC3, RSVD1, RSVD2, RSVD3),
- PIN(SDMMC3_DAT1_PP4, SDMMC3, RSVD1, RSVD2, RSVD3),
- PIN(SDMMC3_DAT2_PP3, SDMMC3, RSVD1, RSVD2, RSVD3),
- PIN(SDMMC3_DAT3_PP2, SDMMC3, RSVD1, RSVD2, RSVD3),
- PIN_RESERVED,
- /* Offset 0x3038 */
- PIN(PEX_L0_RST_N_PA0, PE0,RSVD1, RSVD2, RSVD3),
- PIN(PEX_L0_CLKREQ_N_PA1, PE0,RSVD1, RSVD2, RSVD3),
- PIN(PEX_WAKE_N_PA2, PE, RSVD1, RSVD2, RSVD3),
- PIN(PEX_L1_RST_N_PA3, PE1,RSVD1, RSVD2, RSVD3),
- PIN(PEX_L1_CLKREQ_N_PA4, PE1,RSVD1, RSVD2, RSVD3),
- PIN(SATA_LED_ACTIVE_PA5, SATA, RSVD1, RSVD2, RSVD3),
- PIN(SPI1_MOSI_PC0,SPI1, RSVD1, RSVD2, RSVD3),
- PIN(SPI1_MISO_PC1,SPI1, RSVD1, RSVD2, RSVD3),
- PIN(SPI1_SCK_PC2, SPI1, RSVD1, RSVD2, RSVD3),
- PIN(SPI1_CS0_PC3, SPI1, RSVD1, RSVD2, RSVD3),
- PIN(SPI1_CS1_PC4, SPI1, RSVD1, RSVD2, RSVD3),
- PIN(SPI2_MOSI_PB4,SPI2, DTV,RSVD2, RSVD3),
- PIN(SPI2_MISO_PB5,SPI2, DTV,RSVD2, RSVD3),
- PIN(SPI2_SCK_PB6, SPI2, DTV,RSVD2, RSVD3),
- PIN(SPI2_CS0_PB7, SPI2, DTV,RSVD2, RSVD3),
- PIN(SPI2_CS1_PDD0,SPI2, RSVD1, RSVD2, RSVD3),
- PIN(SPI4_MOSI_PC7,SPI4, RSVD1, RSVD2, RSVD3),
- PIN(SPI4_MISO_PD0,SPI4, RSVD1, RSVD2, RSVD3),
- PIN(SPI4_SCK_PC5, SPI4, RSVD1, RSVD2, RSVD3),
-
[PATCH 0/3] t210: miscellaneous patches
From: Tom Warren These patches change some PLL power sequencing, remove pinmuxing and GPIO init on T210, and adjust some load addresses to allow for larger kernels. JC Kuo (1): t210: do not enable PLLE and UPHY PLL HW PWRSEQ Tom Warren (2): t210: Adjust ramdisk_addr_r/fdt_addr_r to allow for large kernels t210: pinmux: Remove pinmux/GPIO init from T210 boards arch/arm/cpu/armv8/cpu.c | 5 + arch/arm/include/asm/arch-tegra/xusb-padctl.h | 1 + arch/arm/mach-tegra/board2.c | 6 + arch/arm/mach-tegra/tegra210/Makefile | 3 +- arch/arm/mach-tegra/tegra210/clock.c | 19 -- arch/arm/mach-tegra/tegra210/pinmux.c | 194 -- arch/arm/mach-tegra/tegra210/xusb-padctl.c | 68 +++-- arch/arm/mach-tegra/xusb-padctl-dummy.c| 4 + board/nvidia/e2220-1170/e2220-1170.c | 21 +- board/nvidia/e2220-1170/pinmux-config-e2220-1170.h | 276 board/nvidia/p2371-/p2371-.c | 21 +- board/nvidia/p2371-/pinmux-config-p2371-.h | 267 board/nvidia/p2371-2180/p2371-2180.c | 21 +- board/nvidia/p2371-2180/pinmux-config-p2371-2180.h | 278 - board/nvidia/p2571/p2571.c | 21 +- board/nvidia/p2571/pinmux-config-p2571.h | 242 -- include/configs/tegra210-common.h | 4 +- 17 files changed, 66 insertions(+), 1385 deletions(-) delete mode 100644 arch/arm/mach-tegra/tegra210/pinmux.c delete mode 100644 board/nvidia/e2220-1170/pinmux-config-e2220-1170.h delete mode 100644 board/nvidia/p2371-/pinmux-config-p2371-.h delete mode 100644 board/nvidia/p2371-2180/pinmux-config-p2371-2180.h delete mode 100644 board/nvidia/p2571/pinmux-config-p2571.h -- 1.8.2.1.610.g562af5b --- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. ---
[PATCH 2/3] t210: Adjust ramdisk_addr_r/fdt_addr_r to allow for large kernels
From: Tom Warren The L4T kernel is 32MB+, and can overwrite the ramdisk/fdt loaded from extlinux.conf. Adjust the load addresses to fix this for now. Using the calculated_env addresses table from T186 U-Boot is a better fix, but it isn't working correctly on T210 U-Boot right now, so this will do until I can fix it. Signed-off-by: Tom Warren --- include/configs/tegra210-common.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h index 1c53311..1b8e94b 100644 --- a/include/configs/tegra210-common.h +++ b/include/configs/tegra210-common.h @@ -46,8 +46,8 @@ "scriptaddr=0x9000\0" \ "pxefile_addr_r=0x9010\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "fdt_addr_r=0x8200\0" \ - "ramdisk_addr_r=0x8210\0" + "fdt_addr_r=0x8300\0" \ + "ramdisk_addr_r=0x8320\0" /* For USB EHCI controller */ #define CONFIG_EHCI_IS_TDI -- 1.8.2.1.610.g562af5b --- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. ---
[PATCH 1/3] t210: do not enable PLLE and UPHY PLL HW PWRSEQ
From: JC Kuo
This commit removes the programming sequence that enables PLLE and UPHY
PLL hardware power sequencers. Per TRM, boot software should enable PLLE
and UPHY PLLs in software controlled power-on state and should power
down PLL before jumping into kernel or the next stage boot software.
Adds call to board_cleanup_before_linux to facilitate this.
Signed-off-by: JC Kuo
Signed-off-by: Tom Warren
Acked-by: Stephen Warren
---
arch/arm/cpu/armv8/cpu.c | 5 ++
arch/arm/include/asm/arch-tegra/xusb-padctl.h | 1 +
arch/arm/mach-tegra/board2.c | 6 +++
arch/arm/mach-tegra/tegra210/clock.c | 19
arch/arm/mach-tegra/tegra210/xusb-padctl.c| 68 +--
arch/arm/mach-tegra/xusb-padctl-dummy.c | 4 ++
6 files changed, 59 insertions(+), 44 deletions(-)
diff --git a/arch/arm/cpu/armv8/cpu.c b/arch/arm/cpu/armv8/cpu.c
index 2467e0b..3575203 100644
--- a/arch/arm/cpu/armv8/cpu.c
+++ b/arch/arm/cpu/armv8/cpu.c
@@ -32,6 +32,8 @@ void sdelay(unsigned long loops)
"b.ne 1b" : "=r" (loops) : "0"(loops) : "cc");
}
+void __weak board_cleanup_before_linux(void){}
+
int cleanup_before_linux(void)
{
/*
@@ -40,6 +42,9 @@ int cleanup_before_linux(void)
*
* disable interrupt and turn off caches etc ...
*/
+
+ board_cleanup_before_linux();
+
disable_interrupts();
/*
diff --git a/arch/arm/include/asm/arch-tegra/xusb-padctl.h
b/arch/arm/include/asm/arch-tegra/xusb-padctl.h
index deccdf4..7e14d81 100644
--- a/arch/arm/include/asm/arch-tegra/xusb-padctl.h
+++ b/arch/arm/include/asm/arch-tegra/xusb-padctl.h
@@ -16,6 +16,7 @@ struct tegra_xusb_phy;
struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type);
void tegra_xusb_padctl_init(void);
+void tegra_xusb_padctl_exit(void);
int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy);
int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy);
int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy);
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index d3497a2..787ff97 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -181,6 +181,12 @@ int board_init(void)
return nvidia_board_init();
}
+void board_cleanup_before_linux(void)
+{
+ /* power down UPHY PLL */
+ tegra_xusb_padctl_exit();
+}
+
#ifdef CONFIG_BOARD_EARLY_INIT_F
static void __gpio_early_init(void)
{
diff --git a/arch/arm/mach-tegra/tegra210/clock.c
b/arch/arm/mach-tegra/tegra210/clock.c
index b240860..f1b25e2 100644
--- a/arch/arm/mach-tegra/tegra210/clock.c
+++ b/arch/arm/mach-tegra/tegra210/clock.c
@@ -1235,25 +1235,6 @@ int tegra_plle_enable(void)
value &= ~PLLE_SS_CNTL_INTERP_RESET;
writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
- /* 7. Enable HW power sequencer for PLLE */
-
- value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
- value &= ~PLLE_MISC_IDDQ_SWCTL;
- writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
-
- value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX);
- value &= ~PLLE_AUX_SS_SWCTL;
- value &= ~PLLE_AUX_ENABLE_SWCTL;
- value |= PLLE_AUX_SS_SEQ_INCLUDE;
- value |= PLLE_AUX_USE_LOCKDET;
- writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX);
-
- /* 8. Wait 1 us */
-
- udelay(1);
- value |= PLLE_AUX_SEQ_ENABLE;
- writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX);
-
return 0;
}
diff --git a/arch/arm/mach-tegra/tegra210/xusb-padctl.c
b/arch/arm/mach-tegra/tegra210/xusb-padctl.c
index ab6684f..64dc297 100644
--- a/arch/arm/mach-tegra/tegra210/xusb-padctl.c
+++ b/arch/arm/mach-tegra/tegra210/xusb-padctl.c
@@ -170,6 +170,17 @@ static int phy_unprepare(struct tegra_xusb_phy *phy)
return tegra_xusb_padctl_disable(phy->padctl);
}
+#define XUSB_PADCTL_USB3_PAD_MUX 0x28
+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE (1 << 0)
+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0 (1 << 1)
+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK1 (1 << 2)
+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK2 (1 << 3)
+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK3 (1 << 4)
+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK4 (1 << 5)
+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK5 (1 << 6)
+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK6 (1 << 7)
+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0 (1 << 8)
+
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK (0xff << 20)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(x) (((x) & 0xff) << 20)
@@ -366,31 +377,6 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy)
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
- value =
[PATCH 0/2] net: tegra: Misc network fixes
From: Tom Warren These two patches are from downstream Tegra L4T U-Boot. Tom Warren (2): net: rt8169: WAR for DHCP not getting IP after kernel boot/reboot tegra: Enable CONFIG_BOOTP_PREFER_SERVERIP for all Jetson boards configs/e2220-1170_defconfig | 1 + configs/p2371-_defconfig | 1 + configs/p2371-2180_defconfig | 1 + configs/p2571_defconfig | 1 + configs/p2771--000_defconfig | 1 + configs/p2771--500_defconfig | 1 + drivers/net/rtl8169.c| 16 7 files changed, 22 insertions(+) -- 1.8.2.1.610.g562af5b --- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. ---
[PATCH 3/3] ARM: tegra: p2371-2180: add I2C nodes to DT
From: Stephen Warren
This adds to the DT the I2C controllers that connect to the board ID EEPROM,
camera board EEPROM, etc. With this change, you can now probe all I2C devices
on a TX1 board.
Signed-off-by: Tom Warren
---
arch/arm/dts/tegra210-p2371-2180.dts | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/dts/tegra210-p2371-2180.dts
b/arch/arm/dts/tegra210-p2371-2180.dts
index c2f497c..d982b5f 100644
--- a/arch/arm/dts/tegra210-p2371-2180.dts
+++ b/arch/arm/dts/tegra210-p2371-2180.dts
@@ -12,6 +12,9 @@
aliases {
i2c0 = "/i2c@7000d000";
+ i2c2 = "/i2c@7000c400";
+ i2c3 = "/i2c@7000c500";
+ i2c5 = "/i2c@546c0c00";
mmc0 = "/sdhci@700b0600";
mmc1 = "/sdhci@700b";
usb0 = "/usb@7d00";
@@ -33,6 +36,11 @@
};
};
+ i2c@546c0c00 {
+ status = "okay";
+ clock-frequency = <40>;
+ };
+
padctl@7009f000 {
pinctrl-0 = <_default>;
pinctrl-names = "default";
@@ -85,6 +93,16 @@
non-removable;
};
+ i2c@7000c400 {
+ status = "okay";
+ clock-frequency = <40>;
+ };
+
+ i2c@7000c500 {
+ status = "okay";
+ clock-frequency = <40>;
+ };
+
i2c@7000d000 {
status = "okay";
clock-frequency = <40>;
--
1.8.2.1.610.g562af5b
---
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distribution
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[PATCH 1/3] ARM: tegra: p2771-0000: enable PIE relocation
From: Vishruth U-Boot is configured to build as position independent executable. Enable relocation of RELA section required to work with different load addresses. Signed-off-by: Vishruth Signed-off-by: Tom Warren --- configs/p2771--000_defconfig | 1 + configs/p2771--500_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/p2771--000_defconfig b/configs/p2771--000_defconfig index 06f12e2..e347a77 100644 --- a/configs/p2771--000_defconfig +++ b/configs/p2771--000_defconfig @@ -36,3 +36,4 @@ CONFIG_TEGRA186_POWER_DOMAIN=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_POSITION_INDEPENDENT=y diff --git a/configs/p2771--500_defconfig b/configs/p2771--500_defconfig index 1a14a92..0803b26 100644 --- a/configs/p2771--500_defconfig +++ b/configs/p2771--500_defconfig @@ -36,3 +36,4 @@ CONFIG_TEGRA186_POWER_DOMAIN=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_POSITION_INDEPENDENT=y -- 1.8.2.1.610.g562af5b --- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. ---
[PATCH 2/3] fdt: Fix 'system' command
From: Tom Warren
'fdt systemsetup' wasn't working, due to the fact that the 'set' command
was being parsed in do_fdt() by only testing for the leading 's' instead
of "se", which kept the "sys" test further down from executing. Changed
to test for "se" instead, now 'fdt systemsetup' works (to test the
ft_system_setup proc w/o having to boot a kernel).
Signed-off-by: Tom Warren
---
cmd/fdt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/cmd/fdt.c b/cmd/fdt.c
index 25a6ed4..36cc726 100644
--- a/cmd/fdt.c
+++ b/cmd/fdt.c
@@ -286,7 +286,7 @@ static int do_fdt(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
/*
* Set the value of a property in the working_fdt.
*/
- } else if (argv[1][0] == 's') {
+ } else if (strncmp(argv[1], "se", 2) == 0) {
char *pathp;/* path */
char *prop; /* property */
int nodeoffset;/* node offset from libfdt */
--
1.8.2.1.610.g562af5b
---
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[PATCH 2/2] mmc: t210: Fix 'bad' SD-card clock when doing 400KHz card detect
From: Tom Warren
According to the HW team, for some reason the normal clock select code
picks what appears to be a perfectly valid 375KHz SD card clock, based
on the CAR clock source and SDMMC1 controller register settings (CAR =
408MHz PLLP0 divided by 68 for 6MHz, then a SD Clock Control register
divisor of 16 = 375KHz). But the resulting SD card clock, as measured by
the HW team, is 700KHz, which is out-of-spec. So the WAR is to use the
values given in the TRM PLLP table to generate a 400KHz SD-clock (CAR
clock of 24.7MHz, SD Clock Control divisor of 62) only for SDMMC1 on
T210 when the requested clock is <= 400KHz. Note that as far as I can
tell, the other requests for clocks in the Tegra MMC driver result in
valid SD clocks.
Signed-off-by: Tom Warren
---
Changes for v2:
- None
arch/arm/include/asm/arch-tegra/tegra_mmc.h | 2 +-
drivers/mmc/tegra_mmc.c | 18 ++
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h
b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
index a8bfa46..70dcf4a 100644
--- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h
+++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
@@ -130,9 +130,9 @@ struct tegra_mmc {
/* SDMMC1/3 settings from SDMMCx Initialization Sequence of TRM */
#define MEMCOMP_PADCTRL_VREF 7
#define AUTO_CAL_ENABLE(1 << 29)
-#if defined(CONFIG_TEGRA210)
#define AUTO_CAL_ACTIVE(1 << 31)
#define AUTO_CAL_START (1 << 31)
+#if defined(CONFIG_TEGRA210)
#define AUTO_CAL_PD_OFFSET (0x7D << 8)
#define AUTO_CAL_PU_OFFSET (0 << 0)
#define IO_TRIM_BYPASS_MASK(1 << 2)
diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c
index 73ac58c..03110ba 100644
--- a/drivers/mmc/tegra_mmc.c
+++ b/drivers/mmc/tegra_mmc.c
@@ -376,6 +376,24 @@ static void tegra_mmc_change_clock(struct tegra_mmc_priv
*priv, uint clock)
rate = clk_set_rate(>clk, clock);
div = (rate + clock - 1) / clock;
+
+#if defined(CONFIG_TEGRA210)
+ if (priv->mmc_id == PERIPH_ID_SDMMC1 && clock <= 40) {
+ /* clock_adjust_periph_pll_div() chooses a 'bad' clock
+* on SDMMC1 T210, so skip it here and force a clock
+* that's been spec'd in the table in the TRM for
+* card-detect (400KHz).
+*/
+ uint effective_rate = clock_adjust_periph_pll_div(priv->mmc_id,
+ CLOCK_ID_PERIPH, 24727273, NULL);
+ div = 62;
+
+ debug("%s: WAR: Using SDMMC1 clock of %u, div %d to achieve
%dHz card clock ...\n",
+ __func__, effective_rate, div, clock);
+ } else
+ clock_adjust_periph_pll_div(priv->mmc_id, CLOCK_ID_PERIPH,
clock,
+ );
+#endif
debug("div = %d\n", div);
writew(0, >reg->clkcon);
--
1.8.2.1.610.g562af5b
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[PATCH 1/2] mmc: t210: Add autocal and tap/trim updates for SDMMC1/3
From: Tom Warren
As per the T210 TRM, when running at 3.3v, the SDMMC1 tap/trim and
autocal values need to be set to condition the signals correctly before
talking to the SD-card. This is the same as what's being done in CBoot,
but it gets reset when the SDMMC1 HW is soft-reset during SD driver
init, so needs to be repeated here. Also set autocal and tap/trim for
SDMMC3, although no T210 boards use it for SD-card at this time.
Signed-off-by: Tom Warren
---
Changes for v2:
- Added clocks.h include for TEGRA30 to fix T30 32-bit builds
arch/arm/include/asm/arch-tegra/tegra_mmc.h | 20 +--
drivers/mmc/tegra_mmc.c | 84 ++---
2 files changed, 92 insertions(+), 12 deletions(-)
diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h
b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
index a2b6f63..a8bfa46 100644
--- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h
+++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
@@ -2,7 +2,7 @@
/*
* (C) Copyright 2009 SAMSUNG Electronics
* Minkyu Kang
- * Portions Copyright (C) 2011-2012 NVIDIA Corporation
+ * Portions Copyright (C) 2011-2012,2019 NVIDIA Corporation
*/
#ifndef __TEGRA_MMC_H_
@@ -52,7 +52,7 @@ struct tegra_mmc {
unsigned char admaerr;/* offset 54h */
unsigned char res4[3];/* RESERVED, offset 55h-57h */
unsigned long admaaddr; /* offset 58h-5Fh */
- unsigned char res5[0xa0]; /* RESERVED, offset 60h-FBh */
+ unsigned char res5[0x9c]; /* RESERVED, offset 60h-FBh */
unsigned short slotintstatus; /* offset FCh */
unsigned short hcver; /* HOST Version */
unsigned intvenclkctl; /* _VENDOR_CLOCK_CNTRL_0,100h */
@@ -127,11 +127,23 @@ struct tegra_mmc {
#define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE(1 << 1)
-/* SDMMC1/3 settings from section 24.6 of T30 TRM */
+/* SDMMC1/3 settings from SDMMCx Initialization Sequence of TRM */
#define MEMCOMP_PADCTRL_VREF 7
-#define AUTO_CAL_ENABLED (1 << 29)
+#define AUTO_CAL_ENABLE(1 << 29)
+#if defined(CONFIG_TEGRA210)
+#define AUTO_CAL_ACTIVE(1 << 31)
+#define AUTO_CAL_START (1 << 31)
+#define AUTO_CAL_PD_OFFSET (0x7D << 8)
+#define AUTO_CAL_PU_OFFSET (0 << 0)
+#define IO_TRIM_BYPASS_MASK(1 << 2)
+#define TRIM_VAL_SHIFT 24
+#define TRIM_VAL_MASK (0x1F << TRIM_VAL_SHIFT)
+#define TAP_VAL_SHIFT 16
+#define TAP_VAL_MASK (0xFF << TAP_VAL_SHIFT)
+#else
#define AUTO_CAL_PD_OFFSET (0x70 << 8)
#define AUTO_CAL_PU_OFFSET (0x62 << 0)
+#endif
#endif /* __ASSEMBLY__ */
#endif /* __TEGRA_MMC_H_ */
diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c
index f022e93..73ac58c 100644
--- a/drivers/mmc/tegra_mmc.c
+++ b/drivers/mmc/tegra_mmc.c
@@ -3,7 +3,7 @@
* (C) Copyright 2009 SAMSUNG Electronics
* Minkyu Kang
* Jaehoon Chung
- * Portions Copyright 2011-2016 NVIDIA Corporation
+ * Portions Copyright 2011-2019 NVIDIA Corporation
*/
#include
@@ -15,6 +15,9 @@
#include
#include
#include
+#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA210)
+#include
+#endif
struct tegra_mmc_plat {
struct mmc_config cfg;
@@ -30,6 +33,7 @@ struct tegra_mmc_priv {
struct gpio_desc wp_gpio; /* Write Protect GPIO */
unsigned int version; /* SDHCI spec. version */
unsigned int clock; /* Current clock (MHz) */
+ int mmc_id; /* peripheral id */
};
static void tegra_mmc_set_power(struct tegra_mmc_priv *priv,
@@ -446,16 +450,19 @@ static int tegra_mmc_set_ios(struct udevice *dev)
static void tegra_mmc_pad_init(struct tegra_mmc_priv *priv)
{
-#if defined(CONFIG_TEGRA30)
+#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA210)
u32 val;
+ u16 clk_con;
+ int timeout;
+ int id = priv->mmc_id;
- debug("%s: sdmmc address = %08x\n", __func__, (unsigned int)priv->reg);
+ debug("%s: sdmmc address = %p, id = %d\n", __func__,
+ priv->reg, id);
/* Set the pad drive strength for SDMMC1 or 3 only */
- if (priv->reg != (void *)0x7800 &&
- priv->reg != (void *)0x78000400) {
+ if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) {
debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
- __func__);
+ __func__);
return;
}
@@ -464,11 +471,65 @@ static void tegra_mmc_pad_init(struct tegra_mmc_priv
*priv)
val |= MEMCOMP_PADCTRL_VREF;
writel(val, >reg->sdmemcmppadctl);
+ /* Disable SD Clock Enable before running auto-cal as per TRM */
+ clk_con = readw(>reg->clkcon);
+ debug("%s: CLOCK_CONTROL = 0x%04X\n", __func__, clk_con);
+ clk_con &= ~TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
+ writew(clk_con, >reg->clkcon);
+
val = readl(>reg->autocalcfg);
val &=
[PATCH 0/2 v2] mmc: t210: fix autocal and 400KHz clock
From: Tom Warren These two patches contain fixes for two issues found on T210 MMC during Nano bringup. Autocal wasn't being done correctly as per the TRM, and the 375/400KHz MMC card detect clock wasn't using the correct parameters as per the TRM. Tom Warren (2): mmc: t210: Add autocal and tap/trim updates for SDMMC1/3 mmc: t210: Fix 'bad' SD-card clock when doing 400KHz card detect arch/arm/include/asm/arch-tegra/tegra_mmc.h | 20 -- drivers/mmc/tegra_mmc.c | 102 +--- 2 files changed, 110 insertions(+), 12 deletions(-) -- 1.8.2.1.610.g562af5b --- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. ---
[PATCH] i2c: t210: Add VI_I2C clock source support
From: Tom Warren
Fix VI_I2C clock source type. Will be needed by VI_I2C driver.
Also added use of INTERNAL_ID macro in two places, needed to keep
the id returned to 8 bits.
Signed-off-by: Tom Warren
---
arch/arm/mach-tegra/tegra210/clock.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-tegra/tegra210/clock.c
b/arch/arm/mach-tegra/tegra210/clock.c
index f1b25e2..00c65c2 100644
--- a/arch/arm/mach-tegra/tegra210/clock.c
+++ b/arch/arm/mach-tegra/tegra210/clock.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * (C) Copyright 2013-2015
+ * (C) Copyright 2013-2020
* NVIDIA Corporation
*/
@@ -333,7 +333,7 @@ static enum clock_type_id clock_periph_type[PERIPHC_COUNT]
= {
TYPE(PERIPHC_DMIC3, CLOCK_TYPE_NONE),
TYPE(PERIPHC_APE, CLOCK_TYPE_NONE),
TYPE(PERIPHC_QSPI, CLOCK_TYPE_PC01C00_C42C41TC40),
- TYPE(PERIPHC_VI_I2C,CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_VI_I2C,CLOCK_TYPE_PC2CC3M_T16),
TYPE(PERIPHC_USB2_HSIC_TRK, CLOCK_TYPE_NONE),
TYPE(PERIPHC_PEX_SATA_USB_RX_BYP, CLOCK_TYPE_NONE),
@@ -739,7 +739,7 @@ int get_periph_clock_info(enum periph_id periph_id, int
*mux_bits,
if (!clock_periph_id_isvalid(periph_id))
return -1;
- internal_id = periph_id_to_internal_id[periph_id];
+ internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]);
if (!periphc_internal_id_isvalid(internal_id))
return -1;
@@ -765,7 +765,7 @@ enum clock_id get_periph_clock_id(enum periph_id periph_id,
int source)
if (!clock_periph_id_isvalid(periph_id))
return CLOCK_ID_NONE;
- internal_id = periph_id_to_internal_id[periph_id];
+ internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]);
if (!periphc_internal_id_isvalid(internal_id))
return CLOCK_ID_NONE;
--
1.8.2.1.610.g562af5b
---
This email message is for the sole use of the intended recipient(s) and may
contain
confidential information. Any unauthorized review, use, disclosure or
distribution
is prohibited. If you are not the intended recipient, please contact the
sender by
reply email and destroy all copies of the original message.
---
