Ported from u-boot-1.1.6 driver by Samsung.
Signed-off-by: Guennadi Liakhovetski [EMAIL PROTECTED]
---
drivers/mtd/nand/Makefile |1 +
drivers/mtd/nand/s3c64xx.c | 307
2 files changed, 308 insertions(+), 0 deletions(-)
create mode 100644 drivers/mtd/nand/s3c64xx.c
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 7bd22a0..236cf03 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -33,6 +33,7 @@ COBJS-y += nand_bbt.o
COBJS-y += nand_util.o
COBJS-y += fsl_upm.o
+COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/mtd/nand/s3c64xx.c b/drivers/mtd/nand/s3c64xx.c
new file mode 100644
index 000..162ec26
--- /dev/null
+++ b/drivers/mtd/nand/s3c64xx.c
@@ -0,0 +1,307 @@
+/*
+ * (C) Copyright 2006 DENX Software Engineering
+ *
+ * Implementation for U-Boot 1.1.6 by Samsung
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, [EMAIL PROTECTED]
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+
+#include nand.h
+#include s3c6400.h
+
+#include asm/io.h
+
+#ifdef CONFIG_NAND_SPL
+#define printf(arg...) do {} while (0)
+#endif
+
+/* Nand flash definition values by jsgood */
+#ifdef S3C_NAND_DEBUG
+/*
+ * Function to print out oob buffer for debugging
+ * Written by jsgood
+ */
+static void print_oob(const char *header, struct mtd_info *mtd)
+{
+ int i;
+ struct nand_chip *chip = mtd-priv;
+
+ printf(%s:\t, header);
+
+ for (i = 0; i 64; i++)
+ printf(%02x , chip-oob_poi[i]);
+
+ printf(\n);
+}
+#endif /* S3C_NAND_DEBUG */
+
+#ifdef CONFIG_NAND_SPL
+static u_char nand_read_byte(struct mtd_info *mtd)
+{
+ struct nand_chip *this = mtd-priv;
+ return readb(this-IO_ADDR_R);
+}
+
+static void nand_write_byte(struct mtd_info *mtd, u_char byte)
+{
+ struct nand_chip *this = mtd-priv;
+ writeb(byte, this-IO_ADDR_W);
+}
+
+static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
+ int i;
+ struct nand_chip *this = mtd-priv;
+
+ for (i = 0; i len; i++)
+ buf[i] = readb(this-IO_ADDR_R);
+}
+#endif
+
+static void s3c_nand_select_chip(struct mtd_info *mtd, int chip)
+{
+ int ctrl = readl(NFCONT);
+
+ switch (chip) {
+ case -1:
+ ctrl |= 6;
+ break;
+ case 0:
+ ctrl = ~2;
+ break;
+ case 1:
+ ctrl = ~4;
+ break;
+ default:
+ return;
+ }
+
+ writel(ctrl, NFCONT);
+}
+
+/*
+ * Hardware specific access to control-lines function
+ * Written by jsgood
+ */
+static void s3c_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+{
+ struct nand_chip *this = mtd-priv;
+
+ switch (cmd) {
+ case NAND_CTL_SETCLE:
+ this-IO_ADDR_W = (void __iomem *)NFCMMD;
+ break;
+ case NAND_CTL_CLRCLE:
+ this-IO_ADDR_W = (void __iomem *)NFDATA;
+ break;
+ case NAND_CTL_SETALE:
+ this-IO_ADDR_W = (void __iomem *)NFADDR;
+ break;
+ case NAND_CTL_CLRALE:
+ this-IO_ADDR_W = (void __iomem *)NFDATA;
+ break;
+ case NAND_CTL_SETNCE:
+ s3c_nand_select_chip(mtd, 0);
+ break;
+ case NAND_CTL_CLRNCE:
+ s3c_nand_select_chip(mtd, -1);
+ break;
+ }
+}
+
+/*
+ * Function for checking device ready pin
+ * Written by jsgood
+ */
+static int s3c_nand_device_ready(struct mtd_info *mtdinfo)
+{
+ while (!(readl(NFSTAT) NFSTAT_RnB)) {}
+ return 1;
+}
+
+#ifdef CFG_S3C_NAND_HWECC
+/*
+ * This function is called before encoding ecc codes to ready ecc engine.
+ * Written by jsgood
+ */
+static void s3c_nand_enable_hwecc(struct mtd_info *mtd, int mode)
+{
+ u_long nfcont, nfconf;
+
+ /*
+* The original driver used 4-bit ECC for new MLC chips, i.e., for
+* those with non-zero ID[3][3:2], which anyway only holds for ST
+* (Numonyx) chips
+*/
+ nfconf = readl(NFCONF) ~NFCONF_ECC_4BIT;
+
+
