Location: Chandler, AZ Duration: 3 Months
Rate: 65/hr *Years of Experience & Expertise Level: 10yrs.; Sr. Level*** * *** *Project Description:*** USB Design block integration, validation and qualified for all freeze requirements. *Daily Responsibilities:*** RTL modification, unit and full chip regression and debug, test writing, synthesis timing closure and all aspects of design qualification for tape out. *Necessary Skills (Must Have):*** Proven USB design ownership, proficiency in Verilog and front end design processes such as synthesis, GLS, spyglass etc. sufficient to meet all design requirements for freeze criteria. Record of design block ownership to meet milestones and schedule requirements. *Additional Skills Desired (Nice to Have):*** Familiarity with Intel chipset validation environment and DFX, post-silicon debug. -- Thanks & Regards Kevin Maripax Solutions | ke...@maripax.com www.Maripax.com --~--~---------~--~----~------------~-------~--~----~ You received this message because you are subscribed to the Google Groups "US_IT.Groups" group. To post to this group, send email to us_itgroups@googlegroups.com To unsubscribe from this group, send email to us_itgroups+unsubscr...@googlegroups.com For more options, visit this group at http://groups.google.co.in/group/us_itgroups?hl=en -~----------~----~----~----~------~----~------~--~---
