Re: stm32 external SRAM
On 18/06/2019 07:17, Jython wrote:
> void SRAM_fsmc_setup(void)
> {
> unsigned char FSMC_Bank;
> int i = 0;
>
> // enable port clk
> RCC_AHB1ENR |= 0x0f << 3;
> RCC_AHB3ENR |= 1; // enable fsmc clock
>
> // af A0-A18
> stm32f4_gpio_config temp = STM32F4_PIN_FSMC(5, 0,
> STM32F4_GPIO_AF_FSMC);
>
>
> for(i = 0; i < 6; i++) //pf0-5
> {
>
>
> temp.fields.pin_first = STM32F4_GPIO_PIN(5, i);
> temp.fields.pin_last = STM32F4_GPIO_PIN(5, i);
> stm32f4_gpio_set_config(&temp);
> }
>
> // A6 PF12
> temp.fields.pin_first = STM32F4_GPIO_PIN(5, 12);
> temp.fields.pin_last = STM32F4_GPIO_PIN(5, 12);
> stm32f4_gpio_set_config(&temp);
>
> // A7 PF13
> temp.fields.pin_first = STM32F4_GPIO_PIN(5, 13);
> temp.fields.pin_last = STM32F4_GPIO_PIN(5, 13);
> stm32f4_gpio_set_config(&temp);
>
> // A8 PF14
> temp.fields.pin_first = STM32F4_GPIO_PIN(5, 14);
> temp.fields.pin_last = STM32F4_GPIO_PIN(5, 14);
> stm32f4_gpio_set_config(&temp);
>
> // A9 PF15
> temp.fields.pin_first = STM32F4_GPIO_PIN(5, 15);
> temp.fields.pin_last = STM32F4_GPIO_PIN(5, 15);
> stm32f4_gpio_set_config(&temp);
>
>
> // PG0-5 A10-A15
> for(i = 0; i < 6; i++)
> {
> temp.fields.pin_first = STM32F4_GPIO_PIN(6, i);
> temp.fields.pin_last = STM32F4_GPIO_PIN(6, i);
> stm32f4_gpio_set_config(&temp);
>
> }
>
>
> // a16 - pd11
> temp.fields.pin_first = STM32F4_GPIO_PIN(3, 11);
> temp.fields.pin_last = STM32F4_GPIO_PIN(3, 11);
> stm32f4_gpio_set_config(&temp);
>
> //A17
> temp.fields.pin_first = STM32F4_GPIO_PIN(3, 12);
> temp.fields.pin_last = STM32F4_GPIO_PIN(3, 12);
> stm32f4_gpio_set_config(&temp);
> //A18
> temp.fields.pin_first = STM32F4_GPIO_PIN(3, 13);
> temp.fields.pin_last = STM32F4_GPIO_PIN(3, 13);
> stm32f4_gpio_set_config(&temp);
>
> // address bus end
>
>
> // dbus setting
> // D0 PD14
> temp.fields.pin_first = STM32F4_GPIO_PIN(3, 14);
> temp.fields.pin_last = STM32F4_GPIO_PIN(3, 14);
> stm32f4_gpio_set_config(&temp);
>
> // D1 PD15
> temp.fields.pin_first = STM32F4_GPIO_PIN(3, 15);
> temp.fields.pin_last = STM32F4_GPIO_PIN(3, 15);
> stm32f4_gpio_set_config(&temp);
>
> // D2 PD0
> temp.fields.pin_first = STM32F4_GPIO_PIN(3, 0);
> temp.fields.pin_last = STM32F4_GPIO_PIN(3, 0);
> stm32f4_gpio_set_config(&temp);
>
> // D3 PD1
> temp.fields.pin_first = STM32F4_GPIO_PIN(3, 1);
> temp.fields.pin_last = STM32F4_GPIO_PIN(3, 1);
> stm32f4_gpio_set_config(&temp);
>
> // D4-12 Pe7
> for(i = 4; i < 13; i++)
> {
> temp.fields.pin_first = STM32F4_GPIO_PIN(4, i+3);
> temp.fields.pin_last = STM32F4_GPIO_PIN(4, i+3);
> stm32f4_gpio_set_config(&temp);
> }
>
> // d13 14 15 pd8
> for(i = 13; i < 16; i++)
> {
> temp.fields.pin_first = STM32F4_GPIO_PIN(3, i-5);
> temp.fields.pin_last = STM32F4_GPIO_PIN(3, i-5);
> stm32f4_gpio_set_config(&temp);
>
> }
>
>
> //pg10 ne3
> temp.fields.pin_first = STM32F4_GPIO_PIN(6, 10);
> temp.fields.pin_last = STM32F4_GPIO_PIN(6, 10);
> stm32f4_gpio_set_config(&temp);
>
> //NBL pe0 pe1
> temp.fields.pin_first = STM32F4_GPIO_PIN(4, 0);
> temp.fields.pin_last = STM32F4_GPIO_PIN(4, 0);
> stm32f4_gpio_set_config(&temp);
>
> temp.fields.pin_first = STM32F4_GPIO_PIN(4, 1);
> temp.fields.pin_last = STM32F4_GPIO_PIN(4, 1);
> stm32f4_gpio_set_config(&temp);
>
> //pd4 NOE
> temp.fields.pin_first = STM32F4_GPIO_PIN(3, 4);
> temp.fields.pin_last = STM32F4_GPIO_PIN(3, 4);
> stm32f4_gpio_set_config(&temp);
>
> //pd5 NWE
> temp.fields.pin_first = STM32F4_GPIO_PIN(3, 5);
> temp.fields.pin_last = STM32F4_GPIO_PIN(3, 5);
> stm32f4_gpio_set_config(&temp);
>
> //pd6 NWAIT
> temp.fields.pin_first = STM32F4_GPIO_PIN(3, 6);
> temp.fields.pin_last = STM32F4_GPIO_PIN(3, 6);
> stm32f4_gpio_set_config(&temp);
>
>
>
> //The SRAM is connected to the second FSMC BANK (NE2)
> FSMC_Bank = 1;
>
> STM32_FSMC_BCR3 |= 1<<12;
> STM32_FSMC_BCR3 |= 1<<4; //16bit
>
> //
> STM32_FSMC_BTR3 |= 1<<8; // Data-phase duration DATAST
> //STM32_FSMC_BTR3 |= ~(uint32_t)(1<<4);
> //STM32_FSMC_BTR3 &= ~(uint32_t)1;
> STM32_FSMC_BTR3 &= 0xff00;
>
>
> STM32_F
Re: stm32 external SRAM
>
> void SRAM_fsmc_setup(void)
> {
> unsigned char FSMC_Bank;
> int i = 0;
>
> // enable port clk
> RCC_AHB1ENR |= 0x0f << 3;
> RCC_AHB3ENR |= 1; // enable fsmc clock
>
> // af A0-A18
> stm32f4_gpio_config temp = STM32F4_PIN_FSMC(5, 0,
> STM32F4_GPIO_AF_FSMC);
>
>
> for(i = 0; i < 6; i++) //pf0-5
> {
>
>
> temp.fields.pin_first = STM32F4_GPIO_PIN(5, i);
> temp.fields.pin_last = STM32F4_GPIO_PIN(5, i);
> stm32f4_gpio_set_config(&temp);
> }
>
> // A6 PF12
> temp.fields.pin_first = STM32F4_GPIO_PIN(5, 12);
> temp.fields.pin_last = STM32F4_GPIO_PIN(5, 12);
> stm32f4_gpio_set_config(&temp);
>
> // A7 PF13
> temp.fields.pin_first = STM32F4_GPIO_PIN(5, 13);
> temp.fields.pin_last = STM32F4_GPIO_PIN(5, 13);
> stm32f4_gpio_set_config(&temp);
>
> // A8 PF14
> temp.fields.pin_first = STM32F4_GPIO_PIN(5, 14);
> temp.fields.pin_last = STM32F4_GPIO_PIN(5, 14);
> stm32f4_gpio_set_config(&temp);
>
> // A9 PF15
> temp.fields.pin_first = STM32F4_GPIO_PIN(5, 15);
> temp.fields.pin_last = STM32F4_GPIO_PIN(5, 15);
> stm32f4_gpio_set_config(&temp);
>
>
> // PG0-5A10-A15
> for(i = 0; i < 6; i++)
> {
> temp.fields.pin_first = STM32F4_GPIO_PIN(6, i);
> temp.fields.pin_last = STM32F4_GPIO_PIN(6, i);
> stm32f4_gpio_set_config(&temp);
>
> }
>
>
> // a16 - pd11
> temp.fields.pin_first = STM32F4_GPIO_PIN(3, 11);
> temp.fields.pin_last = STM32F4_GPIO_PIN(3, 11);
> stm32f4_gpio_set_config(&temp);
>
> //A17
> temp.fields.pin_first = STM32F4_GPIO_PIN(3, 12);
> temp.fields.pin_last = STM32F4_GPIO_PIN(3, 12);
> stm32f4_gpio_set_config(&temp);
> //A18
> temp.fields.pin_first = STM32F4_GPIO_PIN(3, 13);
> temp.fields.pin_last = STM32F4_GPIO_PIN(3, 13);
> stm32f4_gpio_set_config(&temp);
>
> // address bus end
>
>
> // dbus setting
> // D0 PD14
> temp.fields.pin_first = STM32F4_GPIO_PIN(3, 14);
> temp.fields.pin_last = STM32F4_GPIO_PIN(3, 14);
> stm32f4_gpio_set_config(&temp);
>
> // D1 PD15
> temp.fields.pin_first = STM32F4_GPIO_PIN(3, 15);
> temp.fields.pin_last = STM32F4_GPIO_PIN(3, 15);
> stm32f4_gpio_set_config(&temp);
>
> // D2 PD0
> temp.fields.pin_first = STM32F4_GPIO_PIN(3, 0);
> temp.fields.pin_last = STM32F4_GPIO_PIN(3, 0);
> stm32f4_gpio_set_config(&temp);
>
> // D3 PD1
> temp.fields.pin_first = STM32F4_GPIO_PIN(3, 1);
> temp.fields.pin_last = STM32F4_GPIO_PIN(3, 1);
> stm32f4_gpio_set_config(&temp);
>
> // D4-12 Pe7
> for(i = 4; i < 13; i++)
> {
> temp.fields.pin_first = STM32F4_GPIO_PIN(4, i+3);
> temp.fields.pin_last = STM32F4_GPIO_PIN(4, i+3);
> stm32f4_gpio_set_config(&temp);
> }
>
> // d13 14 15 pd8
> for(i = 13; i < 16; i++)
> {
> temp.fields.pin_first = STM32F4_GPIO_PIN(3, i-5);
> temp.fields.pin_last = STM32F4_GPIO_PIN(3, i-5);
> stm32f4_gpio_set_config(&temp);
>
> }
>
>
> //pg10 ne3
> temp.fields.pin_first = STM32F4_GPIO_PIN(6, 10);
> temp.fields.pin_last = STM32F4_GPIO_PIN(6, 10);
> stm32f4_gpio_set_config(&temp);
>
> //NBL pe0 pe1
> temp.fields.pin_first = STM32F4_GPIO_PIN(4, 0);
> temp.fields.pin_last = STM32F4_GPIO_PIN(4, 0);
> stm32f4_gpio_set_config(&temp);
>
> temp.fields.pin_first = STM32F4_GPIO_PIN(4, 1);
> temp.fields.pin_last = STM32F4_GPIO_PIN(4, 1);
> stm32f4_gpio_set_config(&temp);
>
> //pd4 NOE
> temp.fields.pin_first = STM32F4_GPIO_PIN(3, 4);
> temp.fields.pin_last = STM32F4_GPIO_PIN(3, 4);
> stm32f4_gpio_set_config(&temp);
>
> //pd5 NWE
> temp.fields.pin_first = STM32F4_GPIO_PIN(3, 5);
> temp.fields.pin_last = STM32F4_GPIO_PIN(3, 5);
> stm32f4_gpio_set_config(&temp);
>
> //pd6 NWAIT
> temp.fields.pin_first = STM32F4_GPIO_PIN(3, 6);
> temp.fields.pin_last = STM32F4_GPIO_PIN(3, 6);
> stm32f4_gpio_set_config(&temp);
>
>
>
> //The SRAM is connected to the second FSMC BANK (NE2)
> FSMC_Bank = 1;
>
> STM32_FSMC_BCR3 |= 1<<12;
> STM32_FSMC_BCR3 |= 1<<4; //16bit
>
> //
> STM32_FSMC_BTR3 |= 1<<8; // Data-phase duration DATAST
> //STM32_FSMC_BTR3 |= ~(uint32_t)(1<<4);
> //STM32_FSMC_BTR3 &= ~(uint32_t)1;
> STM32_FSMC_BTR3 &= 0xff00;
>
>
> STM32_FSMC_BWTR3 = 0x0FFF;
> STM32_FSMC_BCR3 |= 1; //memory bank enable
>
> #if 0
> /
> FSMC_Bank1->BTCR[FSMC_Bank+1] = (FSMC_BTR2_ADDSET_1) | (FSMC_BTR2_DATAST_0
> | FSMC_BTR2_DATAST_1);
>
>
>
> #endif
> }
it is my later application code, i will try it , thanks!
On Tue, Jun 18, 2019 at 1:09 PM Christian Mauderer <
christian.maude...@embedded-brains.de> wrote:
> On 18/06/2019 03:25, Jython wrote:
> > my linkscmd is
> https://gist.github.com/goog/aad6dae4c418255dd6fb2b23bf2e6f08
> >
> > void BSP_START_TEXT_SECTION bsp_start_hook_1(void)
> > {
> > SRAM_fsmc_setup();
Re: stm32 external SRAM
On 18/06/2019 03:25, Jython wrote:
> my linkscmd is https://gist.github.com/goog/aad6dae4c418255dd6fb2b23bf2e6f08
>
> void BSP_START_TEXT_SECTION bsp_start_hook_1(void)
> {
> SRAM_fsmc_setup();
> bsp_start_copy_sections();
> bsp_start_clear_bss();
>
> /* At this point we can use objects outside the .start section */
> }
>
>
> but now my code run disordered
Which one?
The SRAM_fsmc_setup()? In that case please note that you are in a very
early initialization step. So most system services won't work and global
variables are not initialized yet.
Or your later application code? In that case: Did you do a memory test
to check your RAM initialization? For example the routines from Michael
Barr from here work well:
http://www.esacademy.com/en/library/technical-articles-and-documents/miscellaneous/software-based-memory-testing.html
>
> On Mon, Jun 17, 2019 at 2:45 PM Christian Mauderer
> > wrote:
>
> If you put any sections into the external RAM that need initialization,
> you have to init the RAM before the BSP copies it's sections. The STM32
> BSP copies it's sections in bsp_start_hook_1(). So either put it in
> bsp_start_hook_0 or in bsp_start_hook_1 before the copy_section calls.
> Attention: You can't use much in these functions. They are in a very
> early initialization stage. So be careful what you put there.
>
> If you only want malloc to allocate memory from there, there might is a
> later point where you can do that.
>
> On 17/06/2019 08:32, Jython wrote:
> > Thank you and the example! that is to say put extern sram init in
> > bsp_start( void ) function?
> >
> > On Mon, Jun 17, 2019 at 1:04 PM Christian Mauderer
> >
> > >> wrote:
> >
> > On 17/06/2019 03:05, Jython wrote:
> > > STM32:
> > > 112KB at 2000
> > > 16KB at 2001 C000
> > >
> > > external sram : 1MB at 0x6800
> > >
> > > does MEMORY layout support RAM2?
> >
> > Hello Jython,
> >
> > you can distribute the regions to the two RAMs. For example
> this BSP
> > does that:
> >
> >
>
> https://git.rtems.org/rtems/tree/bsps/arm/lpc32xx/start/linkcmds.lpc32xx_phycore
> >
> > Please note that you have to take a detailed look at what is
> used till
> > your external RAM initialization run and what not. But if you
> put your
> > external RAM initialization in an early enough step, you
> shouldn't get
> > problems with that.
> >
> > Best regards
> >
> > Christian
> >
> > >
> > > On Fri, Jun 14, 2019 at 10:13 PM Christian Mauderer
> > >
> > >
> > >
> > > >
> > > If you have already added the chip and it is initialized
> > during startup,
> > > you most likely have to add a section for it in your linker
> > command
> > > file. Depending on where your internal RAM is located and
> > where the
> > > external one is: If they are continuous that can be enough.
> > >
> > > Best regards
> > >
> > > Christian
> > >
> > > On 14/06/2019 04:42, Jython wrote:
> > > > we have added 1M ram by FSMC, and want to manage it by
> > system malloc
> > > > controler
> > > >
> > > > On Fri, Jun 14, 2019 at 10:26 AM Mr. Andrei Chichak
> > > mailto:gro...@chichak.ca>
> >
> >
> >>
> > > >
> >
> >
> wrote:
> > > >
> > > > A 407 doesn’t normally have external RAM.
> > > >
> > > > ARMs have flash at 0 and the 407 has RAM at 0x2000
>
> > as you
> > > > discussed earlier.
> > > >
> > > > If you want to work with external flash or RAM,
> you have
Re: stm32 external SRAM
my linkscmd is https://gist.github.com/goog/aad6dae4c418255dd6fb2b23bf2e6f08
void BSP_START_TEXT_SECTION bsp_start_hook_1(void)
> {
> SRAM_fsmc_setup();
> bsp_start_copy_sections();
> bsp_start_clear_bss();
>
> /* At this point we can use objects outside the .start section */
> }
>
but now my code run disordered
On Mon, Jun 17, 2019 at 2:45 PM Christian Mauderer <
christian.maude...@embedded-brains.de> wrote:
> If you put any sections into the external RAM that need initialization,
> you have to init the RAM before the BSP copies it's sections. The STM32
> BSP copies it's sections in bsp_start_hook_1(). So either put it in
> bsp_start_hook_0 or in bsp_start_hook_1 before the copy_section calls.
> Attention: You can't use much in these functions. They are in a very
> early initialization stage. So be careful what you put there.
>
> If you only want malloc to allocate memory from there, there might is a
> later point where you can do that.
>
> On 17/06/2019 08:32, Jython wrote:
> > Thank you and the example! that is to say put extern sram init in
> > bsp_start( void ) function?
> >
> > On Mon, Jun 17, 2019 at 1:04 PM Christian Mauderer
> > > > wrote:
> >
> > On 17/06/2019 03:05, Jython wrote:
> > > STM32:
> > > 112KB at 2000
> > > 16KB at 2001 C000
> > >
> > > external sram : 1MB at 0x6800
> > >
> > > does MEMORY layout support RAM2?
> >
> > Hello Jython,
> >
> > you can distribute the regions to the two RAMs. For example this BSP
> > does that:
> >
> >
> https://git.rtems.org/rtems/tree/bsps/arm/lpc32xx/start/linkcmds.lpc32xx_phycore
> >
> > Please note that you have to take a detailed look at what is used
> till
> > your external RAM initialization run and what not. But if you put
> your
> > external RAM initialization in an early enough step, you shouldn't
> get
> > problems with that.
> >
> > Best regards
> >
> > Christian
> >
> > >
> > > On Fri, Jun 14, 2019 at 10:13 PM Christian Mauderer
> > > >
> > > > >> wrote:
> > >
> > > If you have already added the chip and it is initialized
> > during startup,
> > > you most likely have to add a section for it in your linker
> > command
> > > file. Depending on where your internal RAM is located and
> > where the
> > > external one is: If they are continuous that can be enough.
> > >
> > > Best regards
> > >
> > > Christian
> > >
> > > On 14/06/2019 04:42, Jython wrote:
> > > > we have added 1M ram by FSMC, and want to manage it by
> > system malloc
> > > > controler
> > > >
> > > > On Fri, Jun 14, 2019 at 10:26 AM Mr. Andrei Chichak
> > > mailto:gro...@chichak.ca>
> > >
> > > >
> > > > >
> > > > A 407 doesn’t normally have external RAM.
> > > >
> > > > ARMs have flash at 0 and the 407 has RAM at 0x2000
> > as you
> > > > discussed earlier.
> > > >
> > > > If you want to work with external flash or RAM, you have
> > to set up
> > > > the FSMC or FMC to support it, but that isn’t a part of
> > the dev
> > > > board that Sebastian used for the BSP port.
> > > >
> > > > The external memory is going to be very specific to your
> > board.
> > > > Which board are you working with?
> > > >
> > > > A
> > > >
> > > > > On 2019-June-13, at 06:23, Christian Mauderer
> > > > >
> > > > >
> > > > >
> > > > > > > >
> > > > > On 05/06/2019 02:55, Jython wrote:
> > > > >> Hello!
> > > > >>
> > > > >> 2. In the normal (non-debugging) case, the linker
> > > script still
> > > > >>places the
> > > > >>
> > > > >>.text section near zero, but places the start of
> the
> > > .data and
> > > > .bss
> > > > >>sections at the start location of the MPC555's
> > internal
> > > RAM. The
> > > > >>system startup code th
Re: gdb-8.2.1 build failed on macos 10.11.6
On 17/6/19 5:48 pm, Jiri Gaisler wrote: > I don't know if it is of any help, but I managed to build gdb-8.2.1 on > MacOSX 10.10 using gcc-9. The trick was to install gcc with 'brew > install gcc', and then configure and compile with CC=gcc-9 and CXX=g++-9 > . I'm doing this in a KVM virtual machine, but I don't think it matters. > The resulting gdb binary worked fine. I am now trying to build the whole > tool-chain with RSB ... Thanks, it is great to know this can be done. What I am not sure about is how to build with Xocde's clang on a "latest" or "current" system or with gcc on older systems we know have problems. Do we need to add to darwin.py a way to specify versions of MacOS and clang which are known to be broken and to automatically switch to gcc if present or raise an error if gcc is not found? My policy for MacOS is building current RSB tools on current MacOS + Xcode versions. I do not have the time or means to support testing two separate packaging systems and their updates. I have found in the past a library installed for some other package may break a build of our tools. Sometimes the presence of a library can trigger a different configure path and this exposes things not normally seen. It would be good to support older MacOS versions if we have active users. Can we say for a clang < 10 we attempt to use gcc? I will need some help with selecting the versions we need. Chris ___ users mailing list users@rtems.org http://lists.rtems.org/mailman/listinfo/users
Re: BeagleBone Black Networking (wifi and/or wired)
On 18/6/19 2:56 am, Gedare Bloom wrote: > On Sat, Jun 8, 2019 at 8:25 PM Chris Johns wrote: >> >> On 8/6/19 1:45 am, Christian Mauderer wrote: >>> Note that basically all device tree files that I have found yet are forked >>> from the Linux ones. >> >> Yes, I understand this is the case. >> >>> They are all GPL. >> >> We need to work with these files and respect the license they are under. I >> think >> GPL DTS is OK if these files are not linked into an executable. I am not sure >> where you stand in relation to the GPL license if you link a GPL dtb into an >> executable. An overlay we create under a suitable license should be fine. >> > > If you apply the overlay using host tools, then the license > implications are problematic since you will be distributing a binary > program that is combining GPL code, the entire image comes under GPL. > Building the overlay online is more defensible, since you can > distribute the dtb separately. I agree. Chris ___ users mailing list users@rtems.org http://lists.rtems.org/mailman/listinfo/users
Re: BeagleBone Black Networking (wifi and/or wired)
On Sat, Jun 8, 2019 at 8:25 PM Chris Johns wrote: > > On 8/6/19 1:45 am, Christian Mauderer wrote: > > Note that basically all device tree files that I have found yet are forked > > from the Linux ones. > > Yes, I understand this is the case. > > > They are all GPL. > > We need to work with these files and respect the license they are under. I > think > GPL DTS is OK if these files are not linked into an executable. I am not sure > where you stand in relation to the GPL license if you link a GPL dtb into an > executable. An overlay we create under a suitable license should be fine. > If you apply the overlay using host tools, then the license implications are problematic since you will be distributing a binary program that is combining GPL code, the entire image comes under GPL. Building the overlay online is more defensible, since you can distribute the dtb separately. > > I think it was Sichen Zhao during 2017 GSoC who wanted to add some to the > > RTEMS repository and it has been rejected due to the license. > > I remember and I still think the position discussed is fine. > > > I don't really object to adding them somewhere. > > What do we host and maintain? Do we need to host any of these files or should > we > have a tool to collect and/or generate the blobs we need. > > > But we should think exactly about where we want that stuff. > > Having a blob as a file in a system theoretically lets someone update it. The > `dtc` compiler can generate the dts source from a blob so a user can recover > the > source, make a change, generate a blob, then return it back into a system if > they wish too. > > What about building the FDT blobs we need with the RSB? I know this will work > on > FreeBSD and I suspect Linux, MacOS has some issues with clang's cpp. > > Chris > ___ > users mailing list > users@rtems.org > http://lists.rtems.org/mailman/listinfo/users ___ users mailing list users@rtems.org http://lists.rtems.org/mailman/listinfo/users
Re: gdb-8.2.1 build failed on macos 10.11.6
I don't know if it is of any help, but I managed to build gdb-8.2.1 on MacOSX 10.10 using gcc-9. The trick was to install gcc with 'brew install gcc', and then configure and compile with CC=gcc-9 and CXX=g++-9 . I'm doing this in a KVM virtual machine, but I don't think it matters. The resulting gdb binary worked fine. I am now trying to build the whole tool-chain with RSB ... brew install gcc export CC=gcc-9 export CXX=g++-9 ../gdb-8.2.1/configure --target=sparc-rtems make -j2 Jiri. On 6/17/19 7:30 AM, Chris Johns wrote: > On 17/6/19 5:31 am, Juan Rafael García Blanco wrote: >> Hi, >> >> I have installed macOS 10.9.5, for which Xcode includes the following >> compiler: >> Apple LLVM version 6.0 (clang-600.0.57) (based on LLVM 3.5svn) >> Target: x86_64-apple-darwin13.4.0 >> Thread model: posix >> >> Compilation of gdb 8.2 fails also with this setup, although the error seems >> to be caused by the compiler itself. Please find below the error log: >> CXXcli/cli-script.o >> Stack dump: >> 0. Program arguments: >> /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/bin/clang >> -cc1 -triple x86_64-apple-macosx10.9.0 -emit-obj -disable-fr\ >> ee -disable-llvm-verifier -main-file-name cli-script.c -mrelocation-model >> pic -pic-level 2 -mdisable-fp-elim -masm-verbose -munwind-tables -target-cpu >> core2 -target-linker-version \ >> 241.9 -gdwarf-2 -coverage-file >> /Users/juanrgar/Projects/rtems/src/rsb/rtems/build/sparc-rtems5-gdb-8.2.1-x86_64-apple-darwin13.4.0-1/build/gdb/cli/cli-script.o >> -resource-dir /Appli\ >> cations/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/bin/../lib/clang/6.0 >> -dependency-file cli/.deps/cli-script.Tpo -MP -MT cli/cli-script.o -D >> LOCALEDIR="/\ >> Users/juanrgar/Projects/rtems/rtems/5/share/locale" -D HAVE_CONFIG_H -D >> TUI=1 -I >> /Users/juanrgar/Projects/rtems/src/rsb/rtems/build/tmp/sb-juanrgar/5/rtems-sparc/Users/juanrgar/Pro\ >> jects/rtems/rtems/5/include -I . -I ../../gdb-8.2.1/gdb -I >> ../../gdb-8.2.1/gdb/common -I ../../gdb-8.2.1/gdb/config -I >> ../../gdb-8.2.1/gdb/../include/opcode -I ../../gdb-8.2.1/gdb/\ >> ../opcodes/.. -I ../../gdb-8.2.1/gdb/../readline/.. -I >> ../../gdb-8.2.1/gdb/../zlib -I ../bfd -I ../../gdb-8.2.1/gdb/../bfd -I >> ../../gdb-8.2.1/gdb/../include -I ../libdecnumber -I .\ >> ./../gdb-8.2.1/gdb/../libdecnumber -I ../../gdb-8.2.1/gdb/gnulib/import -I >> build-gnulib/import -I >> /Users/juanrgar/Projects/rtems/src/rsb/rtems/build/tmp/sb-juanrgar/5/rtems-sparc/U\ >> sers/juanrgar/Projects/rtems/rtems/5/include -I >> /opt/local/Library/Frameworks/Python.framework/Versions/3.7/include/python3.7m >> -I /opt/local/Library/Frameworks/Python.framework/Ver\ >> sions/3.7/include/python3.7m -stdlib=libc++ -O2 -Wall -Wpointer-arith >> -Wno-unused -Wunused-value -Wunused-function -Wno-switch >> -Wno-char-subscripts -Wempty-body -Wno-sign-compare -\ >> Wno-narrowing -Wno-mismatched-tags -Wno-error=deprecated-register >> -Wformat-nonliteral -std=gnu++11 -fdeprecated-macro -fdebug-compilation-dir >> /Users/juanrgar/Projects/rtems/src/rsb\ >> /rtems/build/sparc-rtems5-gdb-8.2.1-x86_64-apple-darwin13.4.0-1/build/gdb >> -fbracket-depth 1024 -ferror-limit 19 -fmessage-length 0 -stack-protector 1 >> -mstackrealign -fblocks -fobjc\ >> -runtime=macosx-10.9.0 -fencode-extended-block-signature -fcxx-exceptions >> -fexceptions -fdiagnostics-show-option -vectorize-loops -vectorize-slp -o >> cli/cli-script.o -x c++ ../../gd\ >> b-8.2.1/gdb/cli/cli-script.c >> 1. parser at end of file >> 2. Per-module optimization passes >> 3. Running pass 'CallGraph Pass Manager' on module >> '../../gdb-8.2.1/gdb/cli/cli-script.c'. >> 4. Running pass 'SROA' on function >> '@_Z16get_command_line20command_control_typePKc' >> CXXcli/cli-setshow.o >> clang: error: unable to execute command: Segmentation fault: 11 >> clang: error: clang frontend command failed due to signal (use -v to see >> invocation) > That is not nice. I have raised issues like this with Apple in the past which > they have fixed but given the age of these tools I do not think they will fix > them. > > I am not sure how we handle these older versions of MacOS with gdb now being > written in C++. Any suggestions? > > (I think gdb being written in C++ is a good thing and I support the change) > > Chris > ___ > users mailing list > users@rtems.org > http://lists.rtems.org/mailman/listinfo/users ___ users mailing list users@rtems.org http://lists.rtems.org/mailman/listinfo/users
