[USRP-users] Fwd: Re: Digital TV Clock recovery using N310 and GNUradio
Hey Daniel,Right now I'm setting an externally generated clock to a nearby frequency and recording the data to file for later processing. I'd like the LOs to be disciplined to the recovered clock (I have a clock splitter already). I suppose I'm most curious to see what GNUradio blocks people have had success with in similar applications-MarkSent from my Verizon, Samsung Galaxy smartphone Original message From: Daniel Jepson Date: 7/22/19 3:00 PM (GMT-08:00) To: Mark Wagner Cc: Usrp Users Subject: Re: [USRP-users] Digital TV Clock recovery using N310 and GNUradio Hi Mark,A few questions: Is your clock recovery algorithm running in the FPGA? Do you require the sample clock/LOs to be disciplined to this recovered clock?While the N310 does not have a dedicated clock output port, if the recovered clock is internal to the FPGA you can transmit a copy of it out the front panel GPIO port and (with a bit of creativity) possibly cable it into another N310. Just watch your voltage level compatibility.-DanielOn Mon, Jul 22, 2019 at 4:38 PM Mark Wagner via USRP-users wrote:Hey all,I'd like to recover the clock tone of a digital TV signal on one USRP N310 and use it as the clock input to another N310. Does anyone have experience doing something like this? I could use some pointers.-Mark-- Mark WagnerUniversity of California San DiegoElectrical and Computer Engineering ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com -- Daniel Jepson Digital Hardware Engineer National Instruments O: +1.512.683.6163 daniel.jep...@ni.com ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] Digital TV Clock recovery using N310 and GNUradio
Hi Mark, A few questions: Is your clock recovery algorithm running in the FPGA? Do you require the sample clock/LOs to be disciplined to this recovered clock? While the N310 does not have a dedicated clock output port, if the recovered clock is internal to the FPGA you can transmit a copy of it out the front panel GPIO port and (with a bit of creativity) possibly cable it into another N310. Just watch your voltage level compatibility. -Daniel On Mon, Jul 22, 2019 at 4:38 PM Mark Wagner via USRP-users < usrp-users@lists.ettus.com> wrote: > Hey all, > > I'd like to recover the clock tone of a digital TV signal on one USRP N310 > and use it as the clock input to another N310. Does anyone have experience > doing something like this? I could use some pointers. > > -Mark > > -- > Mark Wagner > University of California San Diego > Electrical and Computer Engineering > > ___ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > -- Daniel Jepson Digital Hardware Engineer National Instruments O: +1.512.683.6163 daniel.jep...@ni.com ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] Digital TV Clock recovery using N310 and GNUradio
Hey all, I'd like to recover the clock tone of a digital TV signal on one USRP N310 and use it as the clock input to another N310. Does anyone have experience doing something like this? I could use some pointers. -Mark -- Mark Wagner University of California San Diego Electrical and Computer Engineering ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] Transmitting data from 2 antennas of B210
Hi, I have a very simple task: transmitting data with two antennas of B210. The data is just numbers in a file and I just need to play the file. I have been able to transmit data by one antenna with the command tx_samples_from_file. I did a lot of searching but I was not able to find a similar command to use two antennas. I am sorry if this question or some variations of it has been answered before. Any help is appreciated. Thanks, Zhenghao ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] RFNoC Testbench for custom block with AXI_CONFIG_BUS
On Mon, Jul 22, 2019 at 5:18 PM Brian Padalino wrote: > On Mon, Jul 22, 2019 at 5:12 PM Brian Padalino > wrote: > >> You just need to write_reg() and use an address of SR_AXI_CONFIG for >> everything other than the last value, and use SR_AXI_CONFIG_TLAST for the >> last one. >> >> That should push the valid high on the config line for each write you do, >> and then on the last write both valid and tlast will be held. >> > > Sorry, looking at my testbench I should have been more clear. > > I defined AXI_WRAPPER_BASE to 128. > I defined SR_AXI_CONFIG as AXI_WRAPPER_BASE + 1. > I defined SR_AXI_CONFIG_TLAST as SR_AXI_CONFIG + 1. > > In axi_wrapper, I instantiate: > > SR_AXI_CONFIG and assign it SR_AXI_CONFIG, and I also put > NUM_AXI_CONFIG_BUS to 1. > ... and I meant SR_AXI_CONFIG_BASE is the parameter to set on axi_wrapper. I shouldn't be so quick to reply. Haste makes waste. Again, apologies for not being clear. Brian > ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] RFNoC Testbench for custom block with AXI_CONFIG_BUS
On Mon, Jul 22, 2019 at 5:12 PM Brian Padalino wrote: > You just need to write_reg() and use an address of SR_AXI_CONFIG for > everything other than the last value, and use SR_AXI_CONFIG_TLAST for the > last one. > > That should push the valid high on the config line for each write you do, > and then on the last write both valid and tlast will be held. > Sorry, looking at my testbench I should have been more clear. I defined AXI_WRAPPER_BASE to 128. I defined SR_AXI_CONFIG as AXI_WRAPPER_BASE + 1. I defined SR_AXI_CONFIG_TLAST as SR_AXI_CONFIG + 1. In axi_wrapper, I instantiate: SR_AXI_CONFIG and assign it SR_AXI_CONFIG, and I also put NUM_AXI_CONFIG_BUS to 1. Sorry for not being complete in my previous email. Good luck. Brian ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] RFNoC Testbench for custom block with AXI_CONFIG_BUS
You just need to write_reg() and use an address of SR_AXI_CONFIG for everything other than the last value, and use SR_AXI_CONFIG_TLAST for the last one. That should push the valid high on the config line for each write you do, and then on the last write both valid and tlast will be held. Brian On Mon, Jul 22, 2019 at 3:51 PM Rob Kossler via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi, > I am wondering how to write a testbench for a block that uses the > AXI_CONFIG_BUS to load a vector of coefficients - just as it is done in > noc_block_window.v (I'm not sure why there is no tesbench file for > noc_block_window in the repo??). Are there any examples that show how to > load these coefficients from the testbench? > Thanks. > Rob > ___ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] RFNoC Testbench for custom block with AXI_CONFIG_BUS
Hi, I am wondering how to write a testbench for a block that uses the AXI_CONFIG_BUS to load a vector of coefficients - just as it is done in noc_block_window.v (I'm not sure why there is no tesbench file for noc_block_window in the repo??). Are there any examples that show how to load these coefficients from the testbench? Thanks. Rob ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
