Re: [USRP-users] Phase Representation: Using Xilinx CORDIC IP with RFNoC
On Tue, Sep 4, 2018 at 9:15 AM Jon Pendlum via USRP-users < usrp-users@lists.ettus.com> wrote: > Hey Steve, > > The complex_to_mag_phase 32-bit output is a concatenation: [31:16] phase, > [15:0] magnitude. There is also complex_to_magphase_int16_int24 if you want > 24-bit phase, mag. The phase value is in scaled radians. If you want a > different phase precision, you will need to create a new CORDIC IP > instance. Using the data with RFNoC, you have two options: 1) choose a > precision that will work with the built in UHD converters. see: > https://files.ettus.com/manual/page_converters.html or 2) handle the > conversion on your own. In either case, AXI Wrapper expects 32-bit data, so > you can concatenate or sign extend your data however works best for you. > To expand on Jon's answer, adding your own converter is pretty easy to do, though I must admit I am not an expert. Attached is what I had to do when receiving a u32 type from a magnitude squared representation from a custom block. Note that if you want to make very complicated typed to pass into a send() or recv() call, that can also work. You just need to register them the same way. One point of confusion I have, though, is when dealing with OOT modules which describe their own converters. It isn't clear to me, but there needs to be a destructor defined: uhd::convert::converter::~converter(). To get things to compile for me, I just defined ~converter() to be nothing since no resources were allocated, but if there are multiple OOT blocks with converters in them (think fancy controller blocks with singular static registrations with libuhd at construction or library loading), each trying to define that destructor, I don't know how this is supposed to work. As an experiment, for documentation, and to be complete, can someone from Ettus write a converter going both ways for the 32-bit concatenation that Jon described - [31:16] phase, [15:0] magnitude on the RFNoC side, and complex float on the host side? Both transmit and receive? I think that would be a good code example to have. Thanks, Brian converter_example.cpp Description: Binary data ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] Phase Representation: Using Xilinx CORDIC IP with RFNoC
Hey Steve, The complex_to_mag_phase 32-bit output is a concatenation: [31:16] phase, [15:0] magnitude. There is also complex_to_magphase_int16_int24 if you want 24-bit phase, mag. The phase value is in scaled radians. If you want a different phase precision, you will need to create a new CORDIC IP instance. Using the data with RFNoC, you have two options: 1) choose a precision that will work with the built in UHD converters. see: https://files.ettus.com/manual/page_converters.html or 2) handle the conversion on your own. In either case, AXI Wrapper expects 32-bit data, so you can concatenate or sign extend your data however works best for you. Jonathon On Tue, Sep 4, 2018 at 8:48 PM shachar J. brown via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi all, > > I'm trying to create a "complex-to-phase" by using the arctan within the > Xilinx CORDIC IP. > (Part of a simple fft-->1-in-N-->to-phase scheme). > Quite frankly I am a bit confused with the different bit representations. > > According to the Xilinx manual ( > https://www.xilinx.com/support/documentation/ip_documentation/cordic/v6_0/pg105-cordic.pdf), > the phase is represented by a 3QN format. How can such a format fit into an > RFNoC design? > > Note: Is there a simpler way to calculate a complex-to-phase in RFNoC? > I've noticed a "complex_to_mag_phase.v" within usrp3->lib->corgen, But I > couldn't figure out whether the 32-bit output is a magnitude or a phase > > Thnx a lot, > Steve > ___ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] Phase Representation: Using Xilinx CORDIC IP with RFNoC
Hi all, I'm trying to create a "complex-to-phase" by using the arctan within the Xilinx CORDIC IP. (Part of a simple fft-->1-in-N-->to-phase scheme). Quite frankly I am a bit confused with the different bit representations. According to the Xilinx manual ( https://www.xilinx.com/support/documentation/ip_documentation/cordic/v6_0/pg105-cordic.pdf), the phase is represented by a 3QN format. How can such a format fit into an RFNoC design? Note: Is there a simpler way to calculate a complex-to-phase in RFNoC? I've noticed a "complex_to_mag_phase.v" within usrp3->lib->corgen, But I couldn't figure out whether the 32-bit output is a magnitude or a phase Thnx a lot, Steve ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
