Re: [USRP-users] RFNoC DDC/Radio block/port restrictions
Yes. Thanks! On Tue, Mar 19, 2019 at 2:10 PM Brian Padalino wrote: > On Tue, Mar 19, 2019 at 1:52 PM Rob Kossler via USRP-users < > usrp-users@lists.ettus.com> wrote: > >> Hi, >> Are there restrictions regarding which DDC ports must be connected to >> which Radio ports. I am using an X310/UBX with a custom C++ rfnoc >> application and would like to do the following: >> Radio_0:port0 -> DDC_0:port0 >> Radio_1:port0 -> DDC_0:port1 >> Unfortunately, this fails (using default FPGA image) with a recv() after >> about 3K samples. If I simply change the 2nd link above to the following, >> then everything is fine. >> Radio_1:port0 -> DDC_1:port1 >> >> Why is the first config invalid? If this is a bug, is it presently being >> worked on? >> > > Radio produces samples at 200Msps. Each AXI bus port is 64-bits wide and > around 180-ish MHz. > > So you are limited by the AXI bus bandwidth. > > Does that make sense? > > Brian > ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] RFNoC DDC/Radio block/port restrictions
On Tue, Mar 19, 2019 at 1:52 PM Rob Kossler via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi, > Are there restrictions regarding which DDC ports must be connected to > which Radio ports. I am using an X310/UBX with a custom C++ rfnoc > application and would like to do the following: > Radio_0:port0 -> DDC_0:port0 > Radio_1:port0 -> DDC_0:port1 > Unfortunately, this fails (using default FPGA image) with a recv() after > about 3K samples. If I simply change the 2nd link above to the following, > then everything is fine. > Radio_1:port0 -> DDC_1:port1 > > Why is the first config invalid? If this is a bug, is it presently being > worked on? > Radio produces samples at 200Msps. Each AXI bus port is 64-bits wide and around 180-ish MHz. So you are limited by the AXI bus bandwidth. Does that make sense? Brian ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] RFNoC DDC/Radio block/port restrictions
Hi, Are there restrictions regarding which DDC ports must be connected to which Radio ports. I am using an X310/UBX with a custom C++ rfnoc application and would like to do the following: Radio_0:port0 -> DDC_0:port0 Radio_1:port0 -> DDC_0:port1 Unfortunately, this fails (using default FPGA image) with a recv() after about 3K samples. If I simply change the 2nd link above to the following, then everything is fine. Radio_1:port0 -> DDC_1:port1 Why is the first config invalid? If this is a bug, is it presently being worked on? FYI, my UHD version is UHD_3.14.0.0-20-gf63c089a. Rob ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
