RE: [Xen-ia64-devel] [Patch] Speculative Load/Store to IO memory
Good finding! One question From the patch, guest executes ld.s on physical mode. Is this a cacheable address(region 0) or un-cacheable address(region 4)? If it is a un-cacheable address, According to spec, the behavior of ld.s on un-cacheable page is undefined. We can set psr.ed directly. If it is a cacheable address and it is IO address. I don't know the real behavior on native machine. So we need to get the real behavior first, then decide how to emulate it. I'm asking some exports, hope I can get the answer. Thanks, Anthony -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Akio Takebe Sent: 2007年5月17日 20:49 To: xen-ia64-devel Subject: [Xen-ia64-devel] [Patch] Speculative Load/Store to IO memory Hi, We met a panic_domain(NULL, Undefined IPI-LHF read!\n), when we run test on Windows guest. When the issue was occurred, the guest did ld4.s r49=[r27]. Reading IO memory by using lds is wrong. But if the instruction is speculative, Xen should set psr.ed then return to guest. Signed-off-by: Akio Takebe [EMAIL PROTECTED] Signed-off-by: Kouya Shimura [EMAIL PROTECTED] Best Regards, Akio Takebe ___ Xen-ia64-devel mailing list Xen-ia64-devel@lists.xensource.com http://lists.xensource.com/xen-ia64-devel
RE: [Xen-ia64-devel] [Patch] Speculative Load/Store to IO memory
Hi, Anthony Thank you for yor comments. From the patch, guest executes ld.s on physical mode. Is this a cacheable address(region 0) or un-cacheable address(region 4)? No, this guest work on virtual mode. My patch is for virtual mode. This address is 0xa000fee00018. When we found the isssue, arguments of mmio_access() are (f798, fee00018, f7987d80, 4, 4, 1), so I think it is un-cachable. If it is a un-cacheable address, According to spec, the behavior of ld.s on un-cacheable page is undefined. We can set psr.ed directly. Is cheking ma=4 better? If it is a cacheable address and it is IO address. I don't know the real behavior on native machine. So we need to get the real behavior first, then decide how to emulate it. I'm asking some exports, hope I can get the answer. Thanks. This issue is difficult to reproduce, because we don't know step to reproduce. Best Regards, Akio Takebe ___ Xen-ia64-devel mailing list Xen-ia64-devel@lists.xensource.com http://lists.xensource.com/xen-ia64-devel
RE: [Xen-ia64-devel] [Patch] Speculative Load/Store to IO memory
Akio Takebe Sent: 2007年5月18日 11:43 To: Xu, Anthony; xen-ia64-devel Cc: Akio Takebe Subject: RE: [Xen-ia64-devel] [Patch] Speculative Load/Store to IO memory No, this guest work on virtual mode. My patch is for virtual mode. This address is 0xa000fee00018. When we found the isssue, arguments of mmio_access() are (f798, fee00018, f7987d80, 4, 4, 1), so I think it is un-cachable. Windows ld.s on un-cacheable page, this breaks ia64 spec. Can you dump the code segment and related information such as register value and tlb entres and the windows version you are using? I can send this to Intel windows team. If it is a un-cacheable address, According to spec, the behavior of ld.s on un-cacheable page is undefined. We can set psr.ed directly. Is cheking ma=4 better? This is better. We still need to find out the behavior of ld.s on cacheable IO page. If it is a cacheable address and it is IO address. I don't know the real behavior on native machine. So we need to get the real behavior first, then decide how to emulate it. I'm asking some exports, hope I can get the answer. Thanks. This issue is difficult to reproduce, because we don't know step to reproduce. Forget it. I'll try to get the answer. Thanks, Anthony ___ Xen-ia64-devel mailing list Xen-ia64-devel@lists.xensource.com http://lists.xensource.com/xen-ia64-devel