[Xenomai-git] Philippe Gerum : cobalt/arm64: use regular context switching code
Module: xenomai-3
Branch: next
Commit: dc0ceb9ea0a31c2295270618bf49c4eb79282b45
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=dc0ceb9ea0a31c2295270618bf49c4eb79282b45
Author: Philippe Gerum
Date: Sat Oct 17 18:07:59 2015 +0200
cobalt/arm64: use regular context switching code
Instead of open coding a copy of the regular context switching code,
use __switch_to() directly, assuming the pipeline properly serializes
switches from all domains.
---
kernel/cobalt/arch/arm64/thread.c | 66 +++--
1 file changed, 5 insertions(+), 61 deletions(-)
diff --git a/kernel/cobalt/arch/arm64/thread.c
b/kernel/cobalt/arch/arm64/thread.c
index 35dbd72..5282b0c 100644
--- a/kernel/cobalt/arch/arm64/thread.c
+++ b/kernel/cobalt/arch/arm64/thread.c
@@ -34,7 +34,7 @@
#include
#include
-#if defined(CONFIG_XENO_ARCH_FPU)
+#ifdef CONFIG_XENO_ARCH_FPU
#define FPSIMD_EN (0x3 << 20)
@@ -60,13 +60,6 @@ static void enable_fpsimd(void)
set_cpacr(cpacr);
}
-static void disable_fpsimd(void)
-{
- unsigned long cpacr = get_cpacr();
- cpacr &= ~FPSIMD_EN;
- set_cpacr(cpacr);
-}
-
int xnarch_fault_fpu_p(struct ipipe_trap_data *d)
{
return (d->exception == IPIPE_TRAP_FPU_ACC);
@@ -130,55 +123,17 @@ void xnarch_init_shadow_tcb(struct xnthread *thread)
tcb->fpup = &(tcb->core.host_task->thread.fpsimd_state);
xnthread_clear_state(thread, XNFPU);
}
-#endif /* CONFIG_XENO_ARCH_FPU */
-/* Switch support functions */
-static void xnarch_tls_thread_switch(struct task_struct *next)
-{
- unsigned long tpidr, tpidrro;
-
- if (!is_compat_task()) {
- asm("mrs %0, tpidr_el0" : "=r" (tpidr));
- current->thread.tp_value = tpidr;
- }
-
- if (is_compat_thread(task_thread_info(next))) {
- tpidr = 0;
- tpidrro = next->thread.tp_value;
- } else {
- tpidr = next->thread.tp_value;
- tpidrro = 0;
- }
-
- asm(
- " msr tpidr_el0, %0\n"
- " msr tpidrro_el0, %1"
- : : "r" (tpidr), "r" (tpidrro));
-}
-
-#ifdef CONFIG_PID_IN_CONTEXTIDR
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
- asm(
- " msr contextidr_el1, %0\n"
- " isb"
- :
- : "r" (task_pid_nr(next)));
-}
-#else
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
-}
-#endif
-/* End switch support functions */
+#endif /* CONFIG_XENO_ARCH_FPU */
void xnarch_switch_to(struct xnthread *out, struct xnthread *in)
{
struct xnarchtcb *out_tcb = &out->tcb, *in_tcb = &in->tcb;
struct mm_struct *prev_mm, *next_mm;
- struct task_struct *next;
+ struct task_struct *prev, *next;
next = in_tcb->core.host_task;
+ prev = out_tcb->core.host_task;
prev_mm = out_tcb->core.active_mm;
next_mm = in_tcb->core.mm;
@@ -198,18 +153,7 @@ void xnarch_switch_to(struct xnthread *out, struct
xnthread *in)
enter_lazy_tlb(prev_mm, next);
}
- xnarch_tls_thread_switch(in_tcb->core.tip->task);
- xnarch_contextidr_thread_switch(in_tcb->core.tip->task);
-
- /*
-* Complete any pending TLB or cache maintenance on this CPU in case
-* the thread migrates to a different CPU.
-*/
- dsb(ish);
-
- disable_fpsimd();
-
- cpu_switch_to(out_tcb->core.tip->task, in_tcb->core.tip->task);
+ __switch_to(prev, next);
}
int xnarch_escalate(void)
___
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[Xenomai-git] Philippe Gerum : cobalt/arm64: use regular context switching code
Module: xenomai-3
Branch: next
Commit: cff05e3238ab17e30a3cc002d160052fe12f8042
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=cff05e3238ab17e30a3cc002d160052fe12f8042
Author: Philippe Gerum
Date: Mon May 22 12:06:46 2017 +0200
cobalt/arm64: use regular context switching code
Since 4.9.x, the interrupt pipeline implementation guarantees that the
regular context switching code may be used over the head stage,
including the fpu management bits.
Drop the open coded support and use mainline's implementation instead.
At this chance, drop the useless conditionals for handling the non-FPU
case: this one does not apply to arm64.
---
.../cobalt/arch/arm64/include/asm/xenomai/thread.h | 44 +++-
kernel/cobalt/arch/arm64/thread.c | 14 +--
2 files changed, 26 insertions(+), 32 deletions(-)
diff --git a/kernel/cobalt/arch/arm64/include/asm/xenomai/thread.h
b/kernel/cobalt/arch/arm64/include/asm/xenomai/thread.h
index 319f4d8..eab6851 100644
--- a/kernel/cobalt/arch/arm64/include/asm/xenomai/thread.h
+++ b/kernel/cobalt/arch/arm64/include/asm/xenomai/thread.h
@@ -19,11 +19,16 @@
#ifndef _COBALT_ARM64_ASM_THREAD_H
#define _COBALT_ARM64_ASM_THREAD_H
+#include
#include
+#if defined(CONFIG_XENO_ARCH_FPU) && LINUX_VERSION_CODE < KERNEL_VERSION(4,9,0)
+#define ARM64_XENO_OLD_SWITCH
+#endif
+
struct xnarchtcb {
struct xntcb core;
-#ifdef CONFIG_XENO_ARCH_FPU
+#ifdef ARM64_XENO_OLD_SWITCH
struct fpsimd_state xnfpsimd_state;
struct fpsimd_state *fpup;
#define xnarch_fpu_ptr(tcb) ((tcb)->fpup)
@@ -58,53 +63,36 @@ static inline void xnarch_enter_root(struct xnthread *root)
{ }
int xnarch_escalate(void);
-#if defined(CONFIG_XENO_ARCH_FPU)
+#ifdef ARM64_XENO_OLD_SWITCH
void xnarch_init_root_tcb(struct xnthread *thread);
void xnarch_init_shadow_tcb(struct xnthread *thread);
-static inline int xnarch_fault_fpu_p(struct ipipe_trap_data *d)
-{
- return xnarch_fault_trap(d) == IPIPE_TRAP_FPU_ACC;
-}
-
void xnarch_leave_root(struct xnthread *root);
void xnarch_switch_fpu(struct xnthread *from, struct xnthread *thread);
-static inline int
-xnarch_handle_fpu_fault(struct xnthread *from,
- struct xnthread *to, struct ipipe_trap_data *d)
-{
- return 0;
-}
-
-#else /* !CONFIG_XENO_ARCH_FPU */
+#else /* !ARM64_XENO_OLD_SWITCH */
static inline void xnarch_init_root_tcb(struct xnthread *thread) { }
static inline void xnarch_init_shadow_tcb(struct xnthread *thread) { }
+static inline void xnarch_leave_root(struct xnthread *root) { }
+static inline void xnarch_switch_fpu(struct xnthread *f, struct xnthread *t) {
}
+
+#endif /* !ARM64_XENO_OLD_SWITCH */
-/*
- * Userland may raise FPU faults with FPU-enabled kernels, regardless
- * of whether real-time threads actually use FPU, so we simply ignore
- * these faults.
- */
static inline int xnarch_fault_fpu_p(struct ipipe_trap_data *d)
{
- return 0;
+ return xnarch_fault_trap(d) == IPIPE_TRAP_FPU_ACC;
}
-static inline void xnarch_leave_root(struct xnthread *root) { }
-
-static inline void xnarch_switch_fpu(struct xnthread *f, struct xnthread *t) {
}
-
-static inline int xnarch_handle_fpu_fault(struct xnthread *from,
- struct xnthread *to, struct
ipipe_trap_data *d)
+static inline int
+xnarch_handle_fpu_fault(struct xnthread *from,
+ struct xnthread *to, struct ipipe_trap_data *d)
{
return 0;
}
-#endif /* !CONFIG_XENO_ARCH_FPU */
static inline void xnarch_enable_kfpu(void) { }
diff --git a/kernel/cobalt/arch/arm64/thread.c
b/kernel/cobalt/arch/arm64/thread.c
index 3097aeb..270c99f 100644
--- a/kernel/cobalt/arch/arm64/thread.c
+++ b/kernel/cobalt/arch/arm64/thread.c
@@ -33,9 +33,10 @@
#include
#include
#include
-#include
-#ifdef CONFIG_XENO_ARCH_FPU
+#ifdef ARM64_XENO_OLD_SWITCH
+
+#include
#define FPSIMD_EN (0x3 << 20)
@@ -104,13 +105,13 @@ void xnarch_init_root_tcb(struct xnthread *thread)
tcb->fpup = NULL;
}
-#endif /* CONFIG_XENO_ARCH_FPU */
+#endif /* ARM64_XENO_OLD_SWITCH */
void xnarch_switch_to(struct xnthread *out, struct xnthread *in)
{
struct xnarchtcb *out_tcb = &out->tcb, *in_tcb = &in->tcb;
+ struct task_struct *prev, *next, *last;
struct mm_struct *prev_mm, *next_mm;
- struct task_struct *prev, *next;
next = in_tcb->core.host_task;
prev = out_tcb->core.host_task;
@@ -133,7 +134,12 @@ void xnarch_switch_to(struct xnthread *out, struct
xnthread *in)
enter_lazy_tlb(prev_mm, next);
}
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,9,0)
ipipe_switch_to(prev, next);
+ (void)last;
+#else
+ switch_to(prev, next, last);
+#endif
}
int xnarch_escalate(void)
___
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[Xenomai-git] Philippe Gerum : cobalt/arm64: use regular context switching code
Module: xenomai-3
Branch: next
Commit: f3978abba33c4d6841bca8db57b4b7dc2f50c71a
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=f3978abba33c4d6841bca8db57b4b7dc2f50c71a
Author: Philippe Gerum
Date: Mon May 22 12:06:46 2017 +0200
cobalt/arm64: use regular context switching code
Since 4.9.x, the interrupt pipeline implementation guarantees that the
regular context switching code may be used over the head stage,
including the fpu management bits.
Drop the open coded support and use mainline's implementation instead.
At this chance, drop the useless conditionals for handling the non-FPU
case: this one does not apply to arm64.
---
.../cobalt/arch/arm64/include/asm/xenomai/thread.h | 44 +++-
kernel/cobalt/arch/arm64/thread.c | 14 +--
2 files changed, 26 insertions(+), 32 deletions(-)
diff --git a/kernel/cobalt/arch/arm64/include/asm/xenomai/thread.h
b/kernel/cobalt/arch/arm64/include/asm/xenomai/thread.h
index 319f4d8..eab6851 100644
--- a/kernel/cobalt/arch/arm64/include/asm/xenomai/thread.h
+++ b/kernel/cobalt/arch/arm64/include/asm/xenomai/thread.h
@@ -19,11 +19,16 @@
#ifndef _COBALT_ARM64_ASM_THREAD_H
#define _COBALT_ARM64_ASM_THREAD_H
+#include
#include
+#if defined(CONFIG_XENO_ARCH_FPU) && LINUX_VERSION_CODE < KERNEL_VERSION(4,9,0)
+#define ARM64_XENO_OLD_SWITCH
+#endif
+
struct xnarchtcb {
struct xntcb core;
-#ifdef CONFIG_XENO_ARCH_FPU
+#ifdef ARM64_XENO_OLD_SWITCH
struct fpsimd_state xnfpsimd_state;
struct fpsimd_state *fpup;
#define xnarch_fpu_ptr(tcb) ((tcb)->fpup)
@@ -58,53 +63,36 @@ static inline void xnarch_enter_root(struct xnthread *root)
{ }
int xnarch_escalate(void);
-#if defined(CONFIG_XENO_ARCH_FPU)
+#ifdef ARM64_XENO_OLD_SWITCH
void xnarch_init_root_tcb(struct xnthread *thread);
void xnarch_init_shadow_tcb(struct xnthread *thread);
-static inline int xnarch_fault_fpu_p(struct ipipe_trap_data *d)
-{
- return xnarch_fault_trap(d) == IPIPE_TRAP_FPU_ACC;
-}
-
void xnarch_leave_root(struct xnthread *root);
void xnarch_switch_fpu(struct xnthread *from, struct xnthread *thread);
-static inline int
-xnarch_handle_fpu_fault(struct xnthread *from,
- struct xnthread *to, struct ipipe_trap_data *d)
-{
- return 0;
-}
-
-#else /* !CONFIG_XENO_ARCH_FPU */
+#else /* !ARM64_XENO_OLD_SWITCH */
static inline void xnarch_init_root_tcb(struct xnthread *thread) { }
static inline void xnarch_init_shadow_tcb(struct xnthread *thread) { }
+static inline void xnarch_leave_root(struct xnthread *root) { }
+static inline void xnarch_switch_fpu(struct xnthread *f, struct xnthread *t) {
}
+
+#endif /* !ARM64_XENO_OLD_SWITCH */
-/*
- * Userland may raise FPU faults with FPU-enabled kernels, regardless
- * of whether real-time threads actually use FPU, so we simply ignore
- * these faults.
- */
static inline int xnarch_fault_fpu_p(struct ipipe_trap_data *d)
{
- return 0;
+ return xnarch_fault_trap(d) == IPIPE_TRAP_FPU_ACC;
}
-static inline void xnarch_leave_root(struct xnthread *root) { }
-
-static inline void xnarch_switch_fpu(struct xnthread *f, struct xnthread *t) {
}
-
-static inline int xnarch_handle_fpu_fault(struct xnthread *from,
- struct xnthread *to, struct
ipipe_trap_data *d)
+static inline int
+xnarch_handle_fpu_fault(struct xnthread *from,
+ struct xnthread *to, struct ipipe_trap_data *d)
{
return 0;
}
-#endif /* !CONFIG_XENO_ARCH_FPU */
static inline void xnarch_enable_kfpu(void) { }
diff --git a/kernel/cobalt/arch/arm64/thread.c
b/kernel/cobalt/arch/arm64/thread.c
index 3097aeb..270c99f 100644
--- a/kernel/cobalt/arch/arm64/thread.c
+++ b/kernel/cobalt/arch/arm64/thread.c
@@ -33,9 +33,10 @@
#include
#include
#include
-#include
-#ifdef CONFIG_XENO_ARCH_FPU
+#ifdef ARM64_XENO_OLD_SWITCH
+
+#include
#define FPSIMD_EN (0x3 << 20)
@@ -104,13 +105,13 @@ void xnarch_init_root_tcb(struct xnthread *thread)
tcb->fpup = NULL;
}
-#endif /* CONFIG_XENO_ARCH_FPU */
+#endif /* ARM64_XENO_OLD_SWITCH */
void xnarch_switch_to(struct xnthread *out, struct xnthread *in)
{
struct xnarchtcb *out_tcb = &out->tcb, *in_tcb = &in->tcb;
+ struct task_struct *prev, *next, *last;
struct mm_struct *prev_mm, *next_mm;
- struct task_struct *prev, *next;
next = in_tcb->core.host_task;
prev = out_tcb->core.host_task;
@@ -133,7 +134,12 @@ void xnarch_switch_to(struct xnthread *out, struct
xnthread *in)
enter_lazy_tlb(prev_mm, next);
}
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,9,0)
ipipe_switch_to(prev, next);
+ (void)last;
+#else
+ switch_to(prev, next, last);
+#endif
}
int xnarch_escalate(void)
___
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[Xenomai-git] Philippe Gerum : cobalt/arm64: use regular context switching code
Module: xenomai-3
Branch: next
Commit: 8c32f01c118c3aeaa61a245562374b6bf7c9a827
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=8c32f01c118c3aeaa61a245562374b6bf7c9a827
Author: Philippe Gerum
Date: Sat Oct 17 18:07:59 2015 +0200
cobalt/arm64: use regular context switching code
Instead of open coding a copy of the regular context switching code,
use __switch_to() directly, assuming the pipeline properly serializes
switches from all domains.
---
kernel/cobalt/arch/arm64/thread.c | 66 +++--
1 file changed, 5 insertions(+), 61 deletions(-)
diff --git a/kernel/cobalt/arch/arm64/thread.c
b/kernel/cobalt/arch/arm64/thread.c
index 35dbd72..5282b0c 100644
--- a/kernel/cobalt/arch/arm64/thread.c
+++ b/kernel/cobalt/arch/arm64/thread.c
@@ -34,7 +34,7 @@
#include
#include
-#if defined(CONFIG_XENO_ARCH_FPU)
+#ifdef CONFIG_XENO_ARCH_FPU
#define FPSIMD_EN (0x3 << 20)
@@ -60,13 +60,6 @@ static void enable_fpsimd(void)
set_cpacr(cpacr);
}
-static void disable_fpsimd(void)
-{
- unsigned long cpacr = get_cpacr();
- cpacr &= ~FPSIMD_EN;
- set_cpacr(cpacr);
-}
-
int xnarch_fault_fpu_p(struct ipipe_trap_data *d)
{
return (d->exception == IPIPE_TRAP_FPU_ACC);
@@ -130,55 +123,17 @@ void xnarch_init_shadow_tcb(struct xnthread *thread)
tcb->fpup = &(tcb->core.host_task->thread.fpsimd_state);
xnthread_clear_state(thread, XNFPU);
}
-#endif /* CONFIG_XENO_ARCH_FPU */
-/* Switch support functions */
-static void xnarch_tls_thread_switch(struct task_struct *next)
-{
- unsigned long tpidr, tpidrro;
-
- if (!is_compat_task()) {
- asm("mrs %0, tpidr_el0" : "=r" (tpidr));
- current->thread.tp_value = tpidr;
- }
-
- if (is_compat_thread(task_thread_info(next))) {
- tpidr = 0;
- tpidrro = next->thread.tp_value;
- } else {
- tpidr = next->thread.tp_value;
- tpidrro = 0;
- }
-
- asm(
- " msr tpidr_el0, %0\n"
- " msr tpidrro_el0, %1"
- : : "r" (tpidr), "r" (tpidrro));
-}
-
-#ifdef CONFIG_PID_IN_CONTEXTIDR
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
- asm(
- " msr contextidr_el1, %0\n"
- " isb"
- :
- : "r" (task_pid_nr(next)));
-}
-#else
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
-}
-#endif
-/* End switch support functions */
+#endif /* CONFIG_XENO_ARCH_FPU */
void xnarch_switch_to(struct xnthread *out, struct xnthread *in)
{
struct xnarchtcb *out_tcb = &out->tcb, *in_tcb = &in->tcb;
struct mm_struct *prev_mm, *next_mm;
- struct task_struct *next;
+ struct task_struct *prev, *next;
next = in_tcb->core.host_task;
+ prev = out_tcb->core.host_task;
prev_mm = out_tcb->core.active_mm;
next_mm = in_tcb->core.mm;
@@ -198,18 +153,7 @@ void xnarch_switch_to(struct xnthread *out, struct
xnthread *in)
enter_lazy_tlb(prev_mm, next);
}
- xnarch_tls_thread_switch(in_tcb->core.tip->task);
- xnarch_contextidr_thread_switch(in_tcb->core.tip->task);
-
- /*
-* Complete any pending TLB or cache maintenance on this CPU in case
-* the thread migrates to a different CPU.
-*/
- dsb(ish);
-
- disable_fpsimd();
-
- cpu_switch_to(out_tcb->core.tip->task, in_tcb->core.tip->task);
+ __switch_to(prev, next);
}
int xnarch_escalate(void)
___
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[Xenomai-git] Philippe Gerum : cobalt/arm64: use regular context switching code
Module: xenomai-3
Branch: next
Commit: 5eb0700e35ef3a095b6453f308760e8cc908784e
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=5eb0700e35ef3a095b6453f308760e8cc908784e
Author: Philippe Gerum
Date: Mon May 22 12:06:46 2017 +0200
cobalt/arm64: use regular context switching code
Since 4.9.x, the interrupt pipeline implementation guarantees that the
regular context switching code may be used over the head stage,
including the fpu management bits.
Drop the open coded support and use mainline's implementation instead.
At this chance, drop the useless conditionals for handling the non-FPU
case: this one does not apply to arm64.
---
.../cobalt/arch/arm64/include/asm/xenomai/thread.h | 44 +++-
kernel/cobalt/arch/arm64/thread.c | 14 +--
2 files changed, 26 insertions(+), 32 deletions(-)
diff --git a/kernel/cobalt/arch/arm64/include/asm/xenomai/thread.h
b/kernel/cobalt/arch/arm64/include/asm/xenomai/thread.h
index 319f4d8..eab6851 100644
--- a/kernel/cobalt/arch/arm64/include/asm/xenomai/thread.h
+++ b/kernel/cobalt/arch/arm64/include/asm/xenomai/thread.h
@@ -19,11 +19,16 @@
#ifndef _COBALT_ARM64_ASM_THREAD_H
#define _COBALT_ARM64_ASM_THREAD_H
+#include
#include
+#if defined(CONFIG_XENO_ARCH_FPU) && LINUX_VERSION_CODE < KERNEL_VERSION(4,9,0)
+#define ARM64_XENO_OLD_SWITCH
+#endif
+
struct xnarchtcb {
struct xntcb core;
-#ifdef CONFIG_XENO_ARCH_FPU
+#ifdef ARM64_XENO_OLD_SWITCH
struct fpsimd_state xnfpsimd_state;
struct fpsimd_state *fpup;
#define xnarch_fpu_ptr(tcb) ((tcb)->fpup)
@@ -58,53 +63,36 @@ static inline void xnarch_enter_root(struct xnthread *root)
{ }
int xnarch_escalate(void);
-#if defined(CONFIG_XENO_ARCH_FPU)
+#ifdef ARM64_XENO_OLD_SWITCH
void xnarch_init_root_tcb(struct xnthread *thread);
void xnarch_init_shadow_tcb(struct xnthread *thread);
-static inline int xnarch_fault_fpu_p(struct ipipe_trap_data *d)
-{
- return xnarch_fault_trap(d) == IPIPE_TRAP_FPU_ACC;
-}
-
void xnarch_leave_root(struct xnthread *root);
void xnarch_switch_fpu(struct xnthread *from, struct xnthread *thread);
-static inline int
-xnarch_handle_fpu_fault(struct xnthread *from,
- struct xnthread *to, struct ipipe_trap_data *d)
-{
- return 0;
-}
-
-#else /* !CONFIG_XENO_ARCH_FPU */
+#else /* !ARM64_XENO_OLD_SWITCH */
static inline void xnarch_init_root_tcb(struct xnthread *thread) { }
static inline void xnarch_init_shadow_tcb(struct xnthread *thread) { }
+static inline void xnarch_leave_root(struct xnthread *root) { }
+static inline void xnarch_switch_fpu(struct xnthread *f, struct xnthread *t) {
}
+
+#endif /* !ARM64_XENO_OLD_SWITCH */
-/*
- * Userland may raise FPU faults with FPU-enabled kernels, regardless
- * of whether real-time threads actually use FPU, so we simply ignore
- * these faults.
- */
static inline int xnarch_fault_fpu_p(struct ipipe_trap_data *d)
{
- return 0;
+ return xnarch_fault_trap(d) == IPIPE_TRAP_FPU_ACC;
}
-static inline void xnarch_leave_root(struct xnthread *root) { }
-
-static inline void xnarch_switch_fpu(struct xnthread *f, struct xnthread *t) {
}
-
-static inline int xnarch_handle_fpu_fault(struct xnthread *from,
- struct xnthread *to, struct
ipipe_trap_data *d)
+static inline int
+xnarch_handle_fpu_fault(struct xnthread *from,
+ struct xnthread *to, struct ipipe_trap_data *d)
{
return 0;
}
-#endif /* !CONFIG_XENO_ARCH_FPU */
static inline void xnarch_enable_kfpu(void) { }
diff --git a/kernel/cobalt/arch/arm64/thread.c
b/kernel/cobalt/arch/arm64/thread.c
index 3097aeb..270c99f 100644
--- a/kernel/cobalt/arch/arm64/thread.c
+++ b/kernel/cobalt/arch/arm64/thread.c
@@ -33,9 +33,10 @@
#include
#include
#include
-#include
-#ifdef CONFIG_XENO_ARCH_FPU
+#ifdef ARM64_XENO_OLD_SWITCH
+
+#include
#define FPSIMD_EN (0x3 << 20)
@@ -104,13 +105,13 @@ void xnarch_init_root_tcb(struct xnthread *thread)
tcb->fpup = NULL;
}
-#endif /* CONFIG_XENO_ARCH_FPU */
+#endif /* ARM64_XENO_OLD_SWITCH */
void xnarch_switch_to(struct xnthread *out, struct xnthread *in)
{
struct xnarchtcb *out_tcb = &out->tcb, *in_tcb = &in->tcb;
+ struct task_struct *prev, *next, *last;
struct mm_struct *prev_mm, *next_mm;
- struct task_struct *prev, *next;
next = in_tcb->core.host_task;
prev = out_tcb->core.host_task;
@@ -133,7 +134,12 @@ void xnarch_switch_to(struct xnthread *out, struct
xnthread *in)
enter_lazy_tlb(prev_mm, next);
}
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,9,0)
ipipe_switch_to(prev, next);
+ (void)last;
+#else
+ switch_to(prev, next, last);
+#endif
}
int xnarch_escalate(void)
___
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[Xenomai-git] Philippe Gerum : cobalt/arm64: use regular context switching code
Module: xenomai-3
Branch: next
Commit: 858c70b2b6ee9c8f09068007c4cba30b418a127c
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=858c70b2b6ee9c8f09068007c4cba30b418a127c
Author: Philippe Gerum
Date: Sat Oct 17 18:07:59 2015 +0200
cobalt/arm64: use regular context switching code
Instead of open coding a copy of the regular context switching code,
use __switch_to() directly, assuming the pipeline properly serializes
switches from all domains.
---
kernel/cobalt/arch/arm64/thread.c | 66 +++--
1 file changed, 5 insertions(+), 61 deletions(-)
diff --git a/kernel/cobalt/arch/arm64/thread.c
b/kernel/cobalt/arch/arm64/thread.c
index 35dbd72..5282b0c 100644
--- a/kernel/cobalt/arch/arm64/thread.c
+++ b/kernel/cobalt/arch/arm64/thread.c
@@ -34,7 +34,7 @@
#include
#include
-#if defined(CONFIG_XENO_ARCH_FPU)
+#ifdef CONFIG_XENO_ARCH_FPU
#define FPSIMD_EN (0x3 << 20)
@@ -60,13 +60,6 @@ static void enable_fpsimd(void)
set_cpacr(cpacr);
}
-static void disable_fpsimd(void)
-{
- unsigned long cpacr = get_cpacr();
- cpacr &= ~FPSIMD_EN;
- set_cpacr(cpacr);
-}
-
int xnarch_fault_fpu_p(struct ipipe_trap_data *d)
{
return (d->exception == IPIPE_TRAP_FPU_ACC);
@@ -130,55 +123,17 @@ void xnarch_init_shadow_tcb(struct xnthread *thread)
tcb->fpup = &(tcb->core.host_task->thread.fpsimd_state);
xnthread_clear_state(thread, XNFPU);
}
-#endif /* CONFIG_XENO_ARCH_FPU */
-/* Switch support functions */
-static void xnarch_tls_thread_switch(struct task_struct *next)
-{
- unsigned long tpidr, tpidrro;
-
- if (!is_compat_task()) {
- asm("mrs %0, tpidr_el0" : "=r" (tpidr));
- current->thread.tp_value = tpidr;
- }
-
- if (is_compat_thread(task_thread_info(next))) {
- tpidr = 0;
- tpidrro = next->thread.tp_value;
- } else {
- tpidr = next->thread.tp_value;
- tpidrro = 0;
- }
-
- asm(
- " msr tpidr_el0, %0\n"
- " msr tpidrro_el0, %1"
- : : "r" (tpidr), "r" (tpidrro));
-}
-
-#ifdef CONFIG_PID_IN_CONTEXTIDR
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
- asm(
- " msr contextidr_el1, %0\n"
- " isb"
- :
- : "r" (task_pid_nr(next)));
-}
-#else
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
-}
-#endif
-/* End switch support functions */
+#endif /* CONFIG_XENO_ARCH_FPU */
void xnarch_switch_to(struct xnthread *out, struct xnthread *in)
{
struct xnarchtcb *out_tcb = &out->tcb, *in_tcb = &in->tcb;
struct mm_struct *prev_mm, *next_mm;
- struct task_struct *next;
+ struct task_struct *prev, *next;
next = in_tcb->core.host_task;
+ prev = out_tcb->core.host_task;
prev_mm = out_tcb->core.active_mm;
next_mm = in_tcb->core.mm;
@@ -198,18 +153,7 @@ void xnarch_switch_to(struct xnthread *out, struct
xnthread *in)
enter_lazy_tlb(prev_mm, next);
}
- xnarch_tls_thread_switch(in_tcb->core.tip->task);
- xnarch_contextidr_thread_switch(in_tcb->core.tip->task);
-
- /*
-* Complete any pending TLB or cache maintenance on this CPU in case
-* the thread migrates to a different CPU.
-*/
- dsb(ish);
-
- disable_fpsimd();
-
- cpu_switch_to(out_tcb->core.tip->task, in_tcb->core.tip->task);
+ __switch_to(prev, next);
}
int xnarch_escalate(void)
___
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[Xenomai-git] Philippe Gerum : cobalt/arm64: use regular context switching code
Module: xenomai-3
Branch: next
Commit: 10f22efa0ea519125e6bd63c7add0de27bcb2d86
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=10f22efa0ea519125e6bd63c7add0de27bcb2d86
Author: Philippe Gerum
Date: Sat Oct 17 18:07:59 2015 +0200
cobalt/arm64: use regular context switching code
Instead of open coding a copy of the regular context switching code,
use __switch_to() directly, assuming the pipeline properly serializes
switches from all domains.
---
kernel/cobalt/arch/arm64/thread.c | 66 +++--
1 file changed, 5 insertions(+), 61 deletions(-)
diff --git a/kernel/cobalt/arch/arm64/thread.c
b/kernel/cobalt/arch/arm64/thread.c
index 35dbd72..5282b0c 100644
--- a/kernel/cobalt/arch/arm64/thread.c
+++ b/kernel/cobalt/arch/arm64/thread.c
@@ -34,7 +34,7 @@
#include
#include
-#if defined(CONFIG_XENO_ARCH_FPU)
+#ifdef CONFIG_XENO_ARCH_FPU
#define FPSIMD_EN (0x3 << 20)
@@ -60,13 +60,6 @@ static void enable_fpsimd(void)
set_cpacr(cpacr);
}
-static void disable_fpsimd(void)
-{
- unsigned long cpacr = get_cpacr();
- cpacr &= ~FPSIMD_EN;
- set_cpacr(cpacr);
-}
-
int xnarch_fault_fpu_p(struct ipipe_trap_data *d)
{
return (d->exception == IPIPE_TRAP_FPU_ACC);
@@ -130,55 +123,17 @@ void xnarch_init_shadow_tcb(struct xnthread *thread)
tcb->fpup = &(tcb->core.host_task->thread.fpsimd_state);
xnthread_clear_state(thread, XNFPU);
}
-#endif /* CONFIG_XENO_ARCH_FPU */
-/* Switch support functions */
-static void xnarch_tls_thread_switch(struct task_struct *next)
-{
- unsigned long tpidr, tpidrro;
-
- if (!is_compat_task()) {
- asm("mrs %0, tpidr_el0" : "=r" (tpidr));
- current->thread.tp_value = tpidr;
- }
-
- if (is_compat_thread(task_thread_info(next))) {
- tpidr = 0;
- tpidrro = next->thread.tp_value;
- } else {
- tpidr = next->thread.tp_value;
- tpidrro = 0;
- }
-
- asm(
- " msr tpidr_el0, %0\n"
- " msr tpidrro_el0, %1"
- : : "r" (tpidr), "r" (tpidrro));
-}
-
-#ifdef CONFIG_PID_IN_CONTEXTIDR
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
- asm(
- " msr contextidr_el1, %0\n"
- " isb"
- :
- : "r" (task_pid_nr(next)));
-}
-#else
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
-}
-#endif
-/* End switch support functions */
+#endif /* CONFIG_XENO_ARCH_FPU */
void xnarch_switch_to(struct xnthread *out, struct xnthread *in)
{
struct xnarchtcb *out_tcb = &out->tcb, *in_tcb = &in->tcb;
struct mm_struct *prev_mm, *next_mm;
- struct task_struct *next;
+ struct task_struct *prev, *next;
next = in_tcb->core.host_task;
+ prev = out_tcb->core.host_task;
prev_mm = out_tcb->core.active_mm;
next_mm = in_tcb->core.mm;
@@ -198,18 +153,7 @@ void xnarch_switch_to(struct xnthread *out, struct
xnthread *in)
enter_lazy_tlb(prev_mm, next);
}
- xnarch_tls_thread_switch(in_tcb->core.tip->task);
- xnarch_contextidr_thread_switch(in_tcb->core.tip->task);
-
- /*
-* Complete any pending TLB or cache maintenance on this CPU in case
-* the thread migrates to a different CPU.
-*/
- dsb(ish);
-
- disable_fpsimd();
-
- cpu_switch_to(out_tcb->core.tip->task, in_tcb->core.tip->task);
+ __switch_to(prev, next);
}
int xnarch_escalate(void)
___
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[Xenomai-git] Philippe Gerum : cobalt/arm64: use regular context switching code
Module: xenomai-3
Branch: next
Commit: fb2d493df80d1a78ac8ef1e66797c7a154594f79
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=fb2d493df80d1a78ac8ef1e66797c7a154594f79
Author: Philippe Gerum
Date: Sat Oct 17 18:07:59 2015 +0200
cobalt/arm64: use regular context switching code
Instead of open coding a copy of the regular context switching code,
use __switch_to() directly, assuming the pipeline properly serializes
switches from all domains.
---
kernel/cobalt/arch/arm64/thread.c | 66 +++--
1 file changed, 5 insertions(+), 61 deletions(-)
diff --git a/kernel/cobalt/arch/arm64/thread.c
b/kernel/cobalt/arch/arm64/thread.c
index 35dbd72..5282b0c 100644
--- a/kernel/cobalt/arch/arm64/thread.c
+++ b/kernel/cobalt/arch/arm64/thread.c
@@ -34,7 +34,7 @@
#include
#include
-#if defined(CONFIG_XENO_ARCH_FPU)
+#ifdef CONFIG_XENO_ARCH_FPU
#define FPSIMD_EN (0x3 << 20)
@@ -60,13 +60,6 @@ static void enable_fpsimd(void)
set_cpacr(cpacr);
}
-static void disable_fpsimd(void)
-{
- unsigned long cpacr = get_cpacr();
- cpacr &= ~FPSIMD_EN;
- set_cpacr(cpacr);
-}
-
int xnarch_fault_fpu_p(struct ipipe_trap_data *d)
{
return (d->exception == IPIPE_TRAP_FPU_ACC);
@@ -130,55 +123,17 @@ void xnarch_init_shadow_tcb(struct xnthread *thread)
tcb->fpup = &(tcb->core.host_task->thread.fpsimd_state);
xnthread_clear_state(thread, XNFPU);
}
-#endif /* CONFIG_XENO_ARCH_FPU */
-/* Switch support functions */
-static void xnarch_tls_thread_switch(struct task_struct *next)
-{
- unsigned long tpidr, tpidrro;
-
- if (!is_compat_task()) {
- asm("mrs %0, tpidr_el0" : "=r" (tpidr));
- current->thread.tp_value = tpidr;
- }
-
- if (is_compat_thread(task_thread_info(next))) {
- tpidr = 0;
- tpidrro = next->thread.tp_value;
- } else {
- tpidr = next->thread.tp_value;
- tpidrro = 0;
- }
-
- asm(
- " msr tpidr_el0, %0\n"
- " msr tpidrro_el0, %1"
- : : "r" (tpidr), "r" (tpidrro));
-}
-
-#ifdef CONFIG_PID_IN_CONTEXTIDR
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
- asm(
- " msr contextidr_el1, %0\n"
- " isb"
- :
- : "r" (task_pid_nr(next)));
-}
-#else
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
-}
-#endif
-/* End switch support functions */
+#endif /* CONFIG_XENO_ARCH_FPU */
void xnarch_switch_to(struct xnthread *out, struct xnthread *in)
{
struct xnarchtcb *out_tcb = &out->tcb, *in_tcb = &in->tcb;
struct mm_struct *prev_mm, *next_mm;
- struct task_struct *next;
+ struct task_struct *prev, *next;
next = in_tcb->core.host_task;
+ prev = out_tcb->core.host_task;
prev_mm = out_tcb->core.active_mm;
next_mm = in_tcb->core.mm;
@@ -198,18 +153,7 @@ void xnarch_switch_to(struct xnthread *out, struct
xnthread *in)
enter_lazy_tlb(prev_mm, next);
}
- xnarch_tls_thread_switch(in_tcb->core.tip->task);
- xnarch_contextidr_thread_switch(in_tcb->core.tip->task);
-
- /*
-* Complete any pending TLB or cache maintenance on this CPU in case
-* the thread migrates to a different CPU.
-*/
- dsb(ish);
-
- disable_fpsimd();
-
- cpu_switch_to(out_tcb->core.tip->task, in_tcb->core.tip->task);
+ __switch_to(prev, next);
}
int xnarch_escalate(void)
___
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[Xenomai-git] Philippe Gerum : cobalt/arm64: use regular context switching code
Module: xenomai-3
Branch: next
Commit: ae5bc7e237ee245c2d7df225432f2ac72fd4b3a6
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=ae5bc7e237ee245c2d7df225432f2ac72fd4b3a6
Author: Philippe Gerum
Date: Sat Oct 17 18:07:59 2015 +0200
cobalt/arm64: use regular context switching code
Instead of open coding a copy of the regular context switching code,
use __switch_to() directly, assuming the pipeline properly serializes
switches from all domains.
---
kernel/cobalt/arch/arm64/thread.c | 66 +++--
1 file changed, 5 insertions(+), 61 deletions(-)
diff --git a/kernel/cobalt/arch/arm64/thread.c
b/kernel/cobalt/arch/arm64/thread.c
index 35dbd72..5282b0c 100644
--- a/kernel/cobalt/arch/arm64/thread.c
+++ b/kernel/cobalt/arch/arm64/thread.c
@@ -34,7 +34,7 @@
#include
#include
-#if defined(CONFIG_XENO_ARCH_FPU)
+#ifdef CONFIG_XENO_ARCH_FPU
#define FPSIMD_EN (0x3 << 20)
@@ -60,13 +60,6 @@ static void enable_fpsimd(void)
set_cpacr(cpacr);
}
-static void disable_fpsimd(void)
-{
- unsigned long cpacr = get_cpacr();
- cpacr &= ~FPSIMD_EN;
- set_cpacr(cpacr);
-}
-
int xnarch_fault_fpu_p(struct ipipe_trap_data *d)
{
return (d->exception == IPIPE_TRAP_FPU_ACC);
@@ -130,55 +123,17 @@ void xnarch_init_shadow_tcb(struct xnthread *thread)
tcb->fpup = &(tcb->core.host_task->thread.fpsimd_state);
xnthread_clear_state(thread, XNFPU);
}
-#endif /* CONFIG_XENO_ARCH_FPU */
-/* Switch support functions */
-static void xnarch_tls_thread_switch(struct task_struct *next)
-{
- unsigned long tpidr, tpidrro;
-
- if (!is_compat_task()) {
- asm("mrs %0, tpidr_el0" : "=r" (tpidr));
- current->thread.tp_value = tpidr;
- }
-
- if (is_compat_thread(task_thread_info(next))) {
- tpidr = 0;
- tpidrro = next->thread.tp_value;
- } else {
- tpidr = next->thread.tp_value;
- tpidrro = 0;
- }
-
- asm(
- " msr tpidr_el0, %0\n"
- " msr tpidrro_el0, %1"
- : : "r" (tpidr), "r" (tpidrro));
-}
-
-#ifdef CONFIG_PID_IN_CONTEXTIDR
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
- asm(
- " msr contextidr_el1, %0\n"
- " isb"
- :
- : "r" (task_pid_nr(next)));
-}
-#else
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
-}
-#endif
-/* End switch support functions */
+#endif /* CONFIG_XENO_ARCH_FPU */
void xnarch_switch_to(struct xnthread *out, struct xnthread *in)
{
struct xnarchtcb *out_tcb = &out->tcb, *in_tcb = &in->tcb;
struct mm_struct *prev_mm, *next_mm;
- struct task_struct *next;
+ struct task_struct *prev, *next;
next = in_tcb->core.host_task;
+ prev = out_tcb->core.host_task;
prev_mm = out_tcb->core.active_mm;
next_mm = in_tcb->core.mm;
@@ -198,18 +153,7 @@ void xnarch_switch_to(struct xnthread *out, struct
xnthread *in)
enter_lazy_tlb(prev_mm, next);
}
- xnarch_tls_thread_switch(in_tcb->core.tip->task);
- xnarch_contextidr_thread_switch(in_tcb->core.tip->task);
-
- /*
-* Complete any pending TLB or cache maintenance on this CPU in case
-* the thread migrates to a different CPU.
-*/
- dsb(ish);
-
- disable_fpsimd();
-
- cpu_switch_to(out_tcb->core.tip->task, in_tcb->core.tip->task);
+ __switch_to(prev, next);
}
int xnarch_escalate(void)
___
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[Xenomai-git] Philippe Gerum : cobalt/arm64: use regular context switching code
Module: xenomai-3
Branch: next
Commit: da86fe1bc6fc8e9a640d5ce37a2f7f9ffd2f0b58
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=da86fe1bc6fc8e9a640d5ce37a2f7f9ffd2f0b58
Author: Philippe Gerum
Date: Sat Oct 17 18:07:59 2015 +0200
cobalt/arm64: use regular context switching code
Instead of open coding a copy of the regular context switching code,
use __switch_to() directly, assuming the pipeline properly serializes
switches from all domains.
---
kernel/cobalt/arch/arm64/thread.c | 66 +++--
1 file changed, 5 insertions(+), 61 deletions(-)
diff --git a/kernel/cobalt/arch/arm64/thread.c
b/kernel/cobalt/arch/arm64/thread.c
index 35dbd72..5282b0c 100644
--- a/kernel/cobalt/arch/arm64/thread.c
+++ b/kernel/cobalt/arch/arm64/thread.c
@@ -34,7 +34,7 @@
#include
#include
-#if defined(CONFIG_XENO_ARCH_FPU)
+#ifdef CONFIG_XENO_ARCH_FPU
#define FPSIMD_EN (0x3 << 20)
@@ -60,13 +60,6 @@ static void enable_fpsimd(void)
set_cpacr(cpacr);
}
-static void disable_fpsimd(void)
-{
- unsigned long cpacr = get_cpacr();
- cpacr &= ~FPSIMD_EN;
- set_cpacr(cpacr);
-}
-
int xnarch_fault_fpu_p(struct ipipe_trap_data *d)
{
return (d->exception == IPIPE_TRAP_FPU_ACC);
@@ -130,55 +123,17 @@ void xnarch_init_shadow_tcb(struct xnthread *thread)
tcb->fpup = &(tcb->core.host_task->thread.fpsimd_state);
xnthread_clear_state(thread, XNFPU);
}
-#endif /* CONFIG_XENO_ARCH_FPU */
-/* Switch support functions */
-static void xnarch_tls_thread_switch(struct task_struct *next)
-{
- unsigned long tpidr, tpidrro;
-
- if (!is_compat_task()) {
- asm("mrs %0, tpidr_el0" : "=r" (tpidr));
- current->thread.tp_value = tpidr;
- }
-
- if (is_compat_thread(task_thread_info(next))) {
- tpidr = 0;
- tpidrro = next->thread.tp_value;
- } else {
- tpidr = next->thread.tp_value;
- tpidrro = 0;
- }
-
- asm(
- " msr tpidr_el0, %0\n"
- " msr tpidrro_el0, %1"
- : : "r" (tpidr), "r" (tpidrro));
-}
-
-#ifdef CONFIG_PID_IN_CONTEXTIDR
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
- asm(
- " msr contextidr_el1, %0\n"
- " isb"
- :
- : "r" (task_pid_nr(next)));
-}
-#else
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
-}
-#endif
-/* End switch support functions */
+#endif /* CONFIG_XENO_ARCH_FPU */
void xnarch_switch_to(struct xnthread *out, struct xnthread *in)
{
struct xnarchtcb *out_tcb = &out->tcb, *in_tcb = &in->tcb;
struct mm_struct *prev_mm, *next_mm;
- struct task_struct *next;
+ struct task_struct *prev, *next;
next = in_tcb->core.host_task;
+ prev = out_tcb->core.host_task;
prev_mm = out_tcb->core.active_mm;
next_mm = in_tcb->core.mm;
@@ -198,18 +153,7 @@ void xnarch_switch_to(struct xnthread *out, struct
xnthread *in)
enter_lazy_tlb(prev_mm, next);
}
- xnarch_tls_thread_switch(in_tcb->core.tip->task);
- xnarch_contextidr_thread_switch(in_tcb->core.tip->task);
-
- /*
-* Complete any pending TLB or cache maintenance on this CPU in case
-* the thread migrates to a different CPU.
-*/
- dsb(ish);
-
- disable_fpsimd();
-
- cpu_switch_to(out_tcb->core.tip->task, in_tcb->core.tip->task);
+ __switch_to(prev, next);
}
int xnarch_escalate(void)
___
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[Xenomai-git] Philippe Gerum : cobalt/arm64: use regular context switching code
Module: xenomai-3
Branch: next
Commit: e5e957e99f500eee090996b9965df6086aeb41db
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=e5e957e99f500eee090996b9965df6086aeb41db
Author: Philippe Gerum
Date: Sat Oct 17 18:07:59 2015 +0200
cobalt/arm64: use regular context switching code
Instead of open coding a copy of the regular context switching code,
use __switch_to() directly, assuming the pipeline properly serializes
switches from all domains.
---
kernel/cobalt/arch/arm64/thread.c | 66 +++--
1 file changed, 5 insertions(+), 61 deletions(-)
diff --git a/kernel/cobalt/arch/arm64/thread.c
b/kernel/cobalt/arch/arm64/thread.c
index 35dbd72..5282b0c 100644
--- a/kernel/cobalt/arch/arm64/thread.c
+++ b/kernel/cobalt/arch/arm64/thread.c
@@ -34,7 +34,7 @@
#include
#include
-#if defined(CONFIG_XENO_ARCH_FPU)
+#ifdef CONFIG_XENO_ARCH_FPU
#define FPSIMD_EN (0x3 << 20)
@@ -60,13 +60,6 @@ static void enable_fpsimd(void)
set_cpacr(cpacr);
}
-static void disable_fpsimd(void)
-{
- unsigned long cpacr = get_cpacr();
- cpacr &= ~FPSIMD_EN;
- set_cpacr(cpacr);
-}
-
int xnarch_fault_fpu_p(struct ipipe_trap_data *d)
{
return (d->exception == IPIPE_TRAP_FPU_ACC);
@@ -130,55 +123,17 @@ void xnarch_init_shadow_tcb(struct xnthread *thread)
tcb->fpup = &(tcb->core.host_task->thread.fpsimd_state);
xnthread_clear_state(thread, XNFPU);
}
-#endif /* CONFIG_XENO_ARCH_FPU */
-/* Switch support functions */
-static void xnarch_tls_thread_switch(struct task_struct *next)
-{
- unsigned long tpidr, tpidrro;
-
- if (!is_compat_task()) {
- asm("mrs %0, tpidr_el0" : "=r" (tpidr));
- current->thread.tp_value = tpidr;
- }
-
- if (is_compat_thread(task_thread_info(next))) {
- tpidr = 0;
- tpidrro = next->thread.tp_value;
- } else {
- tpidr = next->thread.tp_value;
- tpidrro = 0;
- }
-
- asm(
- " msr tpidr_el0, %0\n"
- " msr tpidrro_el0, %1"
- : : "r" (tpidr), "r" (tpidrro));
-}
-
-#ifdef CONFIG_PID_IN_CONTEXTIDR
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
- asm(
- " msr contextidr_el1, %0\n"
- " isb"
- :
- : "r" (task_pid_nr(next)));
-}
-#else
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
-}
-#endif
-/* End switch support functions */
+#endif /* CONFIG_XENO_ARCH_FPU */
void xnarch_switch_to(struct xnthread *out, struct xnthread *in)
{
struct xnarchtcb *out_tcb = &out->tcb, *in_tcb = &in->tcb;
struct mm_struct *prev_mm, *next_mm;
- struct task_struct *next;
+ struct task_struct *prev, *next;
next = in_tcb->core.host_task;
+ prev = out_tcb->core.host_task;
prev_mm = out_tcb->core.active_mm;
next_mm = in_tcb->core.mm;
@@ -198,18 +153,7 @@ void xnarch_switch_to(struct xnthread *out, struct
xnthread *in)
enter_lazy_tlb(prev_mm, next);
}
- xnarch_tls_thread_switch(in_tcb->core.tip->task);
- xnarch_contextidr_thread_switch(in_tcb->core.tip->task);
-
- /*
-* Complete any pending TLB or cache maintenance on this CPU in case
-* the thread migrates to a different CPU.
-*/
- dsb(ish);
-
- disable_fpsimd();
-
- cpu_switch_to(out_tcb->core.tip->task, in_tcb->core.tip->task);
+ __switch_to(prev, next);
}
int xnarch_escalate(void)
___
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[Xenomai-git] Philippe Gerum : cobalt/arm64: use regular context switching code
Module: xenomai-3
Branch: next
Commit: c11686c23382c5540d5834900a4124be800f2940
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=c11686c23382c5540d5834900a4124be800f2940
Author: Philippe Gerum
Date: Sat Oct 17 18:07:59 2015 +0200
cobalt/arm64: use regular context switching code
Instead of open coding a copy of the regular context switching code,
use __switch_to() directly, assuming the pipeline properly serializes
switches from all domains.
---
kernel/cobalt/arch/arm64/thread.c | 66 +++--
1 file changed, 5 insertions(+), 61 deletions(-)
diff --git a/kernel/cobalt/arch/arm64/thread.c
b/kernel/cobalt/arch/arm64/thread.c
index 35dbd72..5282b0c 100644
--- a/kernel/cobalt/arch/arm64/thread.c
+++ b/kernel/cobalt/arch/arm64/thread.c
@@ -34,7 +34,7 @@
#include
#include
-#if defined(CONFIG_XENO_ARCH_FPU)
+#ifdef CONFIG_XENO_ARCH_FPU
#define FPSIMD_EN (0x3 << 20)
@@ -60,13 +60,6 @@ static void enable_fpsimd(void)
set_cpacr(cpacr);
}
-static void disable_fpsimd(void)
-{
- unsigned long cpacr = get_cpacr();
- cpacr &= ~FPSIMD_EN;
- set_cpacr(cpacr);
-}
-
int xnarch_fault_fpu_p(struct ipipe_trap_data *d)
{
return (d->exception == IPIPE_TRAP_FPU_ACC);
@@ -130,55 +123,17 @@ void xnarch_init_shadow_tcb(struct xnthread *thread)
tcb->fpup = &(tcb->core.host_task->thread.fpsimd_state);
xnthread_clear_state(thread, XNFPU);
}
-#endif /* CONFIG_XENO_ARCH_FPU */
-/* Switch support functions */
-static void xnarch_tls_thread_switch(struct task_struct *next)
-{
- unsigned long tpidr, tpidrro;
-
- if (!is_compat_task()) {
- asm("mrs %0, tpidr_el0" : "=r" (tpidr));
- current->thread.tp_value = tpidr;
- }
-
- if (is_compat_thread(task_thread_info(next))) {
- tpidr = 0;
- tpidrro = next->thread.tp_value;
- } else {
- tpidr = next->thread.tp_value;
- tpidrro = 0;
- }
-
- asm(
- " msr tpidr_el0, %0\n"
- " msr tpidrro_el0, %1"
- : : "r" (tpidr), "r" (tpidrro));
-}
-
-#ifdef CONFIG_PID_IN_CONTEXTIDR
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
- asm(
- " msr contextidr_el1, %0\n"
- " isb"
- :
- : "r" (task_pid_nr(next)));
-}
-#else
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
-}
-#endif
-/* End switch support functions */
+#endif /* CONFIG_XENO_ARCH_FPU */
void xnarch_switch_to(struct xnthread *out, struct xnthread *in)
{
struct xnarchtcb *out_tcb = &out->tcb, *in_tcb = &in->tcb;
struct mm_struct *prev_mm, *next_mm;
- struct task_struct *next;
+ struct task_struct *prev, *next;
next = in_tcb->core.host_task;
+ prev = out_tcb->core.host_task;
prev_mm = out_tcb->core.active_mm;
next_mm = in_tcb->core.mm;
@@ -198,18 +153,7 @@ void xnarch_switch_to(struct xnthread *out, struct
xnthread *in)
enter_lazy_tlb(prev_mm, next);
}
- xnarch_tls_thread_switch(in_tcb->core.tip->task);
- xnarch_contextidr_thread_switch(in_tcb->core.tip->task);
-
- /*
-* Complete any pending TLB or cache maintenance on this CPU in case
-* the thread migrates to a different CPU.
-*/
- dsb(ish);
-
- disable_fpsimd();
-
- cpu_switch_to(out_tcb->core.tip->task, in_tcb->core.tip->task);
+ __switch_to(prev, next);
}
int xnarch_escalate(void)
___
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[Xenomai-git] Philippe Gerum : cobalt/arm64: use regular context switching code
Module: xenomai-3
Branch: next
Commit: 8c1f4f1462116eba52ad07db0e12d070a73f830c
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=8c1f4f1462116eba52ad07db0e12d070a73f830c
Author: Philippe Gerum
Date: Sat Oct 17 18:07:59 2015 +0200
cobalt/arm64: use regular context switching code
Instead of open coding a copy of the regular context switching code,
use __switch_to() directly, assuming the pipeline properly serializes
switches from all domains.
---
kernel/cobalt/arch/arm64/thread.c | 66 +++--
1 file changed, 5 insertions(+), 61 deletions(-)
diff --git a/kernel/cobalt/arch/arm64/thread.c
b/kernel/cobalt/arch/arm64/thread.c
index 35dbd72..5282b0c 100644
--- a/kernel/cobalt/arch/arm64/thread.c
+++ b/kernel/cobalt/arch/arm64/thread.c
@@ -34,7 +34,7 @@
#include
#include
-#if defined(CONFIG_XENO_ARCH_FPU)
+#ifdef CONFIG_XENO_ARCH_FPU
#define FPSIMD_EN (0x3 << 20)
@@ -60,13 +60,6 @@ static void enable_fpsimd(void)
set_cpacr(cpacr);
}
-static void disable_fpsimd(void)
-{
- unsigned long cpacr = get_cpacr();
- cpacr &= ~FPSIMD_EN;
- set_cpacr(cpacr);
-}
-
int xnarch_fault_fpu_p(struct ipipe_trap_data *d)
{
return (d->exception == IPIPE_TRAP_FPU_ACC);
@@ -130,55 +123,17 @@ void xnarch_init_shadow_tcb(struct xnthread *thread)
tcb->fpup = &(tcb->core.host_task->thread.fpsimd_state);
xnthread_clear_state(thread, XNFPU);
}
-#endif /* CONFIG_XENO_ARCH_FPU */
-/* Switch support functions */
-static void xnarch_tls_thread_switch(struct task_struct *next)
-{
- unsigned long tpidr, tpidrro;
-
- if (!is_compat_task()) {
- asm("mrs %0, tpidr_el0" : "=r" (tpidr));
- current->thread.tp_value = tpidr;
- }
-
- if (is_compat_thread(task_thread_info(next))) {
- tpidr = 0;
- tpidrro = next->thread.tp_value;
- } else {
- tpidr = next->thread.tp_value;
- tpidrro = 0;
- }
-
- asm(
- " msr tpidr_el0, %0\n"
- " msr tpidrro_el0, %1"
- : : "r" (tpidr), "r" (tpidrro));
-}
-
-#ifdef CONFIG_PID_IN_CONTEXTIDR
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
- asm(
- " msr contextidr_el1, %0\n"
- " isb"
- :
- : "r" (task_pid_nr(next)));
-}
-#else
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
-}
-#endif
-/* End switch support functions */
+#endif /* CONFIG_XENO_ARCH_FPU */
void xnarch_switch_to(struct xnthread *out, struct xnthread *in)
{
struct xnarchtcb *out_tcb = &out->tcb, *in_tcb = &in->tcb;
struct mm_struct *prev_mm, *next_mm;
- struct task_struct *next;
+ struct task_struct *prev, *next;
next = in_tcb->core.host_task;
+ prev = out_tcb->core.host_task;
prev_mm = out_tcb->core.active_mm;
next_mm = in_tcb->core.mm;
@@ -198,18 +153,7 @@ void xnarch_switch_to(struct xnthread *out, struct
xnthread *in)
enter_lazy_tlb(prev_mm, next);
}
- xnarch_tls_thread_switch(in_tcb->core.tip->task);
- xnarch_contextidr_thread_switch(in_tcb->core.tip->task);
-
- /*
-* Complete any pending TLB or cache maintenance on this CPU in case
-* the thread migrates to a different CPU.
-*/
- dsb(ish);
-
- disable_fpsimd();
-
- cpu_switch_to(out_tcb->core.tip->task, in_tcb->core.tip->task);
+ __switch_to(prev, next);
}
int xnarch_escalate(void)
___
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[Xenomai-git] Philippe Gerum : cobalt/arm64: use regular context switching code
Module: xenomai-3
Branch: next
Commit: 1a2988cba085e4e81c6227575c73d04ea6c85715
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=1a2988cba085e4e81c6227575c73d04ea6c85715
Author: Philippe Gerum
Date: Sat Oct 17 18:07:59 2015 +0200
cobalt/arm64: use regular context switching code
Instead of open coding a copy of the regular context switching code,
use __switch_to() directly, assuming the pipeline properly serializes
switches from all domains.
---
kernel/cobalt/arch/arm64/thread.c | 66 +++--
1 file changed, 5 insertions(+), 61 deletions(-)
diff --git a/kernel/cobalt/arch/arm64/thread.c
b/kernel/cobalt/arch/arm64/thread.c
index 35dbd72..5282b0c 100644
--- a/kernel/cobalt/arch/arm64/thread.c
+++ b/kernel/cobalt/arch/arm64/thread.c
@@ -34,7 +34,7 @@
#include
#include
-#if defined(CONFIG_XENO_ARCH_FPU)
+#ifdef CONFIG_XENO_ARCH_FPU
#define FPSIMD_EN (0x3 << 20)
@@ -60,13 +60,6 @@ static void enable_fpsimd(void)
set_cpacr(cpacr);
}
-static void disable_fpsimd(void)
-{
- unsigned long cpacr = get_cpacr();
- cpacr &= ~FPSIMD_EN;
- set_cpacr(cpacr);
-}
-
int xnarch_fault_fpu_p(struct ipipe_trap_data *d)
{
return (d->exception == IPIPE_TRAP_FPU_ACC);
@@ -130,55 +123,17 @@ void xnarch_init_shadow_tcb(struct xnthread *thread)
tcb->fpup = &(tcb->core.host_task->thread.fpsimd_state);
xnthread_clear_state(thread, XNFPU);
}
-#endif /* CONFIG_XENO_ARCH_FPU */
-/* Switch support functions */
-static void xnarch_tls_thread_switch(struct task_struct *next)
-{
- unsigned long tpidr, tpidrro;
-
- if (!is_compat_task()) {
- asm("mrs %0, tpidr_el0" : "=r" (tpidr));
- current->thread.tp_value = tpidr;
- }
-
- if (is_compat_thread(task_thread_info(next))) {
- tpidr = 0;
- tpidrro = next->thread.tp_value;
- } else {
- tpidr = next->thread.tp_value;
- tpidrro = 0;
- }
-
- asm(
- " msr tpidr_el0, %0\n"
- " msr tpidrro_el0, %1"
- : : "r" (tpidr), "r" (tpidrro));
-}
-
-#ifdef CONFIG_PID_IN_CONTEXTIDR
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
- asm(
- " msr contextidr_el1, %0\n"
- " isb"
- :
- : "r" (task_pid_nr(next)));
-}
-#else
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
-}
-#endif
-/* End switch support functions */
+#endif /* CONFIG_XENO_ARCH_FPU */
void xnarch_switch_to(struct xnthread *out, struct xnthread *in)
{
struct xnarchtcb *out_tcb = &out->tcb, *in_tcb = &in->tcb;
struct mm_struct *prev_mm, *next_mm;
- struct task_struct *next;
+ struct task_struct *prev, *next;
next = in_tcb->core.host_task;
+ prev = out_tcb->core.host_task;
prev_mm = out_tcb->core.active_mm;
next_mm = in_tcb->core.mm;
@@ -198,18 +153,7 @@ void xnarch_switch_to(struct xnthread *out, struct
xnthread *in)
enter_lazy_tlb(prev_mm, next);
}
- xnarch_tls_thread_switch(in_tcb->core.tip->task);
- xnarch_contextidr_thread_switch(in_tcb->core.tip->task);
-
- /*
-* Complete any pending TLB or cache maintenance on this CPU in case
-* the thread migrates to a different CPU.
-*/
- dsb(ish);
-
- disable_fpsimd();
-
- cpu_switch_to(out_tcb->core.tip->task, in_tcb->core.tip->task);
+ __switch_to(prev, next);
}
int xnarch_escalate(void)
___
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[Xenomai-git] Philippe Gerum : cobalt/arm64: use regular context switching code
Module: xenomai-3
Branch: next
Commit: fad5333157dd756584aa8ae9112d5cb93b26637b
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=fad5333157dd756584aa8ae9112d5cb93b26637b
Author: Philippe Gerum
Date: Sat Oct 17 18:07:59 2015 +0200
cobalt/arm64: use regular context switching code
Instead of open coding a copy of the regular context switching code,
use __switch_to() directly, assuming the pipeline properly serializes
switches from all domains.
---
kernel/cobalt/arch/arm64/thread.c | 66 +++--
1 file changed, 5 insertions(+), 61 deletions(-)
diff --git a/kernel/cobalt/arch/arm64/thread.c
b/kernel/cobalt/arch/arm64/thread.c
index 35dbd72..5282b0c 100644
--- a/kernel/cobalt/arch/arm64/thread.c
+++ b/kernel/cobalt/arch/arm64/thread.c
@@ -34,7 +34,7 @@
#include
#include
-#if defined(CONFIG_XENO_ARCH_FPU)
+#ifdef CONFIG_XENO_ARCH_FPU
#define FPSIMD_EN (0x3 << 20)
@@ -60,13 +60,6 @@ static void enable_fpsimd(void)
set_cpacr(cpacr);
}
-static void disable_fpsimd(void)
-{
- unsigned long cpacr = get_cpacr();
- cpacr &= ~FPSIMD_EN;
- set_cpacr(cpacr);
-}
-
int xnarch_fault_fpu_p(struct ipipe_trap_data *d)
{
return (d->exception == IPIPE_TRAP_FPU_ACC);
@@ -130,55 +123,17 @@ void xnarch_init_shadow_tcb(struct xnthread *thread)
tcb->fpup = &(tcb->core.host_task->thread.fpsimd_state);
xnthread_clear_state(thread, XNFPU);
}
-#endif /* CONFIG_XENO_ARCH_FPU */
-/* Switch support functions */
-static void xnarch_tls_thread_switch(struct task_struct *next)
-{
- unsigned long tpidr, tpidrro;
-
- if (!is_compat_task()) {
- asm("mrs %0, tpidr_el0" : "=r" (tpidr));
- current->thread.tp_value = tpidr;
- }
-
- if (is_compat_thread(task_thread_info(next))) {
- tpidr = 0;
- tpidrro = next->thread.tp_value;
- } else {
- tpidr = next->thread.tp_value;
- tpidrro = 0;
- }
-
- asm(
- " msr tpidr_el0, %0\n"
- " msr tpidrro_el0, %1"
- : : "r" (tpidr), "r" (tpidrro));
-}
-
-#ifdef CONFIG_PID_IN_CONTEXTIDR
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
- asm(
- " msr contextidr_el1, %0\n"
- " isb"
- :
- : "r" (task_pid_nr(next)));
-}
-#else
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
-}
-#endif
-/* End switch support functions */
+#endif /* CONFIG_XENO_ARCH_FPU */
void xnarch_switch_to(struct xnthread *out, struct xnthread *in)
{
struct xnarchtcb *out_tcb = &out->tcb, *in_tcb = &in->tcb;
struct mm_struct *prev_mm, *next_mm;
- struct task_struct *next;
+ struct task_struct *prev, *next;
next = in_tcb->core.host_task;
+ prev = out_tcb->core.host_task;
prev_mm = out_tcb->core.active_mm;
next_mm = in_tcb->core.mm;
@@ -198,18 +153,7 @@ void xnarch_switch_to(struct xnthread *out, struct
xnthread *in)
enter_lazy_tlb(prev_mm, next);
}
- xnarch_tls_thread_switch(in_tcb->core.tip->task);
- xnarch_contextidr_thread_switch(in_tcb->core.tip->task);
-
- /*
-* Complete any pending TLB or cache maintenance on this CPU in case
-* the thread migrates to a different CPU.
-*/
- dsb(ish);
-
- disable_fpsimd();
-
- cpu_switch_to(out_tcb->core.tip->task, in_tcb->core.tip->task);
+ __switch_to(prev, next);
}
int xnarch_escalate(void)
___
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[Xenomai-git] Philippe Gerum : cobalt/arm64: use regular context switching code
Module: xenomai-3
Branch: next
Commit: 9ecde186d7a97981e8738c2b8328f353e1b4bd2c
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=9ecde186d7a97981e8738c2b8328f353e1b4bd2c
Author: Philippe Gerum
Date: Sat Oct 17 18:07:59 2015 +0200
cobalt/arm64: use regular context switching code
Instead of open coding a copy of the regular context switching code,
use __switch_to() directly, assuming the pipeline properly serializes
switches from all domains.
---
kernel/cobalt/arch/arm64/thread.c | 66 +++--
1 file changed, 5 insertions(+), 61 deletions(-)
diff --git a/kernel/cobalt/arch/arm64/thread.c
b/kernel/cobalt/arch/arm64/thread.c
index 35dbd72..5282b0c 100644
--- a/kernel/cobalt/arch/arm64/thread.c
+++ b/kernel/cobalt/arch/arm64/thread.c
@@ -34,7 +34,7 @@
#include
#include
-#if defined(CONFIG_XENO_ARCH_FPU)
+#ifdef CONFIG_XENO_ARCH_FPU
#define FPSIMD_EN (0x3 << 20)
@@ -60,13 +60,6 @@ static void enable_fpsimd(void)
set_cpacr(cpacr);
}
-static void disable_fpsimd(void)
-{
- unsigned long cpacr = get_cpacr();
- cpacr &= ~FPSIMD_EN;
- set_cpacr(cpacr);
-}
-
int xnarch_fault_fpu_p(struct ipipe_trap_data *d)
{
return (d->exception == IPIPE_TRAP_FPU_ACC);
@@ -130,55 +123,17 @@ void xnarch_init_shadow_tcb(struct xnthread *thread)
tcb->fpup = &(tcb->core.host_task->thread.fpsimd_state);
xnthread_clear_state(thread, XNFPU);
}
-#endif /* CONFIG_XENO_ARCH_FPU */
-/* Switch support functions */
-static void xnarch_tls_thread_switch(struct task_struct *next)
-{
- unsigned long tpidr, tpidrro;
-
- if (!is_compat_task()) {
- asm("mrs %0, tpidr_el0" : "=r" (tpidr));
- current->thread.tp_value = tpidr;
- }
-
- if (is_compat_thread(task_thread_info(next))) {
- tpidr = 0;
- tpidrro = next->thread.tp_value;
- } else {
- tpidr = next->thread.tp_value;
- tpidrro = 0;
- }
-
- asm(
- " msr tpidr_el0, %0\n"
- " msr tpidrro_el0, %1"
- : : "r" (tpidr), "r" (tpidrro));
-}
-
-#ifdef CONFIG_PID_IN_CONTEXTIDR
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
- asm(
- " msr contextidr_el1, %0\n"
- " isb"
- :
- : "r" (task_pid_nr(next)));
-}
-#else
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
-}
-#endif
-/* End switch support functions */
+#endif /* CONFIG_XENO_ARCH_FPU */
void xnarch_switch_to(struct xnthread *out, struct xnthread *in)
{
struct xnarchtcb *out_tcb = &out->tcb, *in_tcb = &in->tcb;
struct mm_struct *prev_mm, *next_mm;
- struct task_struct *next;
+ struct task_struct *prev, *next;
next = in_tcb->core.host_task;
+ prev = out_tcb->core.host_task;
prev_mm = out_tcb->core.active_mm;
next_mm = in_tcb->core.mm;
@@ -198,18 +153,7 @@ void xnarch_switch_to(struct xnthread *out, struct
xnthread *in)
enter_lazy_tlb(prev_mm, next);
}
- xnarch_tls_thread_switch(in_tcb->core.tip->task);
- xnarch_contextidr_thread_switch(in_tcb->core.tip->task);
-
- /*
-* Complete any pending TLB or cache maintenance on this CPU in case
-* the thread migrates to a different CPU.
-*/
- dsb(ish);
-
- disable_fpsimd();
-
- cpu_switch_to(out_tcb->core.tip->task, in_tcb->core.tip->task);
+ __switch_to(prev, next);
}
int xnarch_escalate(void)
___
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[Xenomai-git] Philippe Gerum : cobalt/arm64: use regular context switching code
Module: xenomai-3
Branch: next
Commit: 3754d918c64fc2aa512debb4fbc0f26f16476ebe
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=3754d918c64fc2aa512debb4fbc0f26f16476ebe
Author: Philippe Gerum
Date: Sat Oct 17 18:07:59 2015 +0200
cobalt/arm64: use regular context switching code
Instead of open coding a copy of the regular context switching code,
use __switch_to() directly, assuming the pipeline properly serializes
switches from all domains.
---
kernel/cobalt/arch/arm64/thread.c | 66 +++--
1 file changed, 5 insertions(+), 61 deletions(-)
diff --git a/kernel/cobalt/arch/arm64/thread.c
b/kernel/cobalt/arch/arm64/thread.c
index 35dbd72..5282b0c 100644
--- a/kernel/cobalt/arch/arm64/thread.c
+++ b/kernel/cobalt/arch/arm64/thread.c
@@ -34,7 +34,7 @@
#include
#include
-#if defined(CONFIG_XENO_ARCH_FPU)
+#ifdef CONFIG_XENO_ARCH_FPU
#define FPSIMD_EN (0x3 << 20)
@@ -60,13 +60,6 @@ static void enable_fpsimd(void)
set_cpacr(cpacr);
}
-static void disable_fpsimd(void)
-{
- unsigned long cpacr = get_cpacr();
- cpacr &= ~FPSIMD_EN;
- set_cpacr(cpacr);
-}
-
int xnarch_fault_fpu_p(struct ipipe_trap_data *d)
{
return (d->exception == IPIPE_TRAP_FPU_ACC);
@@ -130,55 +123,17 @@ void xnarch_init_shadow_tcb(struct xnthread *thread)
tcb->fpup = &(tcb->core.host_task->thread.fpsimd_state);
xnthread_clear_state(thread, XNFPU);
}
-#endif /* CONFIG_XENO_ARCH_FPU */
-/* Switch support functions */
-static void xnarch_tls_thread_switch(struct task_struct *next)
-{
- unsigned long tpidr, tpidrro;
-
- if (!is_compat_task()) {
- asm("mrs %0, tpidr_el0" : "=r" (tpidr));
- current->thread.tp_value = tpidr;
- }
-
- if (is_compat_thread(task_thread_info(next))) {
- tpidr = 0;
- tpidrro = next->thread.tp_value;
- } else {
- tpidr = next->thread.tp_value;
- tpidrro = 0;
- }
-
- asm(
- " msr tpidr_el0, %0\n"
- " msr tpidrro_el0, %1"
- : : "r" (tpidr), "r" (tpidrro));
-}
-
-#ifdef CONFIG_PID_IN_CONTEXTIDR
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
- asm(
- " msr contextidr_el1, %0\n"
- " isb"
- :
- : "r" (task_pid_nr(next)));
-}
-#else
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
-}
-#endif
-/* End switch support functions */
+#endif /* CONFIG_XENO_ARCH_FPU */
void xnarch_switch_to(struct xnthread *out, struct xnthread *in)
{
struct xnarchtcb *out_tcb = &out->tcb, *in_tcb = &in->tcb;
struct mm_struct *prev_mm, *next_mm;
- struct task_struct *next;
+ struct task_struct *prev, *next;
next = in_tcb->core.host_task;
+ prev = out_tcb->core.host_task;
prev_mm = out_tcb->core.active_mm;
next_mm = in_tcb->core.mm;
@@ -198,18 +153,7 @@ void xnarch_switch_to(struct xnthread *out, struct
xnthread *in)
enter_lazy_tlb(prev_mm, next);
}
- xnarch_tls_thread_switch(in_tcb->core.tip->task);
- xnarch_contextidr_thread_switch(in_tcb->core.tip->task);
-
- /*
-* Complete any pending TLB or cache maintenance on this CPU in case
-* the thread migrates to a different CPU.
-*/
- dsb(ish);
-
- disable_fpsimd();
-
- cpu_switch_to(out_tcb->core.tip->task, in_tcb->core.tip->task);
+ __switch_to(prev, next);
}
int xnarch_escalate(void)
___
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[Xenomai-git] Philippe Gerum : cobalt/arm64: use regular context switching code
Module: xenomai-3
Branch: next
Commit: d767a4f2c4bfaba32e3b88f53847a267d3d96f2d
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=d767a4f2c4bfaba32e3b88f53847a267d3d96f2d
Author: Philippe Gerum
Date: Sat Oct 17 18:07:59 2015 +0200
cobalt/arm64: use regular context switching code
Instead of open coding a copy of the regular context switching code,
use __switch_to() directly, assuming the pipeline properly serializes
switches from all domains.
---
kernel/cobalt/arch/arm64/thread.c | 66 +++--
1 file changed, 5 insertions(+), 61 deletions(-)
diff --git a/kernel/cobalt/arch/arm64/thread.c
b/kernel/cobalt/arch/arm64/thread.c
index 35dbd72..5282b0c 100644
--- a/kernel/cobalt/arch/arm64/thread.c
+++ b/kernel/cobalt/arch/arm64/thread.c
@@ -34,7 +34,7 @@
#include
#include
-#if defined(CONFIG_XENO_ARCH_FPU)
+#ifdef CONFIG_XENO_ARCH_FPU
#define FPSIMD_EN (0x3 << 20)
@@ -60,13 +60,6 @@ static void enable_fpsimd(void)
set_cpacr(cpacr);
}
-static void disable_fpsimd(void)
-{
- unsigned long cpacr = get_cpacr();
- cpacr &= ~FPSIMD_EN;
- set_cpacr(cpacr);
-}
-
int xnarch_fault_fpu_p(struct ipipe_trap_data *d)
{
return (d->exception == IPIPE_TRAP_FPU_ACC);
@@ -130,55 +123,17 @@ void xnarch_init_shadow_tcb(struct xnthread *thread)
tcb->fpup = &(tcb->core.host_task->thread.fpsimd_state);
xnthread_clear_state(thread, XNFPU);
}
-#endif /* CONFIG_XENO_ARCH_FPU */
-/* Switch support functions */
-static void xnarch_tls_thread_switch(struct task_struct *next)
-{
- unsigned long tpidr, tpidrro;
-
- if (!is_compat_task()) {
- asm("mrs %0, tpidr_el0" : "=r" (tpidr));
- current->thread.tp_value = tpidr;
- }
-
- if (is_compat_thread(task_thread_info(next))) {
- tpidr = 0;
- tpidrro = next->thread.tp_value;
- } else {
- tpidr = next->thread.tp_value;
- tpidrro = 0;
- }
-
- asm(
- " msr tpidr_el0, %0\n"
- " msr tpidrro_el0, %1"
- : : "r" (tpidr), "r" (tpidrro));
-}
-
-#ifdef CONFIG_PID_IN_CONTEXTIDR
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
- asm(
- " msr contextidr_el1, %0\n"
- " isb"
- :
- : "r" (task_pid_nr(next)));
-}
-#else
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
-}
-#endif
-/* End switch support functions */
+#endif /* CONFIG_XENO_ARCH_FPU */
void xnarch_switch_to(struct xnthread *out, struct xnthread *in)
{
struct xnarchtcb *out_tcb = &out->tcb, *in_tcb = &in->tcb;
struct mm_struct *prev_mm, *next_mm;
- struct task_struct *next;
+ struct task_struct *prev, *next;
next = in_tcb->core.host_task;
+ prev = out_tcb->core.host_task;
prev_mm = out_tcb->core.active_mm;
next_mm = in_tcb->core.mm;
@@ -198,18 +153,7 @@ void xnarch_switch_to(struct xnthread *out, struct
xnthread *in)
enter_lazy_tlb(prev_mm, next);
}
- xnarch_tls_thread_switch(in_tcb->core.tip->task);
- xnarch_contextidr_thread_switch(in_tcb->core.tip->task);
-
- /*
-* Complete any pending TLB or cache maintenance on this CPU in case
-* the thread migrates to a different CPU.
-*/
- dsb(ish);
-
- disable_fpsimd();
-
- cpu_switch_to(out_tcb->core.tip->task, in_tcb->core.tip->task);
+ __switch_to(prev, next);
}
int xnarch_escalate(void)
___
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[Xenomai-git] Philippe Gerum : cobalt/arm64: use regular context switching code
Module: xenomai-3
Branch: next
Commit: 407c6b25d620b9a81105f0f53d22d54313080f7e
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=407c6b25d620b9a81105f0f53d22d54313080f7e
Author: Philippe Gerum
Date: Sat Oct 17 18:07:59 2015 +0200
cobalt/arm64: use regular context switching code
Instead of open coding a copy of the regular context switching code,
use __switch_to() directly, assuming the pipeline properly serializes
switches from all domains.
---
kernel/cobalt/arch/arm64/thread.c | 66 +++--
1 file changed, 5 insertions(+), 61 deletions(-)
diff --git a/kernel/cobalt/arch/arm64/thread.c
b/kernel/cobalt/arch/arm64/thread.c
index 35dbd72..5282b0c 100644
--- a/kernel/cobalt/arch/arm64/thread.c
+++ b/kernel/cobalt/arch/arm64/thread.c
@@ -34,7 +34,7 @@
#include
#include
-#if defined(CONFIG_XENO_ARCH_FPU)
+#ifdef CONFIG_XENO_ARCH_FPU
#define FPSIMD_EN (0x3 << 20)
@@ -60,13 +60,6 @@ static void enable_fpsimd(void)
set_cpacr(cpacr);
}
-static void disable_fpsimd(void)
-{
- unsigned long cpacr = get_cpacr();
- cpacr &= ~FPSIMD_EN;
- set_cpacr(cpacr);
-}
-
int xnarch_fault_fpu_p(struct ipipe_trap_data *d)
{
return (d->exception == IPIPE_TRAP_FPU_ACC);
@@ -130,55 +123,17 @@ void xnarch_init_shadow_tcb(struct xnthread *thread)
tcb->fpup = &(tcb->core.host_task->thread.fpsimd_state);
xnthread_clear_state(thread, XNFPU);
}
-#endif /* CONFIG_XENO_ARCH_FPU */
-/* Switch support functions */
-static void xnarch_tls_thread_switch(struct task_struct *next)
-{
- unsigned long tpidr, tpidrro;
-
- if (!is_compat_task()) {
- asm("mrs %0, tpidr_el0" : "=r" (tpidr));
- current->thread.tp_value = tpidr;
- }
-
- if (is_compat_thread(task_thread_info(next))) {
- tpidr = 0;
- tpidrro = next->thread.tp_value;
- } else {
- tpidr = next->thread.tp_value;
- tpidrro = 0;
- }
-
- asm(
- " msr tpidr_el0, %0\n"
- " msr tpidrro_el0, %1"
- : : "r" (tpidr), "r" (tpidrro));
-}
-
-#ifdef CONFIG_PID_IN_CONTEXTIDR
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
- asm(
- " msr contextidr_el1, %0\n"
- " isb"
- :
- : "r" (task_pid_nr(next)));
-}
-#else
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
-}
-#endif
-/* End switch support functions */
+#endif /* CONFIG_XENO_ARCH_FPU */
void xnarch_switch_to(struct xnthread *out, struct xnthread *in)
{
struct xnarchtcb *out_tcb = &out->tcb, *in_tcb = &in->tcb;
struct mm_struct *prev_mm, *next_mm;
- struct task_struct *next;
+ struct task_struct *prev, *next;
next = in_tcb->core.host_task;
+ prev = out_tcb->core.host_task;
prev_mm = out_tcb->core.active_mm;
next_mm = in_tcb->core.mm;
@@ -198,18 +153,7 @@ void xnarch_switch_to(struct xnthread *out, struct
xnthread *in)
enter_lazy_tlb(prev_mm, next);
}
- xnarch_tls_thread_switch(in_tcb->core.tip->task);
- xnarch_contextidr_thread_switch(in_tcb->core.tip->task);
-
- /*
-* Complete any pending TLB or cache maintenance on this CPU in case
-* the thread migrates to a different CPU.
-*/
- dsb(ish);
-
- disable_fpsimd();
-
- cpu_switch_to(out_tcb->core.tip->task, in_tcb->core.tip->task);
+ __switch_to(prev, next);
}
int xnarch_escalate(void)
___
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[Xenomai-git] Philippe Gerum : cobalt/arm64: use regular context switching code
Module: xenomai-3
Branch: next
Commit: e411109e827530f2b0c4743d9855c8498d72b60e
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=e411109e827530f2b0c4743d9855c8498d72b60e
Author: Philippe Gerum
Date: Sat Oct 17 18:07:59 2015 +0200
cobalt/arm64: use regular context switching code
Instead of open coding a copy of the regular context switching code,
use __switch_to() directly, assuming the pipeline properly serializes
switches from all domains.
---
kernel/cobalt/arch/arm64/thread.c | 66 +++--
1 file changed, 5 insertions(+), 61 deletions(-)
diff --git a/kernel/cobalt/arch/arm64/thread.c
b/kernel/cobalt/arch/arm64/thread.c
index 35dbd72..5282b0c 100644
--- a/kernel/cobalt/arch/arm64/thread.c
+++ b/kernel/cobalt/arch/arm64/thread.c
@@ -34,7 +34,7 @@
#include
#include
-#if defined(CONFIG_XENO_ARCH_FPU)
+#ifdef CONFIG_XENO_ARCH_FPU
#define FPSIMD_EN (0x3 << 20)
@@ -60,13 +60,6 @@ static void enable_fpsimd(void)
set_cpacr(cpacr);
}
-static void disable_fpsimd(void)
-{
- unsigned long cpacr = get_cpacr();
- cpacr &= ~FPSIMD_EN;
- set_cpacr(cpacr);
-}
-
int xnarch_fault_fpu_p(struct ipipe_trap_data *d)
{
return (d->exception == IPIPE_TRAP_FPU_ACC);
@@ -130,55 +123,17 @@ void xnarch_init_shadow_tcb(struct xnthread *thread)
tcb->fpup = &(tcb->core.host_task->thread.fpsimd_state);
xnthread_clear_state(thread, XNFPU);
}
-#endif /* CONFIG_XENO_ARCH_FPU */
-/* Switch support functions */
-static void xnarch_tls_thread_switch(struct task_struct *next)
-{
- unsigned long tpidr, tpidrro;
-
- if (!is_compat_task()) {
- asm("mrs %0, tpidr_el0" : "=r" (tpidr));
- current->thread.tp_value = tpidr;
- }
-
- if (is_compat_thread(task_thread_info(next))) {
- tpidr = 0;
- tpidrro = next->thread.tp_value;
- } else {
- tpidr = next->thread.tp_value;
- tpidrro = 0;
- }
-
- asm(
- " msr tpidr_el0, %0\n"
- " msr tpidrro_el0, %1"
- : : "r" (tpidr), "r" (tpidrro));
-}
-
-#ifdef CONFIG_PID_IN_CONTEXTIDR
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
- asm(
- " msr contextidr_el1, %0\n"
- " isb"
- :
- : "r" (task_pid_nr(next)));
-}
-#else
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
-}
-#endif
-/* End switch support functions */
+#endif /* CONFIG_XENO_ARCH_FPU */
void xnarch_switch_to(struct xnthread *out, struct xnthread *in)
{
struct xnarchtcb *out_tcb = &out->tcb, *in_tcb = &in->tcb;
struct mm_struct *prev_mm, *next_mm;
- struct task_struct *next;
+ struct task_struct *prev, *next;
next = in_tcb->core.host_task;
+ prev = out_tcb->core.host_task;
prev_mm = out_tcb->core.active_mm;
next_mm = in_tcb->core.mm;
@@ -198,18 +153,7 @@ void xnarch_switch_to(struct xnthread *out, struct
xnthread *in)
enter_lazy_tlb(prev_mm, next);
}
- xnarch_tls_thread_switch(in_tcb->core.tip->task);
- xnarch_contextidr_thread_switch(in_tcb->core.tip->task);
-
- /*
-* Complete any pending TLB or cache maintenance on this CPU in case
-* the thread migrates to a different CPU.
-*/
- dsb(ish);
-
- disable_fpsimd();
-
- cpu_switch_to(out_tcb->core.tip->task, in_tcb->core.tip->task);
+ __switch_to(prev, next);
}
int xnarch_escalate(void)
___
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[Xenomai-git] Philippe Gerum : cobalt/arm64: use regular context switching code
Module: xenomai-3
Branch: next
Commit: 8988aef3f858677eaa843b35d206377681d3e632
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=8988aef3f858677eaa843b35d206377681d3e632
Author: Philippe Gerum
Date: Sat Oct 17 18:07:59 2015 +0200
cobalt/arm64: use regular context switching code
Instead of open coding a copy of the regular context switching code,
use __switch_to() directly, assuming the pipeline properly serializes
switches from all domains.
---
kernel/cobalt/arch/arm64/thread.c | 66 +++--
1 file changed, 5 insertions(+), 61 deletions(-)
diff --git a/kernel/cobalt/arch/arm64/thread.c
b/kernel/cobalt/arch/arm64/thread.c
index 35dbd72..5282b0c 100644
--- a/kernel/cobalt/arch/arm64/thread.c
+++ b/kernel/cobalt/arch/arm64/thread.c
@@ -34,7 +34,7 @@
#include
#include
-#if defined(CONFIG_XENO_ARCH_FPU)
+#ifdef CONFIG_XENO_ARCH_FPU
#define FPSIMD_EN (0x3 << 20)
@@ -60,13 +60,6 @@ static void enable_fpsimd(void)
set_cpacr(cpacr);
}
-static void disable_fpsimd(void)
-{
- unsigned long cpacr = get_cpacr();
- cpacr &= ~FPSIMD_EN;
- set_cpacr(cpacr);
-}
-
int xnarch_fault_fpu_p(struct ipipe_trap_data *d)
{
return (d->exception == IPIPE_TRAP_FPU_ACC);
@@ -130,55 +123,17 @@ void xnarch_init_shadow_tcb(struct xnthread *thread)
tcb->fpup = &(tcb->core.host_task->thread.fpsimd_state);
xnthread_clear_state(thread, XNFPU);
}
-#endif /* CONFIG_XENO_ARCH_FPU */
-/* Switch support functions */
-static void xnarch_tls_thread_switch(struct task_struct *next)
-{
- unsigned long tpidr, tpidrro;
-
- if (!is_compat_task()) {
- asm("mrs %0, tpidr_el0" : "=r" (tpidr));
- current->thread.tp_value = tpidr;
- }
-
- if (is_compat_thread(task_thread_info(next))) {
- tpidr = 0;
- tpidrro = next->thread.tp_value;
- } else {
- tpidr = next->thread.tp_value;
- tpidrro = 0;
- }
-
- asm(
- " msr tpidr_el0, %0\n"
- " msr tpidrro_el0, %1"
- : : "r" (tpidr), "r" (tpidrro));
-}
-
-#ifdef CONFIG_PID_IN_CONTEXTIDR
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
- asm(
- " msr contextidr_el1, %0\n"
- " isb"
- :
- : "r" (task_pid_nr(next)));
-}
-#else
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
-}
-#endif
-/* End switch support functions */
+#endif /* CONFIG_XENO_ARCH_FPU */
void xnarch_switch_to(struct xnthread *out, struct xnthread *in)
{
struct xnarchtcb *out_tcb = &out->tcb, *in_tcb = &in->tcb;
struct mm_struct *prev_mm, *next_mm;
- struct task_struct *next;
+ struct task_struct *prev, *next;
next = in_tcb->core.host_task;
+ prev = out_tcb->core.host_task;
prev_mm = out_tcb->core.active_mm;
next_mm = in_tcb->core.mm;
@@ -198,18 +153,7 @@ void xnarch_switch_to(struct xnthread *out, struct
xnthread *in)
enter_lazy_tlb(prev_mm, next);
}
- xnarch_tls_thread_switch(in_tcb->core.tip->task);
- xnarch_contextidr_thread_switch(in_tcb->core.tip->task);
-
- /*
-* Complete any pending TLB or cache maintenance on this CPU in case
-* the thread migrates to a different CPU.
-*/
- dsb(ish);
-
- disable_fpsimd();
-
- cpu_switch_to(out_tcb->core.tip->task, in_tcb->core.tip->task);
+ __switch_to(prev, next);
}
int xnarch_escalate(void)
___
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[Xenomai-git] Philippe Gerum : cobalt/arm64: use regular context switching code
Module: xenomai-3
Branch: next
Commit: 1b674296b5ee9fdad5eebfe9a47bbf2d8e83c0b1
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=1b674296b5ee9fdad5eebfe9a47bbf2d8e83c0b1
Author: Philippe Gerum
Date: Sat Oct 17 18:07:59 2015 +0200
cobalt/arm64: use regular context switching code
Instead of open coding a copy of the regular context switching code,
use __switch_to() directly, assuming the pipeline properly serializes
switches from all domains.
---
kernel/cobalt/arch/arm64/thread.c | 66 +++--
1 file changed, 5 insertions(+), 61 deletions(-)
diff --git a/kernel/cobalt/arch/arm64/thread.c
b/kernel/cobalt/arch/arm64/thread.c
index 35dbd72..5282b0c 100644
--- a/kernel/cobalt/arch/arm64/thread.c
+++ b/kernel/cobalt/arch/arm64/thread.c
@@ -34,7 +34,7 @@
#include
#include
-#if defined(CONFIG_XENO_ARCH_FPU)
+#ifdef CONFIG_XENO_ARCH_FPU
#define FPSIMD_EN (0x3 << 20)
@@ -60,13 +60,6 @@ static void enable_fpsimd(void)
set_cpacr(cpacr);
}
-static void disable_fpsimd(void)
-{
- unsigned long cpacr = get_cpacr();
- cpacr &= ~FPSIMD_EN;
- set_cpacr(cpacr);
-}
-
int xnarch_fault_fpu_p(struct ipipe_trap_data *d)
{
return (d->exception == IPIPE_TRAP_FPU_ACC);
@@ -130,55 +123,17 @@ void xnarch_init_shadow_tcb(struct xnthread *thread)
tcb->fpup = &(tcb->core.host_task->thread.fpsimd_state);
xnthread_clear_state(thread, XNFPU);
}
-#endif /* CONFIG_XENO_ARCH_FPU */
-/* Switch support functions */
-static void xnarch_tls_thread_switch(struct task_struct *next)
-{
- unsigned long tpidr, tpidrro;
-
- if (!is_compat_task()) {
- asm("mrs %0, tpidr_el0" : "=r" (tpidr));
- current->thread.tp_value = tpidr;
- }
-
- if (is_compat_thread(task_thread_info(next))) {
- tpidr = 0;
- tpidrro = next->thread.tp_value;
- } else {
- tpidr = next->thread.tp_value;
- tpidrro = 0;
- }
-
- asm(
- " msr tpidr_el0, %0\n"
- " msr tpidrro_el0, %1"
- : : "r" (tpidr), "r" (tpidrro));
-}
-
-#ifdef CONFIG_PID_IN_CONTEXTIDR
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
- asm(
- " msr contextidr_el1, %0\n"
- " isb"
- :
- : "r" (task_pid_nr(next)));
-}
-#else
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
-}
-#endif
-/* End switch support functions */
+#endif /* CONFIG_XENO_ARCH_FPU */
void xnarch_switch_to(struct xnthread *out, struct xnthread *in)
{
struct xnarchtcb *out_tcb = &out->tcb, *in_tcb = &in->tcb;
struct mm_struct *prev_mm, *next_mm;
- struct task_struct *next;
+ struct task_struct *prev, *next;
next = in_tcb->core.host_task;
+ prev = out_tcb->core.host_task;
prev_mm = out_tcb->core.active_mm;
next_mm = in_tcb->core.mm;
@@ -198,18 +153,7 @@ void xnarch_switch_to(struct xnthread *out, struct
xnthread *in)
enter_lazy_tlb(prev_mm, next);
}
- xnarch_tls_thread_switch(in_tcb->core.tip->task);
- xnarch_contextidr_thread_switch(in_tcb->core.tip->task);
-
- /*
-* Complete any pending TLB or cache maintenance on this CPU in case
-* the thread migrates to a different CPU.
-*/
- dsb(ish);
-
- disable_fpsimd();
-
- cpu_switch_to(out_tcb->core.tip->task, in_tcb->core.tip->task);
+ __switch_to(prev, next);
}
int xnarch_escalate(void)
___
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[Xenomai-git] Philippe Gerum : cobalt/arm64: use regular context switching code
Module: xenomai-3
Branch: arm64
Commit: ad29900a74606076a4fc77e12aba972d7d020706
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=ad29900a74606076a4fc77e12aba972d7d020706
Author: Philippe Gerum
Date: Sat Oct 17 18:07:59 2015 +0200
cobalt/arm64: use regular context switching code
Instead of open coding a copy of the regular context switching code,
use __switch_to() directly, assuming the pipeline properly serializes
switches from all domains.
---
kernel/cobalt/arch/arm64/thread.c | 66 +++--
1 file changed, 5 insertions(+), 61 deletions(-)
diff --git a/kernel/cobalt/arch/arm64/thread.c
b/kernel/cobalt/arch/arm64/thread.c
index 35dbd72..5282b0c 100644
--- a/kernel/cobalt/arch/arm64/thread.c
+++ b/kernel/cobalt/arch/arm64/thread.c
@@ -34,7 +34,7 @@
#include
#include
-#if defined(CONFIG_XENO_ARCH_FPU)
+#ifdef CONFIG_XENO_ARCH_FPU
#define FPSIMD_EN (0x3 << 20)
@@ -60,13 +60,6 @@ static void enable_fpsimd(void)
set_cpacr(cpacr);
}
-static void disable_fpsimd(void)
-{
- unsigned long cpacr = get_cpacr();
- cpacr &= ~FPSIMD_EN;
- set_cpacr(cpacr);
-}
-
int xnarch_fault_fpu_p(struct ipipe_trap_data *d)
{
return (d->exception == IPIPE_TRAP_FPU_ACC);
@@ -130,55 +123,17 @@ void xnarch_init_shadow_tcb(struct xnthread *thread)
tcb->fpup = &(tcb->core.host_task->thread.fpsimd_state);
xnthread_clear_state(thread, XNFPU);
}
-#endif /* CONFIG_XENO_ARCH_FPU */
-/* Switch support functions */
-static void xnarch_tls_thread_switch(struct task_struct *next)
-{
- unsigned long tpidr, tpidrro;
-
- if (!is_compat_task()) {
- asm("mrs %0, tpidr_el0" : "=r" (tpidr));
- current->thread.tp_value = tpidr;
- }
-
- if (is_compat_thread(task_thread_info(next))) {
- tpidr = 0;
- tpidrro = next->thread.tp_value;
- } else {
- tpidr = next->thread.tp_value;
- tpidrro = 0;
- }
-
- asm(
- " msr tpidr_el0, %0\n"
- " msr tpidrro_el0, %1"
- : : "r" (tpidr), "r" (tpidrro));
-}
-
-#ifdef CONFIG_PID_IN_CONTEXTIDR
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
- asm(
- " msr contextidr_el1, %0\n"
- " isb"
- :
- : "r" (task_pid_nr(next)));
-}
-#else
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
-}
-#endif
-/* End switch support functions */
+#endif /* CONFIG_XENO_ARCH_FPU */
void xnarch_switch_to(struct xnthread *out, struct xnthread *in)
{
struct xnarchtcb *out_tcb = &out->tcb, *in_tcb = &in->tcb;
struct mm_struct *prev_mm, *next_mm;
- struct task_struct *next;
+ struct task_struct *prev, *next;
next = in_tcb->core.host_task;
+ prev = out_tcb->core.host_task;
prev_mm = out_tcb->core.active_mm;
next_mm = in_tcb->core.mm;
@@ -198,18 +153,7 @@ void xnarch_switch_to(struct xnthread *out, struct
xnthread *in)
enter_lazy_tlb(prev_mm, next);
}
- xnarch_tls_thread_switch(in_tcb->core.tip->task);
- xnarch_contextidr_thread_switch(in_tcb->core.tip->task);
-
- /*
-* Complete any pending TLB or cache maintenance on this CPU in case
-* the thread migrates to a different CPU.
-*/
- dsb(ish);
-
- disable_fpsimd();
-
- cpu_switch_to(out_tcb->core.tip->task, in_tcb->core.tip->task);
+ __switch_to(prev, next);
}
int xnarch_escalate(void)
___
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[Xenomai-git] Philippe Gerum : cobalt/arm64: use regular context switching code
Module: xenomai-3
Branch: arm64
Commit: 8333184f4658da82d616f51fea1e64b29f6f640f
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=8333184f4658da82d616f51fea1e64b29f6f640f
Author: Philippe Gerum
Date: Sat Oct 17 18:07:59 2015 +0200
cobalt/arm64: use regular context switching code
Instead of open coding a copy of the regular context switching code,
use __switch_to() directly, assuming the pipeline properly serializes
switches from all domains.
---
kernel/cobalt/arch/arm64/thread.c | 66 +++--
1 file changed, 5 insertions(+), 61 deletions(-)
diff --git a/kernel/cobalt/arch/arm64/thread.c
b/kernel/cobalt/arch/arm64/thread.c
index 35dbd72..5282b0c 100644
--- a/kernel/cobalt/arch/arm64/thread.c
+++ b/kernel/cobalt/arch/arm64/thread.c
@@ -34,7 +34,7 @@
#include
#include
-#if defined(CONFIG_XENO_ARCH_FPU)
+#ifdef CONFIG_XENO_ARCH_FPU
#define FPSIMD_EN (0x3 << 20)
@@ -60,13 +60,6 @@ static void enable_fpsimd(void)
set_cpacr(cpacr);
}
-static void disable_fpsimd(void)
-{
- unsigned long cpacr = get_cpacr();
- cpacr &= ~FPSIMD_EN;
- set_cpacr(cpacr);
-}
-
int xnarch_fault_fpu_p(struct ipipe_trap_data *d)
{
return (d->exception == IPIPE_TRAP_FPU_ACC);
@@ -130,55 +123,17 @@ void xnarch_init_shadow_tcb(struct xnthread *thread)
tcb->fpup = &(tcb->core.host_task->thread.fpsimd_state);
xnthread_clear_state(thread, XNFPU);
}
-#endif /* CONFIG_XENO_ARCH_FPU */
-/* Switch support functions */
-static void xnarch_tls_thread_switch(struct task_struct *next)
-{
- unsigned long tpidr, tpidrro;
-
- if (!is_compat_task()) {
- asm("mrs %0, tpidr_el0" : "=r" (tpidr));
- current->thread.tp_value = tpidr;
- }
-
- if (is_compat_thread(task_thread_info(next))) {
- tpidr = 0;
- tpidrro = next->thread.tp_value;
- } else {
- tpidr = next->thread.tp_value;
- tpidrro = 0;
- }
-
- asm(
- " msr tpidr_el0, %0\n"
- " msr tpidrro_el0, %1"
- : : "r" (tpidr), "r" (tpidrro));
-}
-
-#ifdef CONFIG_PID_IN_CONTEXTIDR
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
- asm(
- " msr contextidr_el1, %0\n"
- " isb"
- :
- : "r" (task_pid_nr(next)));
-}
-#else
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
-}
-#endif
-/* End switch support functions */
+#endif /* CONFIG_XENO_ARCH_FPU */
void xnarch_switch_to(struct xnthread *out, struct xnthread *in)
{
struct xnarchtcb *out_tcb = &out->tcb, *in_tcb = &in->tcb;
struct mm_struct *prev_mm, *next_mm;
- struct task_struct *next;
+ struct task_struct *prev, *next;
next = in_tcb->core.host_task;
+ prev = out_tcb->core.host_task;
prev_mm = out_tcb->core.active_mm;
next_mm = in_tcb->core.mm;
@@ -198,18 +153,7 @@ void xnarch_switch_to(struct xnthread *out, struct
xnthread *in)
enter_lazy_tlb(prev_mm, next);
}
- xnarch_tls_thread_switch(in_tcb->core.tip->task);
- xnarch_contextidr_thread_switch(in_tcb->core.tip->task);
-
- /*
-* Complete any pending TLB or cache maintenance on this CPU in case
-* the thread migrates to a different CPU.
-*/
- dsb(ish);
-
- disable_fpsimd();
-
- cpu_switch_to(out_tcb->core.tip->task, in_tcb->core.tip->task);
+ __switch_to(prev, next);
}
int xnarch_escalate(void)
___
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[Xenomai-git] Philippe Gerum : cobalt/arm64: use regular context switching code
Module: xenomai-3
Branch: arm64
Commit: 44b42fbb03d60630d165954ff6949b3f10dcab96
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=44b42fbb03d60630d165954ff6949b3f10dcab96
Author: Philippe Gerum
Date: Sat Oct 17 18:07:59 2015 +0200
cobalt/arm64: use regular context switching code
Instead of open coding a copy of the regular context switching code,
use __switch_to() directly, assuming the pipeline properly serializes
switches from all domains.
---
kernel/cobalt/arch/arm64/thread.c | 66 +++--
1 file changed, 5 insertions(+), 61 deletions(-)
diff --git a/kernel/cobalt/arch/arm64/thread.c
b/kernel/cobalt/arch/arm64/thread.c
index 35dbd72..5282b0c 100644
--- a/kernel/cobalt/arch/arm64/thread.c
+++ b/kernel/cobalt/arch/arm64/thread.c
@@ -34,7 +34,7 @@
#include
#include
-#if defined(CONFIG_XENO_ARCH_FPU)
+#ifdef CONFIG_XENO_ARCH_FPU
#define FPSIMD_EN (0x3 << 20)
@@ -60,13 +60,6 @@ static void enable_fpsimd(void)
set_cpacr(cpacr);
}
-static void disable_fpsimd(void)
-{
- unsigned long cpacr = get_cpacr();
- cpacr &= ~FPSIMD_EN;
- set_cpacr(cpacr);
-}
-
int xnarch_fault_fpu_p(struct ipipe_trap_data *d)
{
return (d->exception == IPIPE_TRAP_FPU_ACC);
@@ -130,55 +123,17 @@ void xnarch_init_shadow_tcb(struct xnthread *thread)
tcb->fpup = &(tcb->core.host_task->thread.fpsimd_state);
xnthread_clear_state(thread, XNFPU);
}
-#endif /* CONFIG_XENO_ARCH_FPU */
-/* Switch support functions */
-static void xnarch_tls_thread_switch(struct task_struct *next)
-{
- unsigned long tpidr, tpidrro;
-
- if (!is_compat_task()) {
- asm("mrs %0, tpidr_el0" : "=r" (tpidr));
- current->thread.tp_value = tpidr;
- }
-
- if (is_compat_thread(task_thread_info(next))) {
- tpidr = 0;
- tpidrro = next->thread.tp_value;
- } else {
- tpidr = next->thread.tp_value;
- tpidrro = 0;
- }
-
- asm(
- " msr tpidr_el0, %0\n"
- " msr tpidrro_el0, %1"
- : : "r" (tpidr), "r" (tpidrro));
-}
-
-#ifdef CONFIG_PID_IN_CONTEXTIDR
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
- asm(
- " msr contextidr_el1, %0\n"
- " isb"
- :
- : "r" (task_pid_nr(next)));
-}
-#else
-static inline void xnarch_contextidr_thread_switch(struct task_struct *next)
-{
-}
-#endif
-/* End switch support functions */
+#endif /* CONFIG_XENO_ARCH_FPU */
void xnarch_switch_to(struct xnthread *out, struct xnthread *in)
{
struct xnarchtcb *out_tcb = &out->tcb, *in_tcb = &in->tcb;
struct mm_struct *prev_mm, *next_mm;
- struct task_struct *next;
+ struct task_struct *prev, *next;
next = in_tcb->core.host_task;
+ prev = out_tcb->core.host_task;
prev_mm = out_tcb->core.active_mm;
next_mm = in_tcb->core.mm;
@@ -198,18 +153,7 @@ void xnarch_switch_to(struct xnthread *out, struct
xnthread *in)
enter_lazy_tlb(prev_mm, next);
}
- xnarch_tls_thread_switch(in_tcb->core.tip->task);
- xnarch_contextidr_thread_switch(in_tcb->core.tip->task);
-
- /*
-* Complete any pending TLB or cache maintenance on this CPU in case
-* the thread migrates to a different CPU.
-*/
- dsb(ish);
-
- disable_fpsimd();
-
- cpu_switch_to(out_tcb->core.tip->task, in_tcb->core.tip->task);
+ __switch_to(prev, next);
}
int xnarch_escalate(void)
___
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