You are correct, but Pi2 runs at a higher voltage by default
which meant that force_turbo was incorrectly setting the
warranty bit. That was unintended.
The mailbox property interface to the gpu has a tag for VCMSG_SET_TURBO.
I wonder if doing it that way would bypass the warranty check?
Do the RPI2s break very fast or why is the warranty such an issue?
Not an issue for me - the pi is cheap enough that I consider it
essentially disposable, so I don't think twice about tinkering. But
since I was advising people to use turbo mode it seemed courteous
to mention the consequences.
On Sun, Feb 8, 2015 at 6:42 PM, erik quanstrom quans...@quanstro.net
wrote:
On Sun, Feb 8, 2015 at 6:27 PM, erik quanstrom quans...@quanstro.net
wrote:
am i reading the intel docs wrong, or is 6l missing a valid
instruction?
memmove5: doasm: notfound from=12 to=92 (47)CMOVQNE
at the risk of a second dumb question of the day, i'm looking at
MOVQQU -32(SI)(BX*1), X7
which generates the diagnostic
memmove4: doasm: notfound from=91 to=3b (220) [aname 666] -32(SI)(BX*1),X7
i tend to trust the compiler, but the verbage in the manual is a bit obtuse, and
i
On Sun, Feb 8, 2015 at 6:27 PM, erik quanstrom quans...@quanstro.net
wrote:
am i reading the intel docs wrong, or is 6l missing a valid instruction?
memmove5: doasm: notfound from=12 to=92 (47)CMOVQNE DX,(DI)
Go's liblink (which is derived from [5869]l) and cmd/6a support this
On Sun, Feb 8, 2015 at 6:27 PM, erik quanstrom quans...@quanstro.net
wrote:
am i reading the intel docs wrong, or is 6l missing a valid instruction?
memmove5: doasm: notfound from=12 to=92 (47)CMOVQNE DX,(DI)
Go's liblink (which is derived from [5869]l) and cmd/6a support this
On Sun Feb 8 15:31:26 PST 2015, don.bai...@gmail.com wrote:
Technically, there are a few instructions that the 9 compilers miss.
This is generally handled by the BYTE directive (see the asm manual).
Alternatively, adding a new instruction to the lexer/etc is fairly
trivial. See diffs
No. I just realized you want conditional move from DX to (DI).
It's an illegal combination. The intel document only lists three forms for
CMOVNE:
CMOVNE r16, r/m16 // CMOVWNE
CMOVNE r32, r/m32 // CMOVLNE
CMOVNE r64, r/m64 // CMOVQNE
All of them are conditionally moving from reg/mem to a
Ahh gotcha.
On Feb 8, 2015, at 4:37 PM, erik quanstrom quans...@quanstro.net wrote:
On Sun Feb 8 15:31:26 PST 2015, don.bai...@gmail.com wrote:
Technically, there are a few instructions that the 9 compilers miss.
This is generally handled by the BYTE directive (see the asm manual).
am i reading the intel docs wrong, or is 6l missing a valid instruction?
memmove5: doasm: notfound from=12 to=92 (47)CMOVQNE DX,(DI)
- erik
Technically, there are a few instructions that the 9 compilers miss. This is
generally handled by the BYTE directive (see the asm manual).
Alternatively, adding a new instruction to the lexer/etc is fairly trivial. See
diffs between vc and kc, for example.
D
On Feb 8, 2015, at 4:27 PM,
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