Re: [9fans] FP register usage in Plan9 assembler

> To that end, the Plan 9 syntax is fine for teaching assembler. And > so doing, a person is better able to write good C code. The only > disadvantage is when learning the assembler one has to translate front > the manufacturer's documentation and the Plan 9 standard syntax. I think too much

Re: [9fans] FP register usage in Plan9 assembler

> I think too much depends on the perception of a need to use assembly. > If you start from the assumption that assembly can be relegated to > pin-point optimisation on one hand and architecture-focused > instructions on the other, that leaves a huge space in the middle > where one can use a more

Re: [9fans] FP register usage in Plan9 assembler

> Or just how some architectures use typed registers, and some use > different-sized instruction variants. which architeture uses typed registers? a quick check of 386, 68020, alpha, arm, mips, power, power64, sparc, and amd64 shows all use MOV[WLQ]. - erik

Re: [9fans] FP register usage in Plan9 assembler

> I still quite like the distribution of work, for the reasons Aram just gave. > Latterly, I've been making the things a little smaller and perhaps simpler, > by continuing some changes that > Russ made (eg, pgen.c pswt.c) to reduce the amount of almost identical code > that's replicated across

Re: [9fans] FP register usage in Plan9 assembler

(Totally unrelated to the original post, but hey, we've already left that path, so why not?) Speaking of the Plan 9 toolchain, I much prefer the way it works internally compared to the Go toolchain because it is much easier to re-target. I haven't ported the Plan 9 toolchain (only saw Charles do

Re: [9fans] FP register usage in Plan9 assembler

On 4 February 2016 at 12:24, Brantley Coile wrote: > Which plan 9 assembler uses right to left argument assignments, or compare > argument order For example, the ARM's MCR and MRC instructions are unchanged from the manufacturer's order. Partly that's because the

Re: [9fans] FP register usage in Plan9 assembler

Brantley Coile wrote: > Which plan 9 assembler uses right to left argument assignments, > or compare argument order? The CMP order is different (at least) between power and arm64. This inconsistency is impossible to fix; I know because I tried to fix it in the SPARC64 Go

Re: [9fans] FP register usage in Plan9 assembler

To add some more on my previous post, yes, there are inconsistencies, but the common syntax still help tremendously, so much that translating between power and arm64 assembly has been mostly achieved through sam(1). -- Aram Hăvărneanu

Re: [9fans] FP register usage in Plan9 assembler

On February 4, 2016 6:04:49 AM CST, lu...@proxima.alt.za wrote: >> Plan 9 assembly is nice because it looks mostly the >> same, and the simple addressing modes are mostly consistent, but it's >> far from being really consistent between architectures. > >Personally, I agree with the view that

Re: [9fans] FP register usage in Plan9 assembler

Limbo is a contemporary of Java and it has several key features that Go and Java are known for; e.g. CSP and VM. The difference is that the level of awareness and experience of developers is higher now than it was then. Sadly, Inferno and Limbo are still underrated today. On Thu, Feb 4, 2016 at

Re: [9fans] FP register usage in Plan9 assembler

On 4 February 2016 at 15:22, erik quanstrom wrote: > MOVQQU or MOVQQA still follow the expected pattern. Originally on amd64 I consistently used O instead of sometimes DQ and sometimes O as Intel did, but in the end I changed them back to the Intel names, since it was

Re: [9fans] FP register usage in Plan9 assembler

> *cough* that's what people said about Java *cough* What, that Java does what it says on the tin? Which tin? Lucio.

Re: [9fans] FP register usage in Plan9 assembler

On February 4, 2016 10:09:49 AM CST, lu...@proxima.alt.za wrote: >> *cough* that's what people said about Java *cough* > >What, that Java does what it says on the tin? Which tin? Almost forgot: The AbstractBeanPartAluminumRecyclableTinFactory that makes AbstractPartAluminumRecyclableTinLists,

Re: [9fans] FP register usage in Plan9 assembler

On February 4, 2016 10:09:49 AM CST, lu...@proxima.alt.za wrote: >> *cough* that's what people said about Java *cough* > >What, that Java does what it says on the tin? Which tin? > cross-platform development tool >Lucio. -- Sent from my Nexus 5 with K-9 Mail. Please excuse my brevity.

Re: [9fans] FP register usage in Plan9 assembler

go without the packages will be as useful as java without class libraries. nothing. i'm happy they understood the table stakes for a new software/application development language. i can also see why they bundled all the compilation stages into one -- script kiddies don't do make files On Thu, Feb

Re: [9fans] FP register usage in Plan9 assembler

> > MOVQQU or MOVQQA still follow the expected pattern. > > > > Originally on amd64 I consistently used O instead of sometimes DQ and > sometimes O as Intel did, but in the end I changed them back to the > Intel names, since it was hard to look them up, and there were so > many. ack. typo in

Re: [9fans] FP register usage in Plan9 assembler

On Tue Feb 2 08:43:47 PST 2016, sstall...@gmail.com wrote: > Hi Giacomo, > > It's probably worth mentioning that learning assembly using the Plan 9 > assembler is probably a bad idea. *a makes heavy use of pseudo > instructions and registers and unless you're well versed in its > quirks, can be

Re: [9fans] FP register usage in Plan9 assembler

On Wed, Feb 3, 2016 at 9:24 AM, erik quanstrom wrote: > i think this is off the original point, but as to modifying the assmbler. > to add a new instruction, the linker, assembler and libmach need modification. > typically this is a matter of adding a line to each one for

Re: [9fans] FP register usage in Plan9 assembler

> WRT to drawbacks in the loader for writing assembly, one of the > biggest problems is merciless optimization that cannot be disabled on > a per translation-unit basis (we're using a loader, remember?) As an > example, it's damned near impossible to perform PC-relative branching > in the vector

Re: [9fans] FP register usage in Plan9 assembler

Hi Giacomo, It's probably worth mentioning that learning assembly using the Plan 9 assembler is probably a bad idea. *a makes heavy use of pseudo instructions and registers and unless you're well versed in its quirks, can be very confusing when looking at more common assembly dialects. Many

Re: [9fans] FP register usage in Plan9 assembler

Yes, on Plan 9, on amd64, only one register is used (as explained by Charles). Go doesn't use any registers for argument passing (even on Plan 9). You can just run 6c -S to see these things yourself. -- Aram Hăvărneanu

[9fans] FP register usage in Plan9 assembler

I'm studying the 9front's amd64 kernel, and I'm pretty new to assembler programming, so sorry if my question is too dumb... I cannot understand the FP pseudo register usage. The cpuid function, for example, is implemented as /* * The CPUID instruction is always supported on the amd64. */ TEXT

Re: [9fans] FP register usage in Plan9 assembler

Thanks for the explainations! I did read in the Pike's paper about the syntax name+offset(FP), but I did understood that name had to be a symbol already defined, and I was looking for it in the c code. Sorry for the noise! This led me to another question, however: I've read before that the plan9

Re: [9fans] FP register usage in Plan9 assembler

On 1 February 2016 at 16:47, Giacomo Tesio wrote: > MOVQinfo+8(FP), BP > MOVLAX, 0(BP) > MOVLBX, 4(BP) > MOVLCX, 8(BP) > MOVLDX, 12(BP) > RET > > What I miss is where "info" comes from. > the syntax name+offset(FP) defines name as

Re: [9fans] FP register usage in Plan9 assembler

FP is a translated to a varying offset to SP depending on where in the program you are. arguments on the stack are padded to 8 bytes on amd64, the first argument is not passed on the stack on function entry, but passed in BP register (RARG is an alias for that), however the slot on the stack for

Re: [9fans] FP register usage in Plan9 assembler

On 1 February 2016 at 23:34, Giacomo Tesio wrote: > > Is it correct to say that this means that the Plan9 compiler suite *never* > follows the sysV calling convention documented at section 3.2.3 of AMD64 > ABI http://www.x86-64.org/documentation/abi.pdf and always pushes >

Re: [9fans] FP register usage in Plan9 assembler

I kinda agree, but I'm too incompetent in the matter. :-) However, I was simply asking if, on amd64, kencc uses the 6 registers that the abi deserves to the parameters. As far as I've understood only BP is used (for the first argument, if integer). Can you confirm? Giacomo 2016-02-02 1:36