the astounding thing is that t1-t0 is often ~ 60,000 cycles.
it only hits a small fraction of the time, and the average is
much lower. but that just blows the mind. 6 cycles!
(other versions with sched were much worse.)
as far as i can tell, there are no funny bits in the
On Fri Jun 20 01:04:20 EDT 2014, devon.od...@gmail.com wrote:
Weird. I assume cycles is using rdtsc or rdtscp. Perhaps some of it is due
to a combination of contention and rdtsc(p) being serializing instructions?
On Jun 19, 2014 12:04 PM, erik quanstrom quans...@quanstro.net wrote:
other than
2014-06-20 7:50 GMT-04:00 erik quanstrom quans...@quanstro.net:
On Fri Jun 20 01:04:20 EDT 2014, devon.od...@gmail.com wrote:
Weird. I assume cycles is using rdtsc or rdtscp. Perhaps some of it is due
to a combination of contention and rdtsc(p) being serializing instructions?
I forget that
It disables out-of-order execution by the processor, so there's a
pipeline stall.
we know there's going to be a stall already, since we can't get
the cacheline we're looking for.
There's overhead to calling the tsc instructions, but not that much.
Does `srb-wmach != m-machno` imply that t0
i'm seeing some mighty interesting timing on my intel ivy bridge.
i found a bug in the file server aoe implementation (can't happen
if you're using the uniprocessor x86 version) that happens because
the Srb is freed before wakeup completes. to solve this there is
some code that sets the state
Weird. I assume cycles is using rdtsc or rdtscp. Perhaps some of it is due
to a combination of contention and rdtsc(p) being serializing instructions?
On Jun 19, 2014 12:04 PM, erik quanstrom quans...@quanstro.net wrote:
i'm seeing some mighty interesting timing on my intel ivy bridge.
i found
On Thu, 19 Jun 2014 12:01:10 EDT erik quanstrom quans...@quanstro.net wrote:
i'm seeing some mighty interesting timing on my intel ivy bridge.
i found a bug in the file server aoe implementation (can't happen
if you're using the uniprocessor x86 version) that happens because
the Srb is freed
